- 13 8月, 2015 40 次提交
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由 Tom Rini 提交于
- Import various DT files for DRA7 / DR72x / dra72-evm from Linux Kernel v4.1 - Add config file for this board, enable DM and DM_GPIO Cc: Simon Glass <sjg@chromium.org> Signed-off-by: NTom Rini <trini@konsulko.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Tom Rini 提交于
- Move the CONS_INDEX selection out of CONFIG_SYS_EXTRA_OPTIONS and into Kconfig proper. - While in here, enable CONFIG_SPL_STACK_ADDR Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Tom Rini 提交于
We now have the CONFIG_SPL_DM for code within SPL to toggle caring about DM or not. Without this change platforms that do enable CONFIG_DM but not CONFIG_SPL_DM may be broken (such as OMAP5). Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Tom Rini 提交于
The "method" parameter was part of the original port of the driver from the kernel. At some point this may have been added to allow for future differentiation (as omap1 and omap2 have different GPIO IP blocks, so this wasn't an unreasonable thing to do). At this point however it's just extra overhead, so drop. Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Tom Rini 提交于
- Re-sync DT files for am33xx with Linux Kernel v4.1 - Include DT file now for the "AM335x GP EVM" and build target for it, via device tree and DM. - We only need to provide platform data for UART when OF_CONTROL isn't also enabled really. We can just push GPIO to coming from DT Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Nikita Kiryanov 提交于
Add initial support for CM-T43, an AM437x based SoM. This support includes: serial, MMC/eMMC, NAND, USB, ETH, I2C, GPIO, DRAM detection. Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il>
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由 Nikita Kiryanov 提交于
AM43XX SoCs support up to 192 GPIO signals. Make this amount available to the driver. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il>
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由 Nikita Kiryanov 提交于
Enable 8bit interface on HSMMC2 for am43xx to support 8bit eMMC chips. Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il>
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由 Nikita Kiryanov 提交于
The CMD(DAT) lines reset procedure described in the OMAP4(AM335x, OMAP5, DRA7xx) TRMs is also necessary for AM43XX. Enable it in the driver. Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il>
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由 Nikita Kiryanov 提交于
Add spi clock to the list of am43xx basic clocks to make the SPI subsystem available on am43xx systems. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Nikita Kiryanov 提交于
Add support for AM43XX to the omap3_spi driver. Cc: Jagan Teki <jteki@openedev.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Peter Griffin 提交于
To help others with compiling and flashing ATF and u-boot add a README for this board. Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
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由 Peter Griffin 提交于
HiKey is the first 96boards consumer edition compliant board. It features a hi6220 SoC which has eight ARM A53 cpu's. This initial port adds support for: - 1) Serial 2) eMMC / SD card 3) USB 4) GPIO It has been tested with Arm Trusted Firmware running u-boot as the BL33 executable. Notes: eMMC has been tested with basic reading of eMMC partition into DDR. I have not tested writing / erasing. Due to lack of clock control it won't be running in the most performant high speed mode. SD card slot has been tested for reading and booting kernels into DDR. It is also currently configured to save the u-boot environment to the SD card. USB has been tested with ASIX networking adapter to tftpboot kernels into DDR. On v2015.07-rc2 dhcp now works, and also USB mass storage are correctly enumerated. GPIO has been tested using gpio toggle GPIO4_1-3 to flash the LEDs. Basic SoC datasheet can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ Hi6220V100_Multi-Mode_Application_Processor_Function_Description.pdf Board schematic can be found here: - https://github.com/96boards/documentation/blob/master/hikey/ 96Boards-Hikey-Rev-A1.pdf Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
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由 Peter Griffin 提交于
This patch adds the glue code for hi6220 SoC which has 2x synopsis dw_mmc controllers. This will be used by the hikey board support in subsequent patches. Signed-off-by: NPeter Griffin <peter.griffin@linaro.org> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Peter Griffin 提交于
This adds a simple pmic driver for the hi6553 pmic which is used in conjunction with the hi6220 SoC on the hikey board. Eventually this driver will be updated to be a proper UCLASS PMIC driver which can parse the voltages direct from device tree. Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
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由 Peter Griffin 提交于
This patch adds basic pinmux support for the hi6220 SoC, which is found on the hikey board. Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
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由 Peter Griffin 提交于
This patch adds the header files which will be used in the subsquent board / drivers to enable support for hi6220 hikey board. Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
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由 Peter Griffin 提交于
This patch adds support for the GPIO perif found on hi6220 SoC. Signed-off-by: NPeter Griffin <peter.griffin@linaro.org>
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由 Gong Qianyu 提交于
Modify the data pointer type from ulong* to u32*. For arm64 type "ulong" could be 64-bit. Then in line 89 of common/cmd_source.c: "while (*data++);" data will point to the next 64 bits each time. As the uImage file generated by mkimage tool keeps the same data format in either 32-bit or 64-bit platform, the difference would cause failure in 64-bit platform. Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
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由 Gong Qianyu 提交于
Make the cast explicit for "warning: cast to pointer from integer of different size". Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
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由 Måns Rullgård 提交于
The semantics for non-static functions declared inline have changed in gcc5, causing the empty functions not to be emitted as an external symbol. Since lowlevel_init() is only referenced from start.S, it should not be declared inline at all. Reported-by: NOtavio Salvador <otavio@ossystems.com.br> Tested-by: NOtavio Salvador <otavio@ossystems.com.br> [trini: Reword commit message] Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Lokesh Vutla 提交于
Since all the clocks are defined common, and has the same logic to get the frequencies, use a common definition for for clk_get_rate(). Reviewed-by: NTom Rini <trini@konsulko.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
Remove unused external clocks and make a common definition for all keystone platforms. Reviewed-by: NTom Rini <trini@konsulko.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
This is just a cosmetic change that makes the calling of pll init code looks much cleaner. Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NVitaly Andrianov <vitalya@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
Register Base addresses are same for PLLs in all keystone platforms. If a PLL is not available, the corresponding register addresses are marked as reserved. Hence use a common definition. Reviewed-by: NTom Rini <trini@konsulko.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
Use common devspeed and armspeed definitions. Also fix reading efuse bootrom register. Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NVitaly Andrianov <vitalya@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
There are two types of PLL for all keystone platforms: Main PLL, Secondary PLL. Instead of duplicating the same definition for each secondary PLL, have a common function which does initialization for both PLLs. And also add proper register definitions. Reviewed-by: NTom Rini <trini@konsulko.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
Add print_cpuinfo() function and enable CONFIG_DISPLAY_CPUINFO for keystone platforms, so that cpu info can be displayed during boot. Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NVitaly Andrianov <vitalya@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Lokesh Vutla 提交于
Add proper register definition for JTAG ID and cleanup cpu_is_* functions. Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NVitaly Andrianov <vitalya@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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由 Nishanth Menon 提交于
DRA72x processor variants are single core and it does not export ACP[1]. Hence, we have no source for generating an external snoop requests which appear to be key to the deadlock in DRA72x design. Since we build the same image for DRA74x and DRA72x platforms, lets runtime detect and disable the workaround (in favor of performance) on DRA72x platforms. [1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438i/BABIAJAG.htmlSuggested-by: NRichard Woodruff <r-woodruff2@ti.com> Suggested-by: NBrad Griffis <bgriffis@ti.com> Reviewed-by: NBrad Griffis <bgriffis@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com>
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由 Nishanth Menon 提交于
Implement logic for ACR(Auxiliary Control Register) configuration using ROM Code smc service. Suggested-by: NRichard Woodruff <r-woodruff2@ti.com> Suggested-by: NBrad Griffis <bgriffis@ti.com> Reviewed-by: NBrad Griffis <bgriffis@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com>
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由 Nishanth Menon 提交于
Add workaround for Cortex-A15 ARM erratum 801819 which says in summary that "A livelock can occur in the L2 cache arbitration that might prevent a snoop from completing. Under certain conditions this can cause the system to deadlock. " Recommended workaround is as follows: Do both of the following: 1) Do not use the write-back no-allocate memory type. 2) Do not issue write-back cacheable stores at any time when the cache is disabled (SCTLR.C=0) and the MMU is enabled (SCTLR.M=1). Because it is implementation defined whether cacheable stores update the cache when the cache is disabled it is not expected that any portable code will execute cacheable stores when the cache is disabled. For implementations of Cortex-A15 configured without the “L2 arbitration register slice” option (typically one or two core systems), you must also do the following: 3) Disable write-streaming in each CPU by setting ACTLR[28:25] = 0b1111 So, we provide an option to disable write streaming on OMAP5 and DRA7. It is a rare condition to occur and may be enabled selectively based on platform acceptance of risk. Applies to: A15 revisions r2p0, r2p1, r2p2, r2p3 or r2p4 and REVIDR[3] is set to 0. Note: certain unicore SoCs *might* not have REVIDR[3] not set, but might not meet the condition for the erratum to occur when they donot have ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency Extensions). Such SoCs will need the work around handled in the SoC specific manner, since there is no ARM generic manner to detect such configurations. Based on ARM errata Document revision 18.0 (22 Nov 2013) Suggested-by: NRichard Woodruff <r-woodruff2@ti.com> Suggested-by: NBrad Griffis <bgriffis@ti.com> Reviewed-by: NBrad Griffis <bgriffis@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com>
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由 Linus Walleij 提交于
This switches the Integrator boards over to using the device model for its serial ports. Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
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由 Wu, Josh 提交于
Remove the CONFIG_DM_USB limitation to enable cache support functions. Tested on SAMA5D3x-EK board. Signed-off-by: NJosh Wu <josh.wu@atmel.com> Acked-by: NHans de Goede <hdegoede@redhat.com>
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由 Wu, Josh 提交于
Current many cpu use the same flush_cache() function, which just call the flush_dcache_range(). So implement a weak flush_cache() for all the cpus to use. In original weak flush_cache() in arch/arm/lib/cache.c, there has some code for ARM1136 & ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache() function as well. That means the original code for ARM1136 & ARM926ejs in weak flush_cache() of arch/arm/lib/cache.c is totally useless. So in this patch remove such code in flush_cache() and only call flush_dcache_range(). Signed-off-by: NJosh Wu <josh.wu@atmel.com>
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由 Wu, Josh 提交于
Since some driver like ohci, lcd used dcache functions. But some ARM cpu don't implement the invalidate_dcache_range()/flush_dcache_range() functions. To avoid compiling errors this patch adds an weak empty stub function for all ARM cpu in arch/arm/lib/cache.c. And ARM cpu still can implemnt its own cache functions on the cpu folder. Signed-off-by: NJosh Wu <josh.wu@atmel.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Wu, Josh 提交于
Since some driver like ohci, lcd used dcache functions. But m68k don't implement the invalidate_dcache_range()/flush_dcache_range() functions. To avoid compiling errors this patch adds an weak empty stub function for all m68k cpu. Also each cpu can implement its own implementation. If not implemented then by default is using an empty function. Signed-off-by: NJosh Wu <josh.wu@atmel.com> Acked-by: NAngelo Dureghello <angelo@sysam.it>
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由 Ruchika Gupta 提交于
gpio.h - Added missing copyright in few files. rsa-mod-exp.h - Corrected copyright in the file. fsl_sec.h - Added missing license in files drivers/crypto/fsl/Makefile - Removed the incomplete GPLv2 license and replaced it with GPLv2+ license Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com>
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由 Stefano Babic 提交于
Signed-off-by: NStefano Babic <sbabic@denx.de> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Stefano Babic 提交于
Signed-off-by: NStefano Babic <sbabic@denx.de> Reviewed-by: NTom Rini <trini@konsulko.com>
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