ARM: DRA7/ OMAP5: implement Auxiliary Control Register configuration

Implement logic for ACR(Auxiliary Control Register) configuration using
ROM Code smc service.
Suggested-by: NRichard Woodruff <r-woodruff2@ti.com>
Suggested-by: NBrad Griffis <bgriffis@ti.com>
Reviewed-by: NBrad Griffis <bgriffis@ti.com>
Signed-off-by: NNishanth Menon <nm@ti.com>

arch/arm/cpu/armv7/omap5/hwinit.c

@@ -418,3 +418,9 @@ void v7_arch_cp15_set_l2aux_ctrl(u32 l2auxctrl, u32 cpu_midr,
 {
 	omap_smc1(OMAP5_SERVICE_L2ACTLR_SET, l2auxctrl);
 }
+
+void v7_arch_cp15_set_acr(u32 acr, u32 cpu_midr, u32 cpu_rev_comb,
+			  u32 cpu_variant, u32 cpu_rev)
+{
+	omap_smc1(OMAP5_SERVICE_ACR_SET, acr);
+}

arch/arm/include/asm/arch-omap5/sys_proto.h

@@ -81,5 +81,6 @@ static inline u32 usec_to_32k(u32 usec)
 }
 
 #define OMAP5_SERVICE_L2ACTLR_SET    0x104
+#define OMAP5_SERVICE_ACR_SET        0x107
 
 #endif