Signed-off-by: NLuka Perkov <luka@openwrt.org>
CC: Prafulla Wadaskar <prafulla@marvell.com>
Acked-By: NPrafulla Wadaskar <prafulla@marvell.com>

Conflicts:
	include/micrel.h

The conflict above was trivial, caused by four lines being
added in both branches with different whitepace.

Enable fuse supply before fuse programming and disable after.
Signed-off-by: NSergey Alyoshin <alyoshin.s@gmail.com>
Reviewed-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

The enable_fec_anatop_clock method should be available for all MX6
variant as it is not MX6 SoloLite specific. This moves the code out of
the #ifdef/#endif and we make it conditional to CONFIG_FEC_MXC
instead.
Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>
Acked-by: NStefano Babic <sbabic@denx.de>

This patch fixes allow for the DeviceTree and initrd relocation fixing
the boot of FSL 3.10.9-1.0.0-alpha kernel.

This changes following boards:

 - mx6sabreauto
 - mx6sabresd
 - wandboard
 - udoo
 - nitrogen6x
 - cgtqmx6eval

The reasoning, as explained by Hui Liu, is:

,----
| The FDT blob will be placed at DDR physical addr: 0x11000000. When Linux kernel
| Boot up, it will decompress the compressed kernel image and place the decompressed
| kernel image at the low end of the DDR memory and start running from it. If the
| decompressed kernel image is bigger for example than 16M, it may over written the
| fdt blob which u-boot loaded to the DDR memory @0x11000000 with fdt_addr=0x11000000
|
| To expand the fdt_addr from 0x11000000 to 0x18000000, which can avoid the override
| Since we will not likely have one kernel image larger than 128MB.
`----
Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>
Acked-by: NStefano Babic <sbabic@denx.de>

This adds following new targets:

 - update_nand_kernel
 - update_nand_fdt
 - update_nand_filesystem

and to avoid confusion, the 'update_nand_full' has been renamed to
'update_nand_firmware_full'.
Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>

This reads the kernel, ftd and boot into ubifs filesystem. While on
that, the SD firmware filename definition has been moved next to the
other SD related commands.
Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>
Reviewed-by: NFabio Estevam <fabio.estevam@freescale.com>

Using 512k for fdt partition allow it to be aligned with the other
small partitions and 512k erase block size.
Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>
Acked-by: NStefano Babic <sbabic@denx.de>

The macro allows easy setting in per-pin, as for example:

,----
| imx_iomux_v3_setup_pad(MX6_PAD_NANDF_D1__GPIO_2_1 | MUX_MODE_SION);
`----

The IOMUX_CONFIG_SION allows for reading PAD value from PSR register.

The following quote from the datasheet:

,----
| ...
| 28.4.2.2 GPIO Write Mode
| The programming sequence for driving output signals should be as follows:
| 1. Configure IOMUX to select GPIO mode (Via IOMUXC), also enable SION if need
| to read loopback pad value through PSR
| 2. Configure GPIO direction register to output (GPIO_GDIR[GDIR] set to 1b).
| 3. Write value to data register (GPIO_DR).
| ...
`----

This fixes the gpio_get_value to properly work when a GPIO is set for
output and has no conflicts.

Thanks for Benoît Thébaudeau <benoit.thebaudeau@advansee.com>, Fabio
Estevam <fabio.estevam@freescale.com> and Eric Bénard
<eric@eukrea.com> for helping to properly trace this down.
Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>
Acked-by: NStefano Babic <sbabic@denx.de>

As U-boot does not use GPU/VPU peripherals, shutdown the VDDPU regulator
in order to save power.
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NJason Liu <r64343@freescale.com>
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

When changing LDO voltages we need to wait for the required amount of time
for the voltage to settle.

Also, as the timer is still not available when arch_cpu_init() is called, we
need to call it later at board_postclk_init() phase.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Introduce set_ldo_voltage() so that all three LDO regulators can be configured.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

mx6 datasheet specifies that the minimum VDDSOC at 792 MHz is 1.15 V.
Add a 25 mV margin and set it to 1.175V.

This also matches the VDDSOC voltages for 792MHz operation that the kernel configures:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/arch/arm/mach-mx6/cpu_op-mx6.c?h=imx_3.0.35_4.1.0Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Since ROM may modify the LDO ramp up time according to fuse setting,
it is safer to reset the ramp up field to its default value of 00:

00: 64 cycles of 24MHz clock;
01: 128 cycles of 24MHz clock;
02: 256 cycles of 24MHz clock;
03: 512 cycles of 24MHz clock;
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NJason Liu <r64343@freescale.com>
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

set_vddsoc() is not used anywhere else, so make it static.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Add CONFIG_CMD_FUSE option, so that the fuse API can be used.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

When using the fuse API in U-boot user must calculate the 'bank' and 'word'
values.

Provide a real example on how to calculate such values for the mx6q.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>

This patch add uuid disk to defualt partions necessary to
restore gpt partitions and fixes mmcdev environmental variable.
Signed-off-by: NPiotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

This fix is necessary after increased by one the number
of adapters in s3c24x0 driver.

Tested on Trats and Trats2.
Signed-off-by: NPiotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

When variable size SPL is used, the BL1 expects the SPL to be
encapsulated differently: instead of putting the checksum at a fixed
offset in the SPL blob, prepend the blob with a header including the
size and the checksum.

The enhancements include
	- adding a command line option, '--vs' to indicate the need for the
	variable size encapsulation
	- padding the fixed size encapsulated blob with 0xff instead of random
	memory contents
	- do not silently truncate the input file, report error instead
	- no need to explicitly closing files/freeing memory, this all happens
	on exit; removing cleanups it makes code clearer
	- profuse commenting
	- modify Makefile to allow enabling the new feature per board
Signed-off-by: NVadim Bendebury <vbendeb@chromium.org>
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Adding initial config for SMDK5420 to build and boot U-Boot
over Exynos based SMDK5420.
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

This patch adds dts support for SMDK5420.
exynos5.dtsi created is a common file which has the nodes common
to both 5420 and 5250.
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Adding the base patch for Exynos based SMDK5420.
This shall enable compilation and basic boot support for
SMDK5420.
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Adds code in pinmux and gpio framework to support Exynos5420.
Signed-off-by: NNaveen Krishna Chatradhi <ch.naveen@samsung.com>
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

This patch intends to add DDR3 initialization code for Exynos5420.
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

This patch adds code for clock initialization and clock settings
of various IP's and controllers, required for Exynos5420
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Add dmc and phy_control register structure for 5420.
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Add structure for power register for Exynos5420
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Adds base addresses of various IPs and controllers required for
Exynos5420.
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Signed-off-by: NAkshay Saraswat <akshay.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Create a common board.c file for all functions which are common across
all EXYNOS5 platforms.

exynos_init function is provided for platform specific code.
Signed-off-by: NRajeshwari S Shinde <rajeshwari.s@samsung.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Commit 164d9846 breaks
board with SATA support, because sata is not compiled.
Signed-off-by: NStefano Babic <sbabic@denx.de>

Adding Maintainer for AM43xx.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH).
Adding details for the same.
Below is the brief description of DDR3 init sequence(SW leveling):
-> Enable VTT regulator
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program leveling registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A)
Adding LPDDR2 init sequence and register details for the same.
Below is the brief description of LPDDR2 init sequence:
-> Configure VTP
-> Configure DDR IO settings
-> Disable initialization and refreshes until EMIF registers are programmed.
-> Program Timing registers
-> Program PHY control and Temp alert and ZQ config registers.
-> Enable initialization and refreshes and configure SDRAM CONFIG register
-> Wait till initialization is complete and the configure MR registers.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Currently same value is programmed for all ioregs. This is not
the case for all SoC's like AM4372. So adding a structure for ioregs
and updating in all board files. And also return from config_cmd_ctrl()
and config_ddr_data() functions if data is not passed.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
[trini: Fixup dxr2, cm_t335, adapt pcm051 rev3]
Signed-off-by: NTom Rini <trini@ti.com>

Updating the Multiplier and Dividers value for all DPLLs.
Safest OPP is read from DEV ATTRIBUTE register. Accoring to the value
returned the MPU DPLL is locked.
At different OPPs follwoing are the MPU locked frequencies.
OPP50	300MHz
OPP100	600MHz
OPP120	720MHz
OPPTB	800MHz
OPPNT	1000MHz
According to the latest DM following is the OPP table dependencies:
	VDD_CORE 	VDD_MPU
	OPP50		OPP50
	OPP50 		OPP100
	OPP100		OPP50
	OPP100		OPP100
	OPP100		OPP120
So at different OPPs of MPU it is safest to lock CORE at OPP_NOM.
Following are the DPLL locking frequencies at OPP NOM:
Core locks at 1000MHz
Per locks at 960MHz
LPDDR2 locks at 266MHz
DDR3 locks at 400MHz

Touching AM33xx files also to get DPLL values specific to board but no
functionality difference.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Updating the mux data for UART, adding data for i2c0 and mmc.
And also updating pad_signals structure.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Current Booting devices list is different from that of AM33xx.
Updating the same.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Selecting the Master osc clk as Timer2 clock source.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>