Lets add the necessary DTS node and pinctrl properties for newly added MDIO driver.
Signed-off-by: NRobert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>

Since we have SPI driver for IPQ40xx QUP SPI controller, lets add the necessary nodes, pinctrl and clocks.
Signed-off-by: NRobert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>

As the ownership is now Hitachi Power Grids, change the license string
and adapt the compatible string in DTS files. For kmeter1.dts we
change it to "keymile,KMETER1" for now, as this is then compliant with
what is submitted to the linux kernel. All other boards don't have
a upstreamed version in linux mainline.
Signed-off-by: NHolger Brunck <holger.brunck@hitachi-powergrids.com>
CC: Valentin Longchamp <valentin.longchamp@hitachi-powergrids.com>
CC: Heiko Schocher <hs@denx.de>
CC: Marek Vasut <marex@denx.de>
CC: Tom Rini <trini@konsulko.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

No timer drivers return an error from get_count. Instead of possibly
returning an error, just return the count directly.
Signed-off-by: NSean Anderson <seanga2@gmail.com>
Reviewed-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

When partitions are not available on a device the command stm32prog raises
an error but a device can have no partition to check in init_device()
and the command need to continue to the next part_id.

This patch correct an issue for ram0 target, when block_dev and mtd
are NULL.

For example with the simple flashlayout file:

Opt	Part	Name	Type	Device	Offset	Binary
-	0x01	fsbl	Binary	none	0x0	tf-a-serialboot.stm32
-	0x03	ssbl	Binary	none	0x0	u-boot.stm32
P	0x10	kernel	System	ram0	0xC2000000	uImage.bin
P	0x11	dtb	FileSytem	ram0	0xC4000000	stm32mp157f-ev1.dtb

Fixes: ffc405e6 ("stm32mp: stm32prog: add upport of partial update")
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>

Cosmetic update of gpio.h:
- remove enumerate: stm32_gpio_port, stm32_gpio_pin
  because STM32_GPIO_XXX values are unused
- move STM32_GPIOS_PER_BANK in stm32_gpio.c
  as its value is IP dependent and not arch dependent

No functional change as number of banks and number of gpio by banks
is managed by device tree since since DM migration and
commit 8f651ca6 ("pinctrl: stm32: Add get_pins_count() ops").
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>

In pre-reloc stage, U-Boot marks cacheable the DDR limited by
the new config CONFIG_DDR_CACHEABLE_SIZE.

This patch allows to avoid any speculative access to DDR protected by
firewall and used by OP-TEE; the "no-map" reserved memory
node in DT are assumed after this limit:
STM32_DDR_BASE + DDR_CACHEABLE_SIZE.

Without security, in basic boot, the value is equal to STM32_DDR_SIZE.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>

An earlier conversion from struct to defines introduced two errors, both
related to setup of EMAC routed via the FPGA. One of the offsets was
incorrect, and the EMAC0/EMAC1 were swapped.

The effect of this was rather odd: both ports could operate at gigabit,
but one of them would fail to transmit when operating at 100Mbit.

Fixes: db5741f7 ("arm: socfpga: Convert system manager from struct to defines")
Signed-off-by: NRalph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: NLey Foon Tan <ley.foon.tan@intel.com>

Import RZ/G2E (R8A774C0) clock tables from Linux 5.9 commit
bbf5c979011a ("Linux 5.9").
Signed-off-by: NLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: NBiju Das <biju.das.jz@bp.renesas.com>

This sync's the RZ/G2H clock tables with mainline linux 5.9 commit
bbf5c979011a ("Linux 5.9").
Signed-off-by: NBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: NLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

This sync's the RZ/G2N clock tables with mainline linux 5.9 commit
bbf5c979011a ("Linux 5.9").
Signed-off-by: NBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: NLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Import R8A774C0 (RZ/G2E) SoC DTSI and headers from Linux 5.9
commit bbf5c979011a ("Linux 5.9").
Signed-off-by: NLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: NBiju Das <biju.das.jz@bp.renesas.com>

Add config support for RZ/G2E (a.k.a R8A774C0) SoC.
Signed-off-by: NLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: NBiju Das <biju.das.jz@bp.renesas.com>

Add config support for RZ/G2H(a.k.a R8A774E1) SoC.
Signed-off-by: NBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: NLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add config support for RZ/G2N(a.k.a R8A774B1) SoC.

Also fixed the alignment issue on R8A774A1 config.
Signed-off-by: NBiju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: NLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add usb, usb phy, and fixed regulators nodes
Signed-off-by: NChunfeng Yun <chunfeng.yun@mediatek.com>
Acked-by: NBin Meng <bmeng.cn@gmail.com>

SAM9X60 SiP (System in Package) are added for SoC identification.
Signed-off-by: NNicolas Ferre <nicolas.ferre@microchip.com>

Use alphabetical order for entries in sam9x60ek-u-boot.dtsi
Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>

Use CCF compatible for PMC. With this, the board/SoC will be
able to boot.
Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>

Use slow clock CCF compatible DT bindings. This will not break
the above functionality as the SoC is not booting with current
PMC bindings.
Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>

Use u-boot,dm-pre-reloc for slow xtal and main xtal.
Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>

Slow Xtal and Main Xtal are board specific. Add their proper
frequency to board file.
Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>

Necessary for dev_xxx.
Signed-off-by: NTom Rini <trini@konsulko.com>

Clock support is needed for all Octeon TX/TX2 boards. This patch selects
CONFIG_CLK so that it is available.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Suneel Garapati <sgarapati@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>

The EFI_RNG_PROTOCOL is needed for address randomization in Linux.
We should provide it by default on QEMU.
Reported-by: NFrançois Ozog <francois.ozog@linaro.org>
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

Using different strings for the device tree node labels and the label
property of buttons sharpens the button label unit test.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: NPhilippe Reynes <philippe.reynes@softathome.com>

Import armada-3720-espressobin-emmc.dts from Linux, but use sdhc1 for
emmc, since our dtsi is still based on downstream and sdhc0 is used for
the sd card.
Signed-off-by: NAndre Heider <a.heider@gmail.com>

Move most of the dts to the new common armada-3720-espressobin.dtsi
file, just like Linux, but keep the current, downstream based, version.

The dts itself is imported from Linux.
Signed-off-by: NAndre Heider <a.heider@gmail.com>

Fix the actual board vendor and ease synching dts files from Linux.
Signed-off-by: NAndre Heider <a.heider@gmail.com>
Reviewed-by: NPali Rohár <pali@kernel.org>
Reviewed-by: NStefan Roese <sr@denx.de>

Add initial U-Boot support for the iEi Puzzle-M801 board based on the
Marvell Armada 88F8040 SoC.

Currently supported hardware:
1x USB 3.0
4x Gigabit Ethernet
2x SFP+ (with NXP PCA9555 and NXP PCA9544)
1x SATA 3.0
1x M.2 type B
1x RJ45 UART
1x SPI flash
1x EPSON RX8010 RTC
Signed-off-by: NLuka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: NStefan Roese <sr@denx.de>

Add properties related to eMMC HS400 mode.

mmc-hs400-1_8v;
bus-width = <8>;

They had been already in kernel dts file since the first
lx2160ardb dts patch.

b068890 arm64: dts: add LX2160ARDB board support
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>

Move to use generic handoff dtsi (socfpga_arria10-handoff.dtsi) and include
the specify generated _handoff.h header file from qts-filter-a10.sh script.
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Add the qts-filter-a10.sh generated handoff header file for the Arria10
SoCDK SDMMC u-boot device tree.
Signed-off-by: NDalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Add a script to process HPS handoff data and generate a header
for inclusion in u-boot specific devicetree addons. The header
should be included in the top level of u-boot.dtsi.
Signed-off-by: NDalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Resend mailbox command for 3 times with 2ms interval in between if
it receives MBOX_RESP_TIMEOUT and MBOX_RESP_DEVICE_BUSY response code.

Add a wrapper function mbox_send_cmd_common_retry() for retry, change
all the callers to use this wrapper function.
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com>

Sync latest mailbox response codes from SDM firmware.
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com>

Mailbox command which is too large to fit into the mailbox
FIFO command buffer can be sent to SDM in multiple parts.
Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: NLey Foon Tan <ley.foon.tan@intel.com>

Mailbox driver should always check for the length of the response
and read the response data before returning the response status to
caller.
Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: NLey Foon Tan <ley.foon.tan@intel.com>

Add miliseconds delay when waiting for mailbox event to happen
before timeout. This will ensure the timeout duration is predictive.
Signed-off-by: NChee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: NLey Foon Tan <ley.foon.tan@intel.com>

Document down the usage of boot_scratch_cold register to avoid
overlapping of usage in the code for S10 & Agilex.
The boot_scratch_cold register is generally used for passing
critical system info between SPL, U-Boot and Linux.
Signed-off-by: NChin Liang See <chin.liang.see@intel.com>
Signed-off-by: NSiew Chin Lim <elly.siew.chin.lim@intel.com>
Reviewed-by: NLey Foon Tan <ley.foon.tan@intel.com>