Pull the PL310 clearing code into common code, so it can be reused
by Arria10.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>

commit 1b898ffc ("gpio: dwapb_gpio: convert to livetree") introduced
a bug in that dev->node of the gpio chip was accidentally set to the
of_node of its bank subnode.

What it meant to do was assign subdev->node, not dev->node.

While this doesn't affect too many use cases, iterating over the gpio
chip's properties doesn't work any more after that, so fix this.

Fixes: commit 1b898ffc ("gpio: dwapb_gpio: convert to livetree")
Signed-off-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Various DM fixes
Addition of ofnode_get_addr_size_index()

Changes from rc2 tag
  - Support PCIe Gen4 driver of the Mobiveil IP
  - NXP LS1028A SoC and platform support
  - Few SPI related config updates
  - Distinguish the ecc val by chassis version and move the ecc addr to dts
  - sp805 watchdog support

commit 58c3e620 ("armv8: lx2160ardb : Add support for LX2160ARDB
platform") brought a new boards support with redundancy in the config.h.

One of them is CONFIG_CMDLINE_EDITING which is removed by this change.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Peng Ma <peng.ma@nxp.com>
Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Signed-off-by: NZhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Signed-off-by: NZhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

sp805 is watchdog on some NXP layerscape SoCs, adding
it's driver. Configs CONFIG_WDT_SP805, CONFIG_WDT, CONFIG_CMD_WDT
needs to be enabled to use it.
Signed-off-by: NZhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Signed-off-by: NRajat Srivastava <rajat.srivastava@nxp.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Signed-off-by: NRajat Srivastava <rajat.srivastava@nxp.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: NRajat Srivastava <rajat.srivastava@nxp.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on
CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE
is enabled
Signed-off-by: NUdit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

esbc_validate command will not be executed if “load” command for its
header fails and will further execute the source command for bootscript,
without its validation and boot process continues.

To halt the  boot process in case secure boot header is not loaded
successfully, esbc_validate command is invoked separately after “load”
command. The secure boot validation of the bootscript header will fail
(if header is not loaded) and halts the boot process, which prevent source
command from execution.
Signed-off-by: NVinitha V Pillai <vinitha.pillai@nxp.com>
Signed-off-by: NUdit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

AQR107 PHYs interrupt pins are active-low, while the GIC expects a
level-high signal.
Signed-off-by: NFlorin Chiculita <florinlaurentiu.chiculita@nxp.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Distinguish the ecc val by chassis version and move the ecc addr to dts.
Add ls1028a soc support.
Signed-off-by: NPeng Ma <peng.ma@nxp.com>
Reviewed-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Move the ecc addr from driver to dts.
Signed-off-by: NPeng Ma <peng.ma@nxp.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Enables CONFIG_SPI_FLASH
Signed-off-by: NChuanhua Han <chuanhua.han@nxp.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

LS1028AQDS Development System is a high-performance
computing, evaluation, and development platform that supports
LS1028A QorIQ Architecture processor.
Signed-off-by: NSudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: NRai Harninder <harninder.rai@nxp.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: NBhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: NTang yuantian <andy.tang@nxp.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

LS1028A is an ARMv8 implementation. LS1028ARDB is an evaluation
platform that supports the LS1028A family SoCs. This patch add basic
support of the platform.
Signed-off-by: NSudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: NRai Harninder <harninder.rai@nxp.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: NBhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: NTang Yuantian <andy.tang@nxp.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Ls1028a SoC is based on Layerscape Chassis Generation 3.2
architecture with features:
 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN
 ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers,
 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc.
Signed-off-by: NSudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: NRai Harninder <harninder.rai@nxp.com>
Signed-off-by: NRajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: NBhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: NTang Yuantian <andy.tang@nxp.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Enable the PCIe Gen4 controller driver and e1000 for LX2160ARDB
and LX2160AQDS boards.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

The LX2160A integrated 6 PCIe Gen4 controllers.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Add the infrastructure for Layerscape SoCs PCIe Gen4 controller
to update device tree nodes to convey SMMU stream IDs in the
device tree.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

The LX2160A PCIe is using driver PCIE_LAYERSCAPE_GEN4 instead
of PCIE_LAYERSCAPE.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe
controller is based on the Mobiveil IP, which is compatible
with the PCI Express™ Base Specification, Revision 4.0.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: NBao Xiaowei <Xiaowei.Bao@nxp.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

The lx2160a have up to 6 PCIe controllers and have different
address and size of PCIe region.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

The LS2080A has 8GB region for each PCIe controller, while the
other platforms have 32GB.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Change to use PCIe address macro to determine if precompile the PCIe
MMU table entry.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Update mtd-id for QSPI nor due to change introduced in mtd/spi in
linux 5.0. commit 84d043185dbe
  ("spi: Add a driver for the Freescale/NXP QuadSPI controller")

This modification is only for linux kernel version >= 5.0. To use
bootargs for kernel < 5.0, use the following bootargs
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0
earlycon=uart8250,mmio,0x21c0500
mtdparts=1550000.quadspi:2m(uboot),14m(free)"

CONFIG_MTDPARTS_DEFAULT="mtdparts=1550000.quadspi:2m(uboot),14m(free)"
Signed-off-by: NKuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

This function  takes an argument, blob,
but never uses it, instead uses gd->fdt_blob directly.

Fixes: e81c9864 ("dm: core: add clocks node scan")
Reported-by: NAKASHI Takahiro <takahiro.akashi@linaro.org>
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

It was returning an int, which doesn't work if the u32 it is reading,
or the default value, will overflow a signed int.

While it could be made to work, when using a C standard/compiler where
casting negative signed values to unsigned has a defined behavior,
combined with careful casting, it seems obvious one is meant to use
ofnode_read_s32_default() with signed values.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: NTrent Piepho <tpiepho@impinj.com>

The 'done' files created by buildman may end up being empty if buildman
runs out of disk space while writing them. At present buildman dies with
an exception when using -s to check the build status. Fix this.

Seriesl-cc: trini
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add ofnode_get_addr_size_index function to fetch the address
and size of the reg space based on index.
Signed-off-by: NKeerthy <j-keerthy@ti.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

When using fdt_fixup_mtdparts() offset and length cell sizes
are limited to 4 bytes (1 cell). However if the mtd device is
bigger then 4GiB, then #address-cells and #size-cells are
8 bytes (2 cells) [1].

This patch read #size-cells and uses either fdt32_t or
fdt64_t cell size. The default is fdt32_t.

[1] Documentation/devicetree/bindings/mtd/partition.txt
Signed-off-by: NStefan Mavrodiev <stefan@olimex.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

U-Boot already defines the {upper,lower}_32_bits() macros that have the
same purpose. Use the existing macros instead of defining new APIs.
Signed-off-by: NThierry Reding <treding@nvidia.com>

Some libraries build by U-Boot may include stdint.h. This is not used by
U-Boot itself and causes conflicts with the types defined in
linux/types.h. To work around this, add an empty file with this name so
that it will be used in preference to the compiler version.
Signed-off-by: NSimon Glass <sjg@chromium.org>

In some cases it is necessary to read the keyboard in early phases of
U-Boot. The cros_ec keyboard is kept in the misc directory. Update the
config to allow this.
Signed-off-by: NSimon Glass <sjg@chromium.org>

- Update MPC83xx platform support to current best practices, etc.

"Please pull mmc-5-20 for v2019.07, this is to avoid break i.MX53 boot."

- update for using splashfile instead of location->name
  when loading the splash image from a FIT
- updates for loading internal and external splash data from FIT
- DM_GPIO/DM_VIDEO migration for mx53 cx9020 board
- fix boot issue on mx6sabresd board after DM_VIDEO migration
- increase the max preallocated framebuffer BPP to 32 in ipuv3
  driver to prepare for configurations with higher color depth
- allow to use vidconsole_put_string() in board code for text
  output on LCD displays