Merge git://git.denx.de/u-boot-mpc83xx

- Update MPC83xx platform support to current best practices, etc.

Kconfig

@@ -512,7 +512,7 @@ config SYS_TEXT_BASE
 
 
 config SYS_CLK_FREQ
-	depends on ARC || ARCH_SUNXI
+	depends on ARC || ARCH_SUNXI || MPC83xx
 	int "CPU clock frequency"
 	help
 	  TODO: Move CONFIG_SYS_CLK_FREQ for all the architecture

arch/powerpc/Kconfig

@@ -39,6 +39,12 @@ config MPC8xx
 
 endchoice
 
+config HIGH_BATS
+	bool "Enable high BAT registers"
+	help
+	  Enable BATs (block address translation registers) 4-7 on machines
+	  that support them.
+
 source "arch/powerpc/cpu/mpc83xx/Kconfig"
 source "arch/powerpc/cpu/mpc85xx/Kconfig"
 source "arch/powerpc/cpu/mpc86xx/Kconfig"

arch/powerpc/cpu/mpc83xx/Kconfig

@@ -10,38 +10,66 @@ choice
 
 config TARGET_MPC8308_P1M
 	bool "Support mpc8308_p1m"
+	select ARCH_MPC8308
 
 config TARGET_SBC8349
 	bool "Support sbc8349"
+	select ARCH_MPC8349
 
 config TARGET_VE8313
 	bool "Support ve8313"
+	select ARCH_MPC8313
 
 config TARGET_VME8349
 	bool "Support vme8349"
+	select ARCH_MPC8349
+
+config TARGET_CADDY2
+	bool "Support caddy2"
+	select ARCH_MPC8349
 
 config TARGET_MPC8308RDB
 	bool "Support MPC8308RDB"
+	select ARCH_MPC8308
 	select SYS_FSL_ERRATUM_ESDHC111
 
-config TARGET_MPC8313ERDB
-	bool "Support MPC8313ERDB"
+config TARGET_MPC8313ERDB_NOR
+	bool "Support MPC8313ERDB_NOR"
+	select ARCH_MPC8313
+	select BOARD_EARLY_INIT_F
+	select SUPPORT_SPL
+
+config TARGET_MPC8313ERDB_NAND
+	bool "Support MPC8313ERDB_NAND"
+	select ARCH_MPC8313
 	select BOARD_EARLY_INIT_F
 	select SUPPORT_SPL
 
 config TARGET_MPC8315ERDB
 	bool "Support MPC8315ERDB"
+	select ARCH_MPC8315
 	select BOARD_EARLY_INIT_F
 
 config TARGET_MPC8323ERDB
 	bool "Support MPC8323ERDB"
+	select ARCH_MPC832X
 
 config TARGET_MPC832XEMDS
 	bool "Support MPC832XEMDS"
+	select ARCH_MPC832X
 	select BOARD_EARLY_INIT_F
 
 config TARGET_MPC8349EMDS
 	bool "Support MPC8349EMDS"
+	select ARCH_MPC8349
+	select BOARD_EARLY_INIT_F
+	select SYS_FSL_DDR
+	select SYS_FSL_DDR_BE
+	select SYS_FSL_HAS_DDR2
+
+config TARGET_MPC8349EMDS_SDRAM
+	bool "Support MPC8349EMDS_SDRAM"
+	select ARCH_MPC8349
 	select BOARD_EARLY_INIT_F
 	select SYS_FSL_DDR
 	select SYS_FSL_DDR_BE
@@ -49,53 +77,272 @@ config TARGET_MPC8349EMDS
 
 config TARGET_MPC8349ITX
 	bool "Support MPC8349ITX"
+	select ARCH_MPC8349
 	imply CMD_IRQ
 
 config TARGET_MPC837XEMDS
 	bool "Support MPC837XEMDS"
+	select ARCH_MPC837X
 	select BOARD_EARLY_INIT_F
 	imply CMD_SATA
 	imply FSL_SATA
 
 config TARGET_MPC837XERDB
 	bool "Support MPC837XERDB"
+	select ARCH_MPC837X
 	select BOARD_EARLY_INIT_F
 
 config TARGET_IDS8313
 	bool "Support ids8313"
+	select ARCH_MPC8313
 	select DM
 	imply CMD_DM
 
-config TARGET_KM8360
-	bool "Support km8360"
+config TARGET_KMETER1
+	bool "Support kmeter1"
+	select ARCH_MPC8360
+	imply CMD_CRAMFS
+	imply CMD_DIAG
+	imply FS_CRAMFS
+
+config TARGET_KMCOGE5NE
+	bool "Support kmcoge5ne"
+	select ARCH_MPC8360
 	imply CMD_CRAMFS
 	imply CMD_DIAG
 	imply FS_CRAMFS
 
 config TARGET_SUVD3
 	bool "Support suvd3"
+	select ARCH_MPC832X
+	imply CMD_CRAMFS
+	imply FS_CRAMFS
+
+config TARGET_KMVECT1
+	bool "Support kmvect1"
+	select ARCH_MPC8309
+	imply CMD_CRAMFS
+	imply FS_CRAMFS
+
+config TARGET_KMTEGR1
+	bool "Support kmtegr1"
+	select ARCH_MPC8309
 	imply CMD_CRAMFS
 	imply FS_CRAMFS
 
 config TARGET_TUXX1
 	bool "Support tuxx1"
+	select ARCH_MPC832X
+	imply CMD_CRAMFS
+	imply FS_CRAMFS
+
+config TARGET_KMSUPX5
+	bool "Support kmsupx5"
+	select ARCH_MPC832X
+	imply CMD_CRAMFS
+	imply FS_CRAMFS
+
+config TARGET_TUGE1
+	bool "Support tuge1"
+	select ARCH_MPC832X
+	imply CMD_CRAMFS
+	imply FS_CRAMFS
+
+config TARGET_KMOPTI2
+	bool "Support kmopti2"
+	select ARCH_MPC832X
+	imply CMD_CRAMFS
+	imply FS_CRAMFS
+
+config TARGET_KMTEPR2
+	bool "Support kmtepr2"
+	select ARCH_MPC832X
 	imply CMD_CRAMFS
 	imply FS_CRAMFS
 
 config TARGET_TQM834X
 	bool "Support TQM834x"
+	select ARCH_MPC8349
 
 config TARGET_HRCON
 	bool "Support hrcon"
+	select ARCH_MPC8308
 	select SYS_FSL_ERRATUM_ESDHC111
 
 config TARGET_STRIDER
 	bool "Support strider"
+	select ARCH_MPC8308
 	select SYS_FSL_ERRATUM_ESDHC111
 	imply CMD_PCA953X
 
+config TARGET_GAZERBEAM
+	bool "Support gazerbeam"
+	select ARCH_MPC8308
+	select SYS_FSL_ERRATUM_ESDHC111
+	imply ENV_IS_IN_FLASH
+	help
+	  The "Gazerbeam" is a modular system by Guntermann & Drunck GmbH
+	  Systementwicklung based on the NXP MPC8308 SoC for usage in KVM
+	  appliances.
+
+	  Features include:
+	  * Two gigabit ethernet ports
+	  * Multiple USB ports (depending on variant)
+	  * Several gigabit ethernet or optical fiber ports (depending on
+	    variant)
+	  * Several display port inputs and outputs, and supporting redrivers
+	    (depending on variant)
+	  * Several FPGAs with custom logic (depending on variant)
+
+endchoice
+
+config MPC83XX_QUICC_ENGINE
+	bool
+
+# TODO: Imply MPC83xx PCI driver
+config MPC83XX_PCI_SUPPORT
+	bool
+
+# TODO: Imply TSEC driver
+config MPC83XX_TSEC1_SUPPORT
+	bool
+
+config MPC83XX_TSEC2_SUPPORT
+	bool
+
+config MPC83XX_PCIE1_SUPPORT
+	bool
+
+config MPC83XX_PCIE2_SUPPORT
+	bool
+
+config MPC83XX_SDHC_SUPPORT
+	bool
+
+config MPC83XX_SATA_SUPPORT
+	bool
+
+config MPC83XX_SECOND_I2C_SUPPORT
+	bool
+
+config MPC83XX_LDP_PIN
+	bool
+
+config ARCH_MPC830X
+	bool
+	select MPC83XX_SDHC_SUPPORT
+
+config ARCH_MPC8308
+	bool
+	select ARCH_MPC830X
+	select MPC83XX_TSEC1_SUPPORT
+	select MPC83XX_TSEC2_SUPPORT
+	select MPC83XX_PCIE1_SUPPORT
+	select MPC83XX_SECOND_I2C_SUPPORT
+
+config ARCH_MPC8309
+	bool
+	select ARCH_MPC830X
+	select MPC83XX_QUICC_ENGINE
+	select MPC83XX_PCI_SUPPORT
+	select MPC83XX_SECOND_I2C_SUPPORT
+
+config ARCH_MPC831X
+	bool
+	select MPC83XX_PCI_SUPPORT
+	select MPC83XX_TSEC1_SUPPORT
+	select MPC83XX_TSEC2_SUPPORT
+
+config ARCH_MPC8313
+	bool
+	select ARCH_MPC831X
+	select MPC83XX_SECOND_I2C_SUPPORT
+
+config ARCH_MPC8315
+	bool
+	select ARCH_MPC831X
+	select MPC83XX_PCIE1_SUPPORT
+	select MPC83XX_PCIE2_SUPPORT
+	select MPC83XX_SATA_SUPPORT
+
+config ARCH_MPC832X
+	bool
+	select MPC83XX_QUICC_ENGINE
+	select MPC83XX_PCI_SUPPORT
+
+config ARCH_MPC834X
+	bool
+
+config ARCH_MPC8349
+	bool
+	select ARCH_MPC834X
+	select MPC83XX_PCI_SUPPORT
+	select MPC83XX_TSEC1_SUPPORT
+	select MPC83XX_TSEC2_SUPPORT
+	select MPC83XX_LDP_PIN
+	select MPC83XX_SECOND_I2C_SUPPORT
+
+config ARCH_MPC8360
+	bool
+	select MPC83XX_QUICC_ENGINE
+	select MPC83XX_PCI_SUPPORT
+	select MPC83XX_LDP_PIN
+	select MPC83XX_SECOND_I2C_SUPPORT
+
+config ARCH_MPC837X
+	bool
+	select MPC83XX_PCI_SUPPORT
+	select MPC83XX_TSEC1_SUPPORT
+	select MPC83XX_TSEC2_SUPPORT
+	select MPC83XX_PCIE1_SUPPORT
+	select MPC83XX_PCIE2_SUPPORT
+	select MPC83XX_SDHC_SUPPORT
+	select MPC83XX_SATA_SUPPORT
+	select MPC83XX_LDP_PIN
+	select MPC83XX_SECOND_I2C_SUPPORT
+
+config SYS_IMMR
+	hex "Value for IMMR"
+	default 0xE0000000
+	help
+	  Address for the Internal Memory-Mapped Registers (IMMR) window used
+	  to configure the features of the SoC.
+
+source "arch/powerpc/cpu/mpc83xx/hrcw/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/bats/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/lblaw/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/hid/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/arbiter/Kconfig"
+source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig"
+
+menu "Legacy options"
+
+if ARCH_MPC8349
+
+#TODO(mario.six@gdsys.cc): Remove when mpc83xx PCI has been converted to DM/DT
+choice
+	prompt "PMC slot configuration"
+
+config PCI_ALL_PCI1
+	bool "All PMC slots on PCI1"
+
+config PCI_ONE_PCI1
+	bool "First PMC1 on PCI1"
+
+config PCI_TWO_PCI1
+	bool "First two PMC1 on PCI1"
+
 endchoice
 
+config PCI_64BIT
+	bool "PMC2 is 64bit"
+
+endif
+
+endmenu
+
 source "board/esd/vme8349/Kconfig"
 source "board/freescale/mpc8308rdb/Kconfig"
 source "board/freescale/mpc8313erdb/Kconfig"

arch/powerpc/cpu/mpc83xx/Makefile

@@ -29,7 +29,9 @@ obj-y += interrupts.o
 obj-y += ecc.o
 obj-$(CONFIG_QE) += qe_io.o
 obj-$(CONFIG_FSL_SERDES) += serdes.o
+ifndef CONFIG_ARCH_MPC8308
 obj-$(CONFIG_PCI) += pci.o
+endif
 obj-$(CONFIG_PCIE) += pcie.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
 

arch/powerpc/cpu/mpc83xx/arbiter/Kconfig

+menu "Arbiter"
+
+choice
+	prompt "Pipeline depth"
+
+config ACR_PIPE_DEP_UNSET
+	bool "Don't set value"
+
+config ACR_PIPE_DEP_1
+	bool "1"
+
+config ACR_PIPE_DEP_2
+	bool "2"
+
+config ACR_PIPE_DEP_3
+	bool "3"
+
+config ACR_PIPE_DEP_4
+	bool "4"
+
+endchoice
+
+choice
+	prompt "Repeat count"
+
+config ACR_RPTCNT_UNSET
+	bool "Don't set value"
+
+config ACR_RPTCNT_1
+	bool "1"
+
+config ACR_RPTCNT_2
+	bool "2"
+
+config ACR_RPTCNT_3
+	bool "3"
+
+config ACR_RPTCNT_4
+	bool "4"
+
+config ACR_RPTCNT_5
+	bool "5"
+
+config ACR_RPTCNT_6
+	bool "6"
+
+config ACR_RPTCNT_7
+	bool "7"
+
+config ACR_RPTCNT_8
+	bool "8"
+
+endchoice
+
+choice
+	prompt "Address parking"
+
+config ACR_APARK_UNSET
+	bool "Don't set value"
+
+config ACR_APARK_MASTER
+	bool "Park to master"
+
+config ACR_APARK_LAST
+	bool "Park to last owner"
+
+config ACR_APARK_DISABLE
+	bool "Disabled"
+
+endchoice
+
+choice
+	prompt "Parking master"
+
+config ACR_PARKM_UNSET
+	bool "Don't set value"
+
+config ACR_PARKM_E300
+	bool "e300 core"
+
+config ACR_PARKM_TSEC_1_2
+	bool "TSEC1, TSEC2"
+
+config ACR_PARKM_USB_I2C1_BOOT
+	bool "USB/I2C1_BOOT"
+
+config ACR_PARKM_DMA_ESDHC_USB
+	bool "DMA, ESDHC, USB"
+
+config ACR_PARKM_PEX
+	bool "PCI Express"
+
+if MPC83XX_QUICC_ENGINE
+
+config ACR_PARKM_ENC_CORE
+	bool "Encryption core"
+
+endif
+
+endchoice
+
+config ACR_PIPE_DEP
+	hex
+	default 0x0 if ACR_PIPE_DEP_UNSET
+	default 0x0 if ACR_PIPE_DEP_1
+	default 0x10000 if ACR_PIPE_DEP_2
+	default 0x20000 if ACR_PIPE_DEP_3
+	default 0x30000 if ACR_PIPE_DEP_4
+
+config ACR_RPTCNT
+	hex
+	default 0x0 if ACR_RPTCNT_UNSET
+	default 0x0 if ACR_RPTCNT_1
+	default 0x100 if ACR_RPTCNT_2
+	default 0x200 if ACR_RPTCNT_3
+	default 0x300 if ACR_RPTCNT_4
+	default 0x400 if ACR_RPTCNT_5
+	default 0x500 if ACR_RPTCNT_6
+	default 0x600 if ACR_RPTCNT_7
+	default 0x700 if ACR_RPTCNT_8
+
+config ACR_APARK
+	hex
+	default 0x0 if ACR_APARK_UNSET
+	default 0x0 if ACR_APARK_MASTER
+	default 0x10 if ACR_APARK_LAST
+	default 0x20 if ACR_APARK_DISABLE
+
+config ACR_PARKM
+	hex
+	default 0x0 if ACR_PARKM_UNSET
+	default 0x0 if ACR_PARKM_E300
+	default 0x2 if ACR_PARKM_TSEC_1_2
+	default 0x3 if ACR_PARKM_USB_I2C1_BOOT
+	default 0x4 if ACR_PARKM_DMA_ESDHC_USB
+	default 0x5 if ACR_PARKM_PEX
+	default 0x5 if ACR_PARKM_ENC_CORE
+
+endmenu

arch/powerpc/cpu/mpc83xx/arbiter/arbiter.h

+	const __be32 acr_mask =
+#ifndef CONFIG_ACR_PIPE_DEP_UNSET
+		ACR_PIPE_DEP |
+#endif
+#ifndef CONFIG_ACR_RPTCNT_UNSET
+		ACR_RPTCNT |
+#endif
+#ifndef CONFIG_ACR_APARK_UNSET
+		ACR_APARK |
+#endif
+#ifndef CONFIG_ACR_PARKM_UNSET
+		ACR_PARKM |
+#endif
+		0;
+	const __be32 acr_val =
+#ifndef CONFIG_ACR_PIPE_DEP_UNSET
+		CONFIG_ACR_PIPE_DEP |
+#endif
+#ifndef CONFIG_ACR_RPTCNT_UNSET
+		CONFIG_ACR_RPTCNT |
+#endif
+#ifndef CONFIG_ACR_APARK_UNSET
+		CONFIG_ACR_APARK |
+#endif
+#ifndef CONFIG_ACR_PARKM_UNSET
+		CONFIG_ACR_PARKM |
+#endif
+		0;

arch/powerpc/cpu/mpc83xx/bats/bats.h

+#ifdef CONFIG_BAT0
+#define CONFIG_SYS_IBAT0L (\
+		(CONFIG_BAT0_BASE) |\
+		(CONFIG_BAT0_PAGE_PROTECTION) |\
+		(CONFIG_BAT0_WIMG_ICACHE) \
+		)
+#define CONFIG_SYS_IBAT0U (\
+		(CONFIG_BAT0_BASE) |\
+		(CONFIG_BAT0_LENGTH) |\
+		(CONFIG_BAT0_VALID_BITS) \
+		)
+#define CONFIG_SYS_DBAT0L (\
+		(CONFIG_BAT0_BASE) |\
+		(CONFIG_BAT0_PAGE_PROTECTION) |\
+		(CONFIG_BAT0_WIMG_DCACHE) \
+		)
+#define CONFIG_SYS_DBAT0U (\
+		(CONFIG_BAT0_BASE) |\
+		(CONFIG_BAT0_LENGTH) |\
+		(CONFIG_BAT0_VALID_BITS) \
+		)
+#else
+#define CONFIG_SYS_IBAT0L (0)
+#define CONFIG_SYS_IBAT0U (0)
+#define CONFIG_SYS_DBAT0L (0)
+#define CONFIG_SYS_DBAT0U (0)
+#endif /* CONFIG_BAT0 */
+
+#ifdef CONFIG_BAT1
+#define CONFIG_SYS_IBAT1L (\
+		(CONFIG_BAT1_BASE) |\
+		(CONFIG_BAT1_PAGE_PROTECTION) |\
+		(CONFIG_BAT1_WIMG_ICACHE) \
+		)
+#define CONFIG_SYS_IBAT1U (\
+		(CONFIG_BAT1_BASE) |\
+		(CONFIG_BAT1_LENGTH) |\
+		(CONFIG_BAT1_VALID_BITS) \
+		)
+#define CONFIG_SYS_DBAT1L (\
+		(CONFIG_BAT1_BASE) |\
+		(CONFIG_BAT1_PAGE_PROTECTION) |\
+		(CONFIG_BAT1_WIMG_DCACHE) \
+		)
+#define CONFIG_SYS_DBAT1U (\
+		(CONFIG_BAT1_BASE) |\
+		(CONFIG_BAT1_LENGTH) |\
+		(CONFIG_BAT1_VALID_BITS) \
+		)
+#else
+#define CONFIG_SYS_IBAT1L (0)
+#define CONFIG_SYS_IBAT1U (0)
+#define CONFIG_SYS_DBAT1L (0)
+#define CONFIG_SYS_DBAT1U (0)
+#endif /* CONFIG_BAT1 */
+
+#ifdef CONFIG_BAT2
+#define CONFIG_SYS_IBAT2L (\
+		(CONFIG_BAT2_BASE) |\
+		(CONFIG_BAT2_PAGE_PROTECTION) |\
+		(CONFIG_BAT2_WIMG_ICACHE) \
+		)
+#define CONFIG_SYS_IBAT2U (\
+		(CONFIG_BAT2_BASE) |\
+		(CONFIG_BAT2_LENGTH) |\
+		(CONFIG_BAT2_VALID_BITS) \
+		)
+#define CONFIG_SYS_DBAT2L (\
+		(CONFIG_BAT2_BASE) |\
+		(CONFIG_BAT2_PAGE_PROTECTION) |\
+		(CONFIG_BAT2_WIMG_DCACHE) \
+		)
+#define CONFIG_SYS_DBAT2U (\
+		(CONFIG_BAT2_BASE) |\
+		(CONFIG_BAT2_LENGTH) |\
+		(CONFIG_BAT2_VALID_BITS) \
+		)
+#else
+#define CONFIG_SYS_IBAT2L (0)
+#define CONFIG_SYS_IBAT2U (0)
+#define CONFIG_SYS_DBAT2L (0)
+#define CONFIG_SYS_DBAT2U (0)
+#endif /* CONFIG_BAT2 */
+
+#ifdef CONFIG_BAT3
+#define CONFIG_SYS_IBAT3L (\
+		(CONFIG_BAT3_BASE) |\
+		(CONFIG_BAT3_PAGE_PROTECTION) |\
+		(CONFIG_BAT3_WIMG_ICACHE) \
+		)
+#define CONFIG_SYS_IBAT3U (\
+		(CONFIG_BAT3_BASE) |\
+		(CONFIG_BAT3_LENGTH) |\
+		(CONFIG_BAT3_VALID_BITS) \
+		)
+#define CONFIG_SYS_DBAT3L (\
+		(CONFIG_BAT3_BASE) |\
+		(CONFIG_BAT3_PAGE_PROTECTION) |\
+		(CONFIG_BAT3_WIMG_DCACHE) \
+		)
+#define CONFIG_SYS_DBAT3U (\
+		(CONFIG_BAT3_BASE) |\
+		(CONFIG_BAT3_LENGTH) |\
+		(CONFIG_BAT3_VALID_BITS) \
+		)
+#else
+#define CONFIG_SYS_IBAT3L (0)
+#define CONFIG_SYS_IBAT3U (0)
+#define CONFIG_SYS_DBAT3L (0)
+#define CONFIG_SYS_DBAT3U (0)
+#endif /* CONFIG_BAT3 */
+
+#ifdef CONFIG_BAT4
+#define CONFIG_SYS_IBAT4L (\
+		(CONFIG_BAT4_BASE) |\
+		(CONFIG_BAT4_PAGE_PROTECTION) |\
+		(CONFIG_BAT4_WIMG_ICACHE) \
+		)
+#define CONFIG_SYS_IBAT4U (\
+		(CONFIG_BAT4_BASE) |\
+		(CONFIG_BAT4_LENGTH) |\
+		(CONFIG_BAT4_VALID_BITS) \
+		)
+#define CONFIG_SYS_DBAT4L (\
+		(CONFIG_BAT4_BASE) |\
+		(CONFIG_BAT4_PAGE_PROTECTION) |\
+		(CONFIG_BAT4_WIMG_DCACHE) \
+		)
+#define CONFIG_SYS_DBAT4U (\
+		(CONFIG_BAT4_BASE) |\
+		(CONFIG_BAT4_LENGTH) |\
+		(CONFIG_BAT4_VALID_BITS) \
+		)
+#else
+#define CONFIG_SYS_IBAT4L (0)
+#define CONFIG_SYS_IBAT4U (0)
+#define CONFIG_SYS_DBAT4L (0)
+#define CONFIG_SYS_DBAT4U (0)
+#endif /* CONFIG_BAT4 */
+
+#ifdef CONFIG_BAT5
+#define CONFIG_SYS_IBAT5L (\
+		(CONFIG_BAT5_BASE) |\
+		(CONFIG_BAT5_PAGE_PROTECTION) |\
+		(CONFIG_BAT5_WIMG_ICACHE) \
+		)
+#define CONFIG_SYS_IBAT5U (\
+		(CONFIG_BAT5_BASE) |\
+		(CONFIG_BAT5_LENGTH) |\
+		(CONFIG_BAT5_VALID_BITS) \
+		)
+#define CONFIG_SYS_DBAT5L (\
+		(CONFIG_BAT5_BASE) |\
+		(CONFIG_BAT5_PAGE_PROTECTION) |\
+		(CONFIG_BAT5_WIMG_DCACHE) \
+		)
+#define CONFIG_SYS_DBAT5U (\
+		(CONFIG_BAT5_BASE) |\
+		(CONFIG_BAT5_LENGTH) |\
+		(CONFIG_BAT5_VALID_BITS) \
+		)
+#else
+#define CONFIG_SYS_IBAT5L (0)
+#define CONFIG_SYS_IBAT5U (0)
+#define CONFIG_SYS_DBAT5L (0)
+#define CONFIG_SYS_DBAT5U (0)
+#endif /* CONFIG_BAT5 */
+
+#ifdef CONFIG_BAT6
+#define CONFIG_SYS_IBAT6L (\
+		(CONFIG_BAT6_BASE) |\
+		(CONFIG_BAT6_PAGE_PROTECTION) |\
+		(CONFIG_BAT6_WIMG_ICACHE) \
+		)
+#define CONFIG_SYS_IBAT6U (\
+		(CONFIG_BAT6_BASE) |\
+		(CONFIG_BAT6_LENGTH) |\
+		(CONFIG_BAT6_VALID_BITS) \
+		)
+#define CONFIG_SYS_DBAT6L (\
+		(CONFIG_BAT6_BASE) |\
+		(CONFIG_BAT6_PAGE_PROTECTION) |\
+		(CONFIG_BAT6_WIMG_DCACHE) \
+		)
+#define CONFIG_SYS_DBAT6U (\
+		(CONFIG_BAT6_BASE) |\
+		(CONFIG_BAT6_LENGTH) |\
+		(CONFIG_BAT6_VALID_BITS) \
+		)
+#else
+#define CONFIG_SYS_IBAT6L (0)
+#define CONFIG_SYS_IBAT6U (0)
+#define CONFIG_SYS_DBAT6L (0)
+#define CONFIG_SYS_DBAT6U (0)
+#endif /* CONFIG_BAT6 */
+
+#ifdef CONFIG_BAT7
+#define CONFIG_SYS_IBAT7L (\
+		(CONFIG_BAT7_BASE) |\
+		(CONFIG_BAT7_PAGE_PROTECTION) |\
+		(CONFIG_BAT7_WIMG_ICACHE) \
+		)
+#define CONFIG_SYS_IBAT7U (\
+		(CONFIG_BAT7_BASE) |\
+		(CONFIG_BAT7_LENGTH) |\
+		(CONFIG_BAT7_VALID_BITS) \
+		)
+#define CONFIG_SYS_DBAT7L (\
+		(CONFIG_BAT7_BASE) |\
+		(CONFIG_BAT7_PAGE_PROTECTION) |\
+		(CONFIG_BAT7_WIMG_DCACHE) \
+		)
+#define CONFIG_SYS_DBAT7U (\
+		(CONFIG_BAT7_BASE) |\
+		(CONFIG_BAT7_LENGTH) |\
+		(CONFIG_BAT7_VALID_BITS) \
+		)
+#else
+#define CONFIG_SYS_IBAT7L (0)
+#define CONFIG_SYS_IBAT7U (0)
+#define CONFIG_SYS_DBAT7L (0)
+#define CONFIG_SYS_DBAT7U (0)
+#endif /* CONFIG_BAT7 */

arch/powerpc/cpu/mpc83xx/cpu.c

@@ -18,7 +18,7 @@
 #include <tsec.h>
 #include <netdev.h>
 #include <fsl_esdhc.h>
-#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x)
+#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_ARCH_MPC831X)
 #include <linux/immap_qe.h>
 #include <asm/io.h>
 #endif
@@ -133,18 +133,18 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 #ifdef MPC83xx_RESET
 
 	/* Interrupts and MMU off */
-	__asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
-
-	msr &= ~( MSR_EE | MSR_IR | MSR_DR);
-	__asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
+	msr = mfmsr();
+	msr &= ~(MSR_EE | MSR_IR | MSR_DR);
+	mtmsr(msr);
 
 	/* enable Reset Control Reg */
 	immap->reset.rpr = 0x52535445;
-	__asm__ __volatile__ ("sync");
-	__asm__ __volatile__ ("isync");
+	sync();
+	isync();
 
 	/* confirm Reset Control Reg is enabled */
-	while(!((immap->reset.rcer) & RCER_CRE));
+	while(!((immap->reset.rcer) & RCER_CRE))
+		;
 
 	udelay(200);
 
@@ -156,10 +156,9 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 	immap->reset.rmr = RMR_CSRE;    /* Checkstop Reset enable */
 
 	/* Interrupts and MMU off */
-	__asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
-
+	msr = mfmsr();
 	msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
-	__asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
+	mtmsr(msr);
 
 	/*
 	 * Trying to execute the next instruction at a non-existing address
@@ -199,6 +198,7 @@ void watchdog_reset (void)
 }
 #endif
 
+#ifndef CONFIG_DM_ETH
 /*
  * Initializes on-chip ethernet controllers.
  * to override, implement board_eth_init()
@@ -214,6 +214,7 @@ int cpu_eth_init(bd_t *bis)
 #endif
 	return 0;
 }
+#endif /* !CONFIG_DM_ETH */
 
 /*
  * Initializes on-chip MMC controllers.
@@ -227,3 +228,21 @@ int cpu_mmc_init(bd_t *bis)
 	return 0;
 #endif
 }
+
+void ppcDWstore(unsigned int *addr, unsigned int *value)
+{
+	asm("lfd 1, 0(%1)\n\t"
+	    "stfd 1, 0(%0)"
+	    :
+	    : "r" (addr), "r" (value)
+	    : "memory");
+}
+
+void ppcDWload(unsigned int *addr, unsigned int *ret)
+{
+	asm("lfd 1, 0(%0)\n\t"
+	    "stfd 1, 0(%1)"
+	    :
+	    : "r" (addr), "r" (ret)
+	    : "memory");
+}

arch/powerpc/cpu/mpc83xx/cpu_init.c

@@ -12,6 +12,12 @@
 #include <usb/ehci-ci.h>
 #endif
 
+#include "lblaw/lblaw.h"
+#include "elbc/elbc.h"
+#include "sysio/sysio.h"
+#include "arbiter/arbiter.h"
+#include "initreg/initreg.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_QE
@@ -47,62 +53,6 @@ static void config_qe_ioports(void)
  */
 void cpu_init_f (volatile immap_t * im)
 {
-	__be32 acr_mask =
-#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
-		ACR_PIPE_DEP |
-#endif
-#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
-		ACR_RPTCNT |
-#endif
-#ifdef CONFIG_SYS_ACR_APARK	/* Arbiter address parking mode */
-		ACR_APARK |
-#endif
-#ifdef CONFIG_SYS_ACR_PARKM	/* Arbiter parking master */
-		ACR_PARKM |
-#endif
-		0;
-	__be32 acr_val =
-#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
-		(CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
-		(CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_ACR_APARK	/* Arbiter address parking mode */
-		(CONFIG_SYS_ACR_APARK << ACR_APARK_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_ACR_PARKM	/* Arbiter parking master */
-		(CONFIG_SYS_ACR_PARKM << ACR_PARKM_SHIFT) |
-#endif
-		0;
-	__be32 spcr_mask =
-#ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
-		SPCR_OPT |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
-		SPCR_TSECEP |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
-		SPCR_TSEC1EP |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
-		SPCR_TSEC2EP |
-#endif
-		0;
-	__be32 spcr_val =
-#ifdef CONFIG_SYS_SPCR_OPT
-		(CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
-		(CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
-		(CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
-#endif
-#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
-		(CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
-#endif
-		0;
 	__be32 sccr_mask =
 #ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
 		SCCR_ENCCM |
@@ -177,28 +127,6 @@ void cpu_init_f (volatile immap_t * im)
 #endif
 #ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
 		(CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
-#endif
-		0;
-	__be32 lcrr_mask =
-#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
-		LCRR_DBYP |
-#endif
-#ifdef CONFIG_SYS_LCRR_EADC /* external address delay */
-		LCRR_EADC |
-#endif
-#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
-		LCRR_CLKDIV |
-#endif
-		0;
-	__be32 lcrr_val =
-#ifdef CONFIG_SYS_LCRR_DBYP /* PLL bypass */
-		CONFIG_SYS_LCRR_DBYP |
-#endif
-#ifdef CONFIG_SYS_LCRR_EADC
-		CONFIG_SYS_LCRR_EADC |
-#endif
-#ifdef CONFIG_SYS_LCRR_CLKDIV /* system clock divider */
-		CONFIG_SYS_LCRR_CLKDIV |
 #endif
 		0;
 
@@ -240,7 +168,7 @@ void cpu_init_f (volatile immap_t * im)
 
 	/* System General Purpose Register */
 #ifdef CONFIG_SYS_SICRH
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313)
+#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313)
 	/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
 	__raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
 		     &im->sysconf.sicrh);
@@ -312,7 +240,7 @@ void cpu_init_f (volatile immap_t * im)
 	im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
 	im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
 #endif
-#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_MPC831x)
+#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X)
 	uint32_t temp;
 	struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
 

arch/powerpc/cpu/mpc83xx/ecc.c

@@ -191,8 +191,8 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 			}
 
 			ddr->err_disable = val;
-			__asm__ __volatile__("sync");
-			__asm__ __volatile__("isync");
+			sync();
+			isync();
 			return 0;
 		} else if (strcmp(argv[1], "errdetectclr") == 0) {
 			val = ddr->err_detect;
@@ -249,8 +249,8 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 				printf("Incorrect command\n");
 
 			ddr->ecc_err_inject = val;
-			__asm__ __volatile__("sync");
-			__asm__ __volatile__("isync");
+			sync();
+			isync();
 			return 0;
 		} else if (strcmp(argv[1], "mirror") == 0) {
 			val = ddr->ecc_err_inject;
@@ -282,26 +282,26 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 
 				/* enable injects */
 				ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
-				__asm__ __volatile__("sync");
-				__asm__ __volatile__("isync");
+				sync();
+				isync();
 
 				/* write memory location injecting errors */
 				ppcDWstore((u32 *) i, pattern);
-				__asm__ __volatile__("sync");
+				sync();
 
 				/* disable injects */
 				ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
-				__asm__ __volatile__("sync");
-				__asm__ __volatile__("isync");
+				sync();
+				isync();
 
 				/* read data, this generates ECC error */
 				ppcDWload((u32 *) i, ret);
-				__asm__ __volatile__("sync");
+				sync();
 
 				/* re-initialize memory, double word write the location again,
 				 * generates new ECC code this time */
 				ppcDWstore((u32 *) i, writeback);
-				__asm__ __volatile__("sync");
+				sync();
 			}
 			enable_interrupts();
 			return 0;
@@ -321,29 +321,29 @@ int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 
 				/* enable injects */
 				ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
-				__asm__ __volatile__("sync");
-				__asm__ __volatile__("isync");
+				sync();
+				isync();
 
 				/* write memory location injecting errors */
 				*(u32 *) i = 0xfedcba98UL;
-				__asm__ __volatile__("sync");
+				sync();
 
 				/* sub double word write,
 				 * bus will read-modify-write,
 				 * generates ECC error */
 				*((u32 *) i + 1) = 0x76543210UL;
-				__asm__ __volatile__("sync");
+				sync();
 
 				/* disable injects */
 				ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
-				__asm__ __volatile__("sync");
-				__asm__ __volatile__("isync");
+				sync();
+				isync();
 
 				/* re-initialize memory,
 				 * double word write the location again,
 				 * generates new ECC code this time */
 				ppcDWstore((u32 *) i, writeback);
-				__asm__ __volatile__("sync");
+				sync();
 			}
 			enable_interrupts();
 			return 0;

arch/powerpc/cpu/mpc83xx/elbc/Kconfig

+menu "ELBC register setup"
+
+choice
+	prompt "OR/BR for NAND SPL"
+
+config ELBC_BR_OR_NAND_PRELIM_NONE
+	bool "None"
+
+config ELBC_BR_OR_NAND_PRELIM_0
+	bool "0"
+
+config ELBC_BR_OR_NAND_PRELIM_1
+	bool "1"
+
+config ELBC_BR_OR_NAND_PRELIM_2
+	bool "2"
+
+config ELBC_BR_OR_NAND_PRELIM_3
+	bool "3"
+
+config ELBC_BR_OR_NAND_PRELIM_4
+	bool "4"
+
+endchoice
+
+source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0"
+source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1"
+source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2"
+source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3"
+source "arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4"
+
+endmenu

arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0

+menuconfig ELBC_BR0_OR0
+	bool "ELBC BR0/OR0"
+
+if ELBC_BR0_OR0
+
+config BR0_OR0_NAME
+	string "Identifier"
+
+config BR0_OR0_BASE
+	hex "Port base"
+
+choice
+	prompt "Port size"
+
+config BR0_PORTSIZE_8BIT
+	bool "8-bit"
+
+config BR0_PORTSIZE_16BIT
+	depends on !BR0_MACHINE_FCM
+	bool "16-bit"
+
+
+config BR0_PORTSIZE_32BIT
+	depends on !BR0_MACHINE_FCM
+	depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+	bool "32-bit"
+
+endchoice
+
+if BR0_MACHINE_FCM
+
+choice
+	prompt "Data Error Checking"
+
+config BR0_ERRORCHECKING_DISABLED
+	bool "Disabled"
+
+config BR0_ERRORCHECKING_ECC_CHECKING
+	bool "ECC checking / No ECC generation"
+
+config BR0_ERRORCHECKING_BOTH
+	bool "ECC checking and generation"
+
+endchoice
+
+endif
+
+config BR0_WRITE_PROTECT
+	bool "Write-protect"
+
+config BR0_MACHINE_UPM
+	bool
+
+choice
+	prompt "Machine select"
+
+config BR0_MACHINE_GPCM
+	bool "GPCM"
+
+config BR0_MACHINE_FCM
+	depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+	bool "FCM"
+
+config BR0_MACHINE_SDRAM
+	depends on ARCH_MPC8349 || ARCH_MPC8360
+	bool "SDRAM"
+
+config BR0_MACHINE_UPMA
+	select BR0_MACHINE_UPM
+	bool "UPM (A)"
+
+config BR0_MACHINE_UPMB
+	select BR0_MACHINE_UPM
+	bool "UPM (B)"
+
+config BR0_MACHINE_UPMC
+	select BR0_MACHINE_UPM
+	bool "UPM (C)"
+
+endchoice
+
+if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
+
+choice
+	prompt "Atomic operations"
+
+config BR0_ATOMIC_NONE
+	bool "No atomic operations"
+
+config BR0_ATOMIC_RAWA
+	bool "Read-after-write-atomic"
+
+config BR0_ATOMIC_WARA
+	bool "Write-after-read-atomic"
+
+endchoice
+
+endif
+
+if BR0_MACHINE_GPCM || BR0_MACHINE_FCM || BR0_MACHINE_UPM || BR0_MACHINE_SDRAM
+
+choice
+	prompt "Address mask"
+
+config OR0_AM_32_KBYTES
+	depends on !BR0_MACHINE_SDRAM
+	bool "32 kb"
+
+config OR0_AM_64_KBYTES
+	bool "64 kb"
+
+config OR0_AM_128_KBYTES
+	bool "128 kb"
+
+config OR0_AM_256_KBYTES
+	bool "256 kb"
+
+config OR0_AM_512_KBYTES
+	bool "512 kb"
+
+config OR0_AM_1_MBYTES
+	bool "1 mb"
+
+config OR0_AM_2_MBYTES
+	bool "2 mb"
+
+config OR0_AM_4_MBYTES
+	bool "4 mb"
+
+config OR0_AM_8_MBYTES
+	bool "8 mb"
+
+config OR0_AM_16_MBYTES
+	bool "16 mb"
+
+config OR0_AM_32_MBYTES
+	bool "32 mb"
+
+config OR0_AM_64_MBYTES
+	bool "64 mb"
+
+# XXX: Some boards define 128MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR0_AM_128_MBYTES
+	bool "128 mb"
+
+# XXX: Some boards define 256MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR0_AM_256_MBYTES
+	bool "256 mb"
+
+config OR0_AM_512_MBYTES
+	depends on BR0_MACHINE_FCM
+	bool "512 mb"
+
+# XXX: Some boards define 1GB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR0_AM_1_GBYTES
+	bool "1 gb"
+
+config OR0_AM_2_GBYTES
+	depends on BR0_MACHINE_FCM
+	bool "2 gb"
+
+config OR0_AM_4_GBYTES
+	depends on BR0_MACHINE_FCM
+	bool "4 gb"
+
+endchoice
+
+config OR0_XAM_SET
+	bool "Set unused bytes after address mask"
+choice
+	prompt "Buffer control disable"
+
+config OR0_BCTLD_ASSERTED
+	bool "Asserted"
+
+config OR0_BCTLD_NOT_ASSERTED
+	bool "Not asserted"
+
+endchoice
+
+endif
+
+if BR0_MACHINE_GPCM || BR0_MACHINE_FCM
+
+choice
+	prompt "Cycle length in bus clocks"
+
+config OR0_SCY_0
+	bool "No wait states"
+
+config OR0_SCY_1
+	bool "1 wait state"
+
+config OR0_SCY_2
+	bool "2 wait states"
+
+config OR0_SCY_3
+	bool "3 wait states"
+
+config OR0_SCY_4
+	bool "4 wait states"
+
+config OR0_SCY_5
+	bool "5 wait states"
+
+config OR0_SCY_6
+	bool "6 wait states"
+
+config OR0_SCY_7
+	bool "7 wait states"
+
+config OR0_SCY_8
+	depends on BR0_MACHINE_GPCM
+	bool "8 wait states"
+
+config OR0_SCY_9
+	depends on BR0_MACHINE_GPCM
+	bool "9 wait states"
+
+config OR0_SCY_10
+	depends on BR0_MACHINE_GPCM
+	bool "10 wait states"
+
+config OR0_SCY_11
+	depends on BR0_MACHINE_GPCM
+	bool "11 wait states"
+
+config OR0_SCY_12
+	depends on BR0_MACHINE_GPCM
+	bool "12 wait states"
+
+config OR0_SCY_13
+	depends on BR0_MACHINE_GPCM
+	bool "13 wait states"
+
+config OR0_SCY_14
+	depends on BR0_MACHINE_GPCM
+	bool "14 wait states"
+
+config OR0_SCY_15
+	depends on BR0_MACHINE_GPCM
+	bool "15 wait states"
+
+endchoice
+
+endif # BR0_MACHINE_GPCM || BR0_MACHINE_FCM
+
+if BR0_MACHINE_GPCM
+
+choice
+	prompt "Chip select negotiation time"
+
+config OR0_CSNT_NORMAL
+	bool "Normal"
+
+config OR0_CSNT_EARLIER
+	bool "Earlier"
+
+endchoice
+
+choice
+	prompt "Address to chip-select setup"
+
+config OR0_ACS_SAME_TIME
+	bool "At the same time"
+
+config OR0_ACS_HALF_CYCLE_EARLIER
+	bool "Half of a bus clock cycle earlier"
+
+config OR0_ACS_QUARTER_CYCLE_EARLIER
+	bool "Half/Quarter of a bus clock cycle earlier"
+
+endchoice
+
+choice
+	prompt "Extra address to check-select setup"
+
+config OR0_XACS_NORMAL
+	bool "Normal"
+
+config OR0_XACS_EXTENDED
+	bool "Extended"
+
+endchoice
+
+choice
+	prompt "External address termination"
+
+config OR0_SETA_INTERNAL
+	bool "Access is terminated internally"
+
+config OR0_SETA_EXTERNAL
+	bool "Access is terminated externally"
+
+endchoice
+
+endif # BR0_MACHINE_GPCM
+
+if BR0_MACHINE_FCM
+
+choice
+	prompt "NAND Flash EEPROM page size"
+
+config OR0_PGS_SMALL
+	bool "Small page device"
+
+config OR0_PGS_LARGE
+	bool "Large page device"
+
+endchoice
+
+choice
+	prompt "Chip select to command time"
+
+config OR0_CSCT_1_CYCLE
+	depends on OR0_TRLX_NORMAL
+	bool "1 cycle"
+
+config OR0_CSCT_2_CYCLE
+	depends on OR0_TRLX_RELAXED
+	bool "2 cycles"
+
+config OR0_CSCT_4_CYCLE
+	depends on OR0_TRLX_NORMAL
+	bool "4 cycles"
+
+config OR0_CSCT_8_CYCLE
+	depends on OR0_TRLX_RELAXED
+	bool "8 cycles"
+
+endchoice
+
+choice
+	prompt "Command setup time"
+
+config OR0_CST_COINCIDENT
+	depends on OR0_TRLX_NORMAL
+	bool "Coincident with any command"
+
+config OR0_CST_QUARTER_CLOCK
+	depends on OR0_TRLX_NORMAL
+	bool "0.25 clocks after"
+
+config OR0_CST_HALF_CLOCK
+	depends on OR0_TRLX_RELAXED
+	bool "0.5 clocks after"
+
+config OR0_CST_ONE_CLOCK
+	depends on OR0_TRLX_RELAXED
+	bool "1 clock after"
+
+endchoice
+
+choice
+	prompt "Command hold time"
+
+config OR0_CHT_HALF_CLOCK
+	depends on OR0_TRLX_NORMAL
+	bool "0.5 clocks before"
+
+config OR0_CHT_ONE_CLOCK
+	depends on OR0_TRLX_NORMAL
+	bool "1 clock before"
+
+config OR0_CHT_ONE_HALF_CLOCK
+	depends on OR0_TRLX_RELAXED
+	bool "1.5 clocks before"
+
+config OR0_CHT_TWO_CLOCK
+	depends on OR0_TRLX_RELAXED
+	bool "2 clocks before"
+
+endchoice
+
+choice
+	prompt "Reset setup time"
+
+config OR0_RST_THREE_QUARTER_CLOCK
+	depends on OR0_TRLX_NORMAL
+	bool "0.75 clocks prior"
+
+config OR0_RST_ONE_HALF_CLOCK
+	depends on OR0_TRLX_RELAXED
+	bool "0.5 clocks prior"
+
+config OR0_RST_ONE_CLOCK
+	bool "1 clock prior"
+
+endchoice
+
+endif # BR0_MACHINE_FCM
+
+if BR0_MACHINE_UPM
+
+choice
+	prompt "Burst inhibit"
+
+config OR0_BI_BURSTSUPPORT
+	bool "Support burst access"
+
+config OR0_BI_BURSTINHIBIT
+	bool "Inhibit burst access"
+
+endchoice
+
+endif # BR0_MACHINE_UPM
+
+if BR0_MACHINE_SDRAM
+
+choice
+	prompt "Number of column address lines"
+
+config OR0_COLS_7
+	bool "7"
+
+config OR0_COLS_8
+	bool "8"
+
+config OR0_COLS_9
+	bool "9"
+
+config OR0_COLS_10
+	bool "10"
+
+config OR0_COLS_11
+	bool "11"
+
+config OR0_COLS_12
+	bool "12"
+
+config OR0_COLS_13
+	bool "13"
+
+config OR0_COLS_14
+	bool "14"
+
+endchoice
+
+choice
+	prompt "Number of rows address lines"
+
+config OR0_ROWS_9
+	bool "9"
+
+config OR0_ROWS_10
+	bool "10"
+
+config OR0_ROWS_11
+	bool "11"
+
+config OR0_ROWS_12
+	bool "12"
+
+config OR0_ROWS_13
+	bool "13"
+
+config OR0_ROWS_14
+	bool "14"
+
+config OR0_ROWS_15
+	bool "15"
+
+endchoice
+
+choice
+	prompt "Page mode select"
+
+config OR0_PMSEL_BTB
+	bool "Back-to-back"
+
+config OR0_PMSEL_KEPT_OPEN
+	bool "Page kept open until page miss or refresh"
+
+endchoice
+
+endif # BR0_MACHINE_SDRAM
+
+choice
+	prompt "Relaxed timing"
+
+config OR0_TRLX_NORMAL
+	bool "Normal"
+
+config OR0_TRLX_RELAXED
+	bool "Relaxed"
+
+endchoice
+
+choice
+	prompt "Extended hold time"
+
+config OR0_EHTR_NORMAL
+	depends on OR0_TRLX_NORMAL
+	bool "Normal"
+
+config OR0_EHTR_1_CYCLE
+	depends on OR0_TRLX_NORMAL
+	bool "1 idle clock cycle inserted"
+
+config OR0_EHTR_4_CYCLE
+	depends on OR0_TRLX_RELAXED
+	bool "4 idle clock cycles inserted"
+
+config OR0_EHTR_8_CYCLE
+	depends on OR0_TRLX_RELAXED
+	bool "8 idle clock cycles inserted"
+
+endchoice
+
+if !ARCH_MPC8308
+
+choice
+	prompt "External address latch delay"
+
+config OR0_EAD_NONE
+	bool "None"
+
+config OR0_EAD_EXTRA
+	bool "Extra"
+
+endchoice
+
+endif # !ARCH_MPC8308
+
+endif # ELBC_BR0_OR0
+
+config BR0_PORTSIZE
+	hex
+	default 0x800 if BR0_PORTSIZE_8BIT
+	default 0x1000 if BR0_PORTSIZE_16BIT
+	default 0x1800 if BR0_PORTSIZE_32BIT
+
+config BR0_ERRORCHECKING
+	hex
+	default 0x0 if !BR0_MACHINE_FCM
+	default 0x0 if BR0_ERRORCHECKING_DISABLED
+	default 0x200 if BR0_ERRORCHECKING_ECC_CHECKING
+	default 0x400 if BR0_ERRORCHECKING_BOTH
+
+config BR0_WRITE_PROTECT_BIT
+	hex
+	default 0x0 if !BR0_WRITE_PROTECT
+	default 0x100 if BR0_WRITE_PROTECT
+
+config BR0_MACHINE
+	hex
+	default 0x0 if BR0_MACHINE_GPCM
+	default 0x20 if BR0_MACHINE_FCM
+	default 0x60 if BR0_MACHINE_SDRAM
+	default 0x80 if BR0_MACHINE_UPMA
+	default 0xa0 if BR0_MACHINE_UPMB
+	default 0xc0 if BR0_MACHINE_UPMC
+
+config BR0_ATOMIC
+	hex
+	default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
+	default 0x0 if BR0_ATOMIC_NONE
+	default 0x4 if BR0_ATOMIC_RAWA
+	default 0x8 if BR0_ATOMIC_WARA
+
+config BR0_VALID_BIT
+	hex
+	default 0x0 if !ELBC_BR0_OR0
+	default 0x1 if ELBC_BR0_OR0
+
+config OR0_AM
+	hex
+	default 0xffff8000 if OR0_AM_32_KBYTES && !BR0_MACHINE_SDRAM
+	default 0xffff0000 if OR0_AM_64_KBYTES
+	default 0xfffe0000 if OR0_AM_128_KBYTES
+	default 0xfffc0000 if OR0_AM_256_KBYTES
+	default 0xfff80000 if OR0_AM_512_KBYTES
+	default 0xfff00000 if OR0_AM_1_MBYTES
+	default 0xffe00000 if OR0_AM_2_MBYTES
+	default 0xffc00000 if OR0_AM_4_MBYTES
+	default 0xff800000 if OR0_AM_8_MBYTES
+	default 0xff000000 if OR0_AM_16_MBYTES
+	default 0xfe000000 if OR0_AM_32_MBYTES
+	default 0xfc000000 if OR0_AM_64_MBYTES
+	default 0xf8000000 if OR0_AM_128_MBYTES
+	default 0xf0000000 if OR0_AM_256_MBYTES
+	default 0xe0000000 if OR0_AM_512_MBYTES
+	default 0xc0000000 if OR0_AM_1_GBYTES
+	default 0x80000000 if OR0_AM_2_GBYTES
+	default 0x00000000 if OR0_AM_4_GBYTES
+
+config OR0_XAM
+	hex
+	default 0x0 if !OR0_XAM_SET
+	default 0x6000 if OR0_XAM_SET
+
+config OR0_BCTLD
+	hex
+	default 0x0 if OR0_BCTLD_ASSERTED
+	default 0x1000 if OR0_BCTLD_NOT_ASSERTED
+
+config OR0_BI
+	hex
+	default 0x0 if !BR0_MACHINE_UPM
+	default 0x0 if OR0_BI_BURSTSUPPORT
+	default 0x100 if OR0_BI_BURSTINHIBIT
+
+config OR0_COLS
+	hex
+	default 0x0 if !BR0_MACHINE_SDRAM
+	default 0x0 if OR0_COLS_7
+	default 0x400 if OR0_COLS_8
+	default 0x800 if OR0_COLS_9
+	default 0xc00 if OR0_COLS_10
+	default 0x1000 if OR0_COLS_11
+	default 0x1400 if OR0_COLS_12
+	default 0x1800 if OR0_COLS_13
+	default 0x1c00 if OR0_COLS_14
+
+config OR0_ROWS
+	hex
+	default 0x0 if !BR0_MACHINE_SDRAM
+	default 0x0 if OR0_ROWS_9
+	default 0x40 if OR0_ROWS_10
+	default 0x80 if OR0_ROWS_11
+	default 0xc0 if OR0_ROWS_12
+	default 0x100 if OR0_ROWS_13
+	default 0x140 if OR0_ROWS_14
+	default 0x180 if OR0_ROWS_15
+
+config OR0_PMSEL
+	hex
+	default 0x0 if !BR0_MACHINE_SDRAM
+	default 0x0 if OR0_PMSEL_BTB
+	default 0x20 if OR0_PMSEL_KEPT_OPEN
+
+config OR0_SCY
+	hex
+	default 0x0 if !BR0_MACHINE_GPCM && !BR0_MACHINE_FCM
+	default 0x0 if OR0_SCY_0
+	default 0x10 if OR0_SCY_1
+	default 0x20 if OR0_SCY_2
+	default 0x30 if OR0_SCY_3
+	default 0x40 if OR0_SCY_4
+	default 0x50 if OR0_SCY_5
+	default 0x60 if OR0_SCY_6
+	default 0x70 if OR0_SCY_7
+	default 0x80 if OR0_SCY_8
+	default 0x90 if OR0_SCY_9
+	default 0xa0 if OR0_SCY_10
+	default 0xb0 if OR0_SCY_11
+	default 0xc0 if OR0_SCY_12
+	default 0xd0 if OR0_SCY_13
+	default 0xe0 if OR0_SCY_14
+	default 0xf0 if OR0_SCY_15
+
+config OR0_PGS
+	hex
+	default 0x0 if !BR0_MACHINE_FCM
+	default 0x0 if OR0_PGS_SMALL
+	default 0x400 if OR0_PGS_LARGE
+
+config OR0_CSCT
+	hex
+	default 0x0 if !BR0_MACHINE_FCM
+	default 0x0 if OR0_CSCT_1_CYCLE
+	default 0x0 if OR0_CSCT_2_CYCLE
+	default 0x200 if OR0_CSCT_4_CYCLE
+	default 0x200 if OR0_CSCT_8_CYCLE
+
+config OR0_CST
+	hex
+	default 0x0 if !BR0_MACHINE_FCM
+	default 0x0 if OR0_CST_COINCIDENT
+	default 0x100 if OR0_CST_QUARTER_CLOCK
+	default 0x0 if OR0_CST_HALF_CLOCK
+	default 0x100 if OR0_CST_ONE_CLOCK
+
+config OR0_CHT
+	hex
+	default 0x0 if !BR0_MACHINE_FCM
+	default 0x0 if OR0_CHT_HALF_CLOCK
+	default 0x80 if OR0_CHT_ONE_CLOCK
+	default 0x0 if OR0_CHT_ONE_HALF_CLOCK
+	default 0x80 if OR0_CHT_TWO_CLOCK
+
+config OR0_RST
+	hex
+	default 0x0 if !BR0_MACHINE_FCM
+	default 0x0 if OR0_RST_THREE_QUARTER_CLOCK
+	default 0x8 if OR0_RST_ONE_CLOCK
+	default 0x0 if OR0_RST_ONE_HALF_CLOCK
+
+config OR0_CSNT
+	hex
+	default 0x0 if !BR0_MACHINE_GPCM
+	default 0x0 if OR0_CSNT_NORMAL
+	default 0x800 if OR0_CSNT_EARLIER
+
+config OR0_ACS
+	hex
+	default 0x0 if !BR0_MACHINE_GPCM
+	default 0x0 if OR0_ACS_SAME_TIME
+	default 0x400 if OR0_ACS_QUARTER_CYCLE_EARLIER
+	default 0x600 if OR0_ACS_HALF_CYCLE_EARLIER
+
+config OR0_XACS
+	hex
+	default 0x0 if !BR0_MACHINE_GPCM
+	default 0x0 if OR0_XACS_NORMAL
+	default 0x100 if OR0_XACS_EXTENDED
+
+config OR0_SETA
+	hex
+	default 0x0 if !BR0_MACHINE_GPCM
+	default 0x0 if OR0_SETA_INTERNAL
+	default 0x8 if OR0_SETA_EXTERNAL
+
+config OR0_TRLX
+	hex
+	default 0x0 if OR0_TRLX_NORMAL
+	default 0x4 if OR0_TRLX_RELAXED
+
+config OR0_EHTR
+	hex
+	default 0x0 if OR0_EHTR_NORMAL
+	default 0x2 if OR0_EHTR_1_CYCLE
+	default 0x0 if OR0_EHTR_4_CYCLE
+	default 0x2 if OR0_EHTR_8_CYCLE
+
+config OR0_EAD
+	hex
+	default 0x0 if ARCH_MPC8308
+	default 0x0 if OR0_EAD_NONE
+	default 0x1 if OR0_EAD_EXTRA

arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1

+menuconfig ELBC_BR1_OR1
+	bool "ELBC BR1/OR1"
+
+if ELBC_BR1_OR1
+
+config BR1_OR1_NAME
+	string "Identifier"
+
+config BR1_OR1_BASE
+	hex "Port base"
+
+choice
+	prompt "Port size"
+
+config BR1_PORTSIZE_8BIT
+	bool "8-bit"
+
+config BR1_PORTSIZE_16BIT
+	depends on !BR1_MACHINE_FCM
+	bool "16-bit"
+
+
+config BR1_PORTSIZE_32BIT
+	depends on !BR1_MACHINE_FCM
+	depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+	bool "32-bit"
+
+endchoice
+
+if BR1_MACHINE_FCM
+
+choice
+	prompt "Data Error Checking"
+
+config BR1_ERRORCHECKING_DISABLED
+	bool "Disabled"
+
+config BR1_ERRORCHECKING_ECC_CHECKING
+	bool "ECC checking / No ECC generation"
+
+config BR1_ERRORCHECKING_BOTH
+	bool "ECC checking and generation"
+
+endchoice
+
+endif
+
+config BR1_WRITE_PROTECT
+	bool "Write-protect"
+
+config BR1_MACHINE_UPM
+	bool
+
+choice
+	prompt "Machine select"
+
+config BR1_MACHINE_GPCM
+	bool "GPCM"
+
+config BR1_MACHINE_FCM
+	depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+	bool "FCM"
+
+config BR1_MACHINE_SDRAM
+	depends on ARCH_MPC8349 || ARCH_MPC8360
+	bool "SDRAM"
+
+config BR1_MACHINE_UPMA
+	select BR1_MACHINE_UPM
+	bool "UPM (A)"
+
+config BR1_MACHINE_UPMB
+	select BR1_MACHINE_UPM
+	bool "UPM (B)"
+
+config BR1_MACHINE_UPMC
+	select BR1_MACHINE_UPM
+	bool "UPM (C)"
+
+endchoice
+
+if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
+
+choice
+	prompt "Atomic operations"
+
+config BR1_ATOMIC_NONE
+	bool "No atomic operations"
+
+config BR1_ATOMIC_RAWA
+	bool "Read-after-write-atomic"
+
+config BR1_ATOMIC_WARA
+	bool "Write-after-read-atomic"
+
+endchoice
+
+endif
+
+if BR1_MACHINE_GPCM || BR1_MACHINE_FCM || BR1_MACHINE_UPM || BR1_MACHINE_SDRAM
+
+choice
+	prompt "Address mask"
+
+config OR1_AM_32_KBYTES
+	depends on !BR1_MACHINE_SDRAM
+	bool "32 kb"
+
+config OR1_AM_64_KBYTES
+	bool "64 kb"
+
+config OR1_AM_128_KBYTES
+	bool "128 kb"
+
+config OR1_AM_256_KBYTES
+	bool "256 kb"
+
+config OR1_AM_512_KBYTES
+	bool "512 kb"
+
+config OR1_AM_1_MBYTES
+	bool "1 mb"
+
+config OR1_AM_2_MBYTES
+	bool "2 mb"
+
+config OR1_AM_4_MBYTES
+	bool "4 mb"
+
+config OR1_AM_8_MBYTES
+	bool "8 mb"
+
+config OR1_AM_16_MBYTES
+	bool "16 mb"
+
+config OR1_AM_32_MBYTES
+	bool "32 mb"
+
+config OR1_AM_64_MBYTES
+	bool "64 mb"
+
+# XXX: Some boards define 128MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR1_AM_128_MBYTES
+	bool "128 mb"
+
+# XXX: Some boards define 256MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR1_AM_256_MBYTES
+	bool "256 mb"
+
+config OR1_AM_512_MBYTES
+	depends on BR1_MACHINE_FCM
+	bool "512 mb"
+
+# XXX: Some boards define 1GB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR1_AM_1_GBYTES
+	bool "1 gb"
+
+config OR1_AM_2_GBYTES
+	depends on BR1_MACHINE_FCM
+	bool "2 gb"
+
+config OR1_AM_4_GBYTES
+	depends on BR1_MACHINE_FCM
+	bool "4 gb"
+
+endchoice
+
+config OR1_XAM_SET
+	bool "Set unused bytes after address mask"
+choice
+	prompt "Buffer control disable"
+
+config OR1_BCTLD_ASSERTED
+	bool "Asserted"
+
+config OR1_BCTLD_NOT_ASSERTED
+	bool "Not asserted"
+
+endchoice
+
+endif
+
+if BR1_MACHINE_GPCM || BR1_MACHINE_FCM
+
+choice
+	prompt "Cycle length in bus clocks"
+
+config OR1_SCY_0
+	bool "No wait states"
+
+config OR1_SCY_1
+	bool "1 wait state"
+
+config OR1_SCY_2
+	bool "2 wait states"
+
+config OR1_SCY_3
+	bool "3 wait states"
+
+config OR1_SCY_4
+	bool "4 wait states"
+
+config OR1_SCY_5
+	bool "5 wait states"
+
+config OR1_SCY_6
+	bool "6 wait states"
+
+config OR1_SCY_7
+	bool "7 wait states"
+
+config OR1_SCY_8
+	depends on BR1_MACHINE_GPCM
+	bool "8 wait states"
+
+config OR1_SCY_9
+	depends on BR1_MACHINE_GPCM
+	bool "9 wait states"
+
+config OR1_SCY_10
+	depends on BR1_MACHINE_GPCM
+	bool "10 wait states"
+
+config OR1_SCY_11
+	depends on BR1_MACHINE_GPCM
+	bool "11 wait states"
+
+config OR1_SCY_12
+	depends on BR1_MACHINE_GPCM
+	bool "12 wait states"
+
+config OR1_SCY_13
+	depends on BR1_MACHINE_GPCM
+	bool "13 wait states"
+
+config OR1_SCY_14
+	depends on BR1_MACHINE_GPCM
+	bool "14 wait states"
+
+config OR1_SCY_15
+	depends on BR1_MACHINE_GPCM
+	bool "15 wait states"
+
+endchoice
+
+endif # BR1_MACHINE_GPCM || BR1_MACHINE_FCM
+
+if BR1_MACHINE_GPCM
+
+choice
+	prompt "Chip select negotiation time"
+
+config OR1_CSNT_NORMAL
+	bool "Normal"
+
+config OR1_CSNT_EARLIER
+	bool "Earlier"
+
+endchoice
+
+choice
+	prompt "Address to chip-select setup"
+
+config OR1_ACS_SAME_TIME
+	bool "At the same time"
+
+config OR1_ACS_HALF_CYCLE_EARLIER
+	bool "Half of a bus clock cycle earlier"
+
+config OR1_ACS_QUARTER_CYCLE_EARLIER
+	bool "Half/Quarter of a bus clock cycle earlier"
+
+endchoice
+
+choice
+	prompt "Extra address to check-select setup"
+
+config OR1_XACS_NORMAL
+	bool "Normal"
+
+config OR1_XACS_EXTENDED
+	bool "Extended"
+
+endchoice
+
+choice
+	prompt "External address termination"
+
+config OR1_SETA_INTERNAL
+	bool "Access is terminated internally"
+
+config OR1_SETA_EXTERNAL
+	bool "Access is terminated externally"
+
+endchoice
+
+endif # BR1_MACHINE_GPCM
+
+if BR1_MACHINE_FCM
+
+choice
+	prompt "NAND Flash EEPROM page size"
+
+config OR1_PGS_SMALL
+	bool "Small page device"
+
+config OR1_PGS_LARGE
+	bool "Large page device"
+
+endchoice
+
+choice
+	prompt "Chip select to command time"
+
+config OR1_CSCT_1_CYCLE
+	depends on OR1_TRLX_NORMAL
+	bool "1 cycle"
+
+config OR1_CSCT_2_CYCLE
+	depends on OR1_TRLX_RELAXED
+	bool "2 cycles"
+
+config OR1_CSCT_4_CYCLE
+	depends on OR1_TRLX_NORMAL
+	bool "4 cycles"
+
+config OR1_CSCT_8_CYCLE
+	depends on OR1_TRLX_RELAXED
+	bool "8 cycles"
+
+endchoice
+
+choice
+	prompt "Command setup time"
+
+config OR1_CST_COINCIDENT
+	depends on OR1_TRLX_NORMAL
+	bool "Coincident with any command"
+
+config OR1_CST_QUARTER_CLOCK
+	depends on OR1_TRLX_NORMAL
+	bool "0.25 clocks after"
+
+config OR1_CST_HALF_CLOCK
+	depends on OR1_TRLX_RELAXED
+	bool "0.5 clocks after"
+
+config OR1_CST_ONE_CLOCK
+	depends on OR1_TRLX_RELAXED
+	bool "1 clock after"
+
+endchoice
+
+choice
+	prompt "Command hold time"
+
+config OR1_CHT_HALF_CLOCK
+	depends on OR1_TRLX_NORMAL
+	bool "0.5 clocks before"
+
+config OR1_CHT_ONE_CLOCK
+	depends on OR1_TRLX_NORMAL
+	bool "1 clock before"
+
+config OR1_CHT_ONE_HALF_CLOCK
+	depends on OR1_TRLX_RELAXED
+	bool "1.5 clocks before"
+
+config OR1_CHT_TWO_CLOCK
+	depends on OR1_TRLX_RELAXED
+	bool "2 clocks before"
+
+endchoice
+
+choice
+	prompt "Reset setup time"
+
+config OR1_RST_THREE_QUARTER_CLOCK
+	depends on OR1_TRLX_NORMAL
+	bool "0.75 clocks prior"
+
+config OR1_RST_ONE_HALF_CLOCK
+	depends on OR1_TRLX_RELAXED
+	bool "0.5 clocks prior"
+
+config OR1_RST_ONE_CLOCK
+	bool "1 clock prior"
+
+endchoice
+
+endif # BR1_MACHINE_FCM
+
+if BR1_MACHINE_UPM
+
+choice
+	prompt "Burst inhibit"
+
+config OR1_BI_BURSTSUPPORT
+	bool "Support burst access"
+
+config OR1_BI_BURSTINHIBIT
+	bool "Inhibit burst access"
+
+endchoice
+
+endif # BR1_MACHINE_UPM
+
+if BR1_MACHINE_SDRAM
+
+choice
+	prompt "Number of column address lines"
+
+config OR1_COLS_7
+	bool "7"
+
+config OR1_COLS_8
+	bool "8"
+
+config OR1_COLS_9
+	bool "9"
+
+config OR1_COLS_10
+	bool "10"
+
+config OR1_COLS_11
+	bool "11"
+
+config OR1_COLS_12
+	bool "12"
+
+config OR1_COLS_13
+	bool "13"
+
+config OR1_COLS_14
+	bool "14"
+
+endchoice
+
+choice
+	prompt "Number of rows address lines"
+
+config OR1_ROWS_9
+	bool "9"
+
+config OR1_ROWS_10
+	bool "10"
+
+config OR1_ROWS_11
+	bool "11"
+
+config OR1_ROWS_12
+	bool "12"
+
+config OR1_ROWS_13
+	bool "13"
+
+config OR1_ROWS_14
+	bool "14"
+
+config OR1_ROWS_15
+	bool "15"
+
+endchoice
+
+choice
+	prompt "Page mode select"
+
+config OR1_PMSEL_BTB
+	bool "Back-to-back"
+
+config OR1_PMSEL_KEPT_OPEN
+	bool "Page kept open until page miss or refresh"
+
+endchoice
+
+endif # BR1_MACHINE_SDRAM
+
+choice
+	prompt "Relaxed timing"
+
+config OR1_TRLX_NORMAL
+	bool "Normal"
+
+config OR1_TRLX_RELAXED
+	bool "Relaxed"
+
+endchoice
+
+choice
+	prompt "Extended hold time"
+
+config OR1_EHTR_NORMAL
+	depends on OR1_TRLX_NORMAL
+	bool "Normal"
+
+config OR1_EHTR_1_CYCLE
+	depends on OR1_TRLX_NORMAL
+	bool "1 idle clock cycle inserted"
+
+config OR1_EHTR_4_CYCLE
+	depends on OR1_TRLX_RELAXED
+	bool "4 idle clock cycles inserted"
+
+config OR1_EHTR_8_CYCLE
+	depends on OR1_TRLX_RELAXED
+	bool "8 idle clock cycles inserted"
+
+endchoice
+
+if !ARCH_MPC8308
+
+choice
+	prompt "External address latch delay"
+
+config OR1_EAD_NONE
+	bool "None"
+
+config OR1_EAD_EXTRA
+	bool "Extra"
+
+endchoice
+
+endif # !ARCH_MPC8308
+
+endif # ELBC_BR1_OR1
+
+config BR1_PORTSIZE
+	hex
+	default 0x800 if BR1_PORTSIZE_8BIT
+	default 0x1000 if BR1_PORTSIZE_16BIT
+	default 0x1800 if BR1_PORTSIZE_32BIT
+
+config BR1_ERRORCHECKING
+	hex
+	default 0x0 if !BR1_MACHINE_FCM
+	default 0x0 if BR1_ERRORCHECKING_DISABLED
+	default 0x200 if BR1_ERRORCHECKING_ECC_CHECKING
+	default 0x400 if BR1_ERRORCHECKING_BOTH
+
+config BR1_WRITE_PROTECT_BIT
+	hex
+	default 0x0 if !BR1_WRITE_PROTECT
+	default 0x100 if BR1_WRITE_PROTECT
+
+config BR1_MACHINE
+	hex
+	default 0x0 if BR1_MACHINE_GPCM
+	default 0x20 if BR1_MACHINE_FCM
+	default 0x60 if BR1_MACHINE_SDRAM
+	default 0x80 if BR1_MACHINE_UPMA
+	default 0xa0 if BR1_MACHINE_UPMB
+	default 0xc0 if BR1_MACHINE_UPMC
+
+config BR1_ATOMIC
+	hex
+	default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
+	default 0x0 if BR1_ATOMIC_NONE
+	default 0x4 if BR1_ATOMIC_RAWA
+	default 0x8 if BR1_ATOMIC_WARA
+
+config BR1_VALID_BIT
+	hex
+	default 0x0 if !ELBC_BR1_OR1
+	default 0x1 if ELBC_BR1_OR1
+
+config OR1_AM
+	hex
+	default 0xffff8000 if OR1_AM_32_KBYTES && !BR1_MACHINE_SDRAM
+	default 0xffff0000 if OR1_AM_64_KBYTES
+	default 0xfffe0000 if OR1_AM_128_KBYTES
+	default 0xfffc0000 if OR1_AM_256_KBYTES
+	default 0xfff80000 if OR1_AM_512_KBYTES
+	default 0xfff00000 if OR1_AM_1_MBYTES
+	default 0xffe00000 if OR1_AM_2_MBYTES
+	default 0xffc00000 if OR1_AM_4_MBYTES
+	default 0xff800000 if OR1_AM_8_MBYTES
+	default 0xff000000 if OR1_AM_16_MBYTES
+	default 0xfe000000 if OR1_AM_32_MBYTES
+	default 0xfc000000 if OR1_AM_64_MBYTES
+	default 0xf8000000 if OR1_AM_128_MBYTES
+	default 0xf0000000 if OR1_AM_256_MBYTES
+	default 0xe0000000 if OR1_AM_512_MBYTES
+	default 0xc0000000 if OR1_AM_1_GBYTES
+	default 0x80000000 if OR1_AM_2_GBYTES
+	default 0x00000000 if OR1_AM_4_GBYTES
+
+config OR1_XAM
+	hex
+	default 0x0 if !OR1_XAM_SET
+	default 0x6000 if OR1_XAM_SET
+
+config OR1_BCTLD
+	hex
+	default 0x0 if OR1_BCTLD_ASSERTED
+	default 0x1000 if OR1_BCTLD_NOT_ASSERTED
+
+config OR1_BI
+	hex
+	default 0x0 if !BR1_MACHINE_UPM
+	default 0x0 if OR1_BI_BURSTSUPPORT
+	default 0x100 if OR1_BI_BURSTINHIBIT
+
+config OR1_COLS
+	hex
+	default 0x0 if !BR1_MACHINE_SDRAM
+	default 0x0 if OR1_COLS_7
+	default 0x400 if OR1_COLS_8
+	default 0x800 if OR1_COLS_9
+	default 0xc00 if OR1_COLS_10
+	default 0x1000 if OR1_COLS_11
+	default 0x1400 if OR1_COLS_12
+	default 0x1800 if OR1_COLS_13
+	default 0x1c00 if OR1_COLS_14
+
+config OR1_ROWS
+	hex
+	default 0x0 if !BR1_MACHINE_SDRAM
+	default 0x0 if OR1_ROWS_9
+	default 0x40 if OR1_ROWS_10
+	default 0x80 if OR1_ROWS_11
+	default 0xc0 if OR1_ROWS_12
+	default 0x100 if OR1_ROWS_13
+	default 0x140 if OR1_ROWS_14
+	default 0x180 if OR1_ROWS_15
+
+config OR1_PMSEL
+	hex
+	default 0x0 if !BR1_MACHINE_SDRAM
+	default 0x0 if OR1_PMSEL_BTB
+	default 0x20 if OR1_PMSEL_KEPT_OPEN
+
+config OR1_SCY
+	hex
+	default 0x0 if !BR1_MACHINE_GPCM && !BR1_MACHINE_FCM
+	default 0x0 if OR1_SCY_0
+	default 0x10 if OR1_SCY_1
+	default 0x20 if OR1_SCY_2
+	default 0x30 if OR1_SCY_3
+	default 0x40 if OR1_SCY_4
+	default 0x50 if OR1_SCY_5
+	default 0x60 if OR1_SCY_6
+	default 0x70 if OR1_SCY_7
+	default 0x80 if OR1_SCY_8
+	default 0x90 if OR1_SCY_9
+	default 0xa0 if OR1_SCY_10
+	default 0xb0 if OR1_SCY_11
+	default 0xc0 if OR1_SCY_12
+	default 0xd0 if OR1_SCY_13
+	default 0xe0 if OR1_SCY_14
+	default 0xf0 if OR1_SCY_15
+
+config OR1_PGS
+	hex
+	default 0x0 if !BR1_MACHINE_FCM
+	default 0x0 if OR1_PGS_SMALL
+	default 0x400 if OR1_PGS_LARGE
+
+config OR1_CSCT
+	hex
+	default 0x0 if !BR1_MACHINE_FCM
+	default 0x0 if OR1_CSCT_1_CYCLE
+	default 0x0 if OR1_CSCT_2_CYCLE
+	default 0x200 if OR1_CSCT_4_CYCLE
+	default 0x200 if OR1_CSCT_8_CYCLE
+
+config OR1_CST
+	hex
+	default 0x0 if !BR1_MACHINE_FCM
+	default 0x0 if OR1_CST_COINCIDENT
+	default 0x100 if OR1_CST_QUARTER_CLOCK
+	default 0x0 if OR1_CST_HALF_CLOCK
+	default 0x100 if OR1_CST_ONE_CLOCK
+
+config OR1_CHT
+	hex
+	default 0x0 if !BR1_MACHINE_FCM
+	default 0x0 if OR1_CHT_HALF_CLOCK
+	default 0x80 if OR1_CHT_ONE_CLOCK
+	default 0x0 if OR1_CHT_ONE_HALF_CLOCK
+	default 0x80 if OR1_CHT_TWO_CLOCK
+
+config OR1_RST
+	hex
+	default 0x0 if !BR1_MACHINE_FCM
+	default 0x0 if OR1_RST_THREE_QUARTER_CLOCK
+	default 0x8 if OR1_RST_ONE_CLOCK
+	default 0x0 if OR1_RST_ONE_HALF_CLOCK
+
+config OR1_CSNT
+	hex
+	default 0x0 if !BR1_MACHINE_GPCM
+	default 0x0 if OR1_CSNT_NORMAL
+	default 0x800 if OR1_CSNT_EARLIER
+
+config OR1_ACS
+	hex
+	default 0x0 if !BR1_MACHINE_GPCM
+	default 0x0 if OR1_ACS_SAME_TIME
+	default 0x400 if OR1_ACS_QUARTER_CYCLE_EARLIER
+	default 0x600 if OR1_ACS_HALF_CYCLE_EARLIER
+
+config OR1_XACS
+	hex
+	default 0x0 if !BR1_MACHINE_GPCM
+	default 0x0 if OR1_XACS_NORMAL
+	default 0x100 if OR1_XACS_EXTENDED
+
+config OR1_SETA
+	hex
+	default 0x0 if !BR1_MACHINE_GPCM
+	default 0x0 if OR1_SETA_INTERNAL
+	default 0x8 if OR1_SETA_EXTERNAL
+
+config OR1_TRLX
+	hex
+	default 0x0 if OR1_TRLX_NORMAL
+	default 0x4 if OR1_TRLX_RELAXED
+
+config OR1_EHTR
+	hex
+	default 0x0 if OR1_EHTR_NORMAL
+	default 0x2 if OR1_EHTR_1_CYCLE
+	default 0x0 if OR1_EHTR_4_CYCLE
+	default 0x2 if OR1_EHTR_8_CYCLE
+
+config OR1_EAD
+	hex
+	default 0x0 if ARCH_MPC8308
+	default 0x0 if OR1_EAD_NONE
+	default 0x1 if OR1_EAD_EXTRA

arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2

+menuconfig ELBC_BR2_OR2
+	bool "ELBC BR2/OR2"
+
+if ELBC_BR2_OR2
+
+config BR2_OR2_NAME
+	string "Identifier"
+
+config BR2_OR2_BASE
+	hex "Port base"
+
+choice
+	prompt "Port size"
+
+config BR2_PORTSIZE_8BIT
+	bool "8-bit"
+
+config BR2_PORTSIZE_16BIT
+	depends on !BR2_MACHINE_FCM
+	bool "16-bit"
+
+
+config BR2_PORTSIZE_32BIT
+	depends on !BR2_MACHINE_FCM
+	depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379
+	bool "32-bit"
+
+endchoice
+
+if BR2_MACHINE_FCM
+
+choice
+	prompt "Data Error Checking"
+
+config BR2_ERRORCHECKING_DISABLED
+	bool "Disabled"
+
+config BR2_ERRORCHECKING_ECC_CHECKING
+	bool "ECC checking / No ECC generation"
+
+config BR2_ERRORCHECKING_BOTH
+	bool "ECC checking and generation"
+
+endchoice
+
+endif
+
+config BR2_WRITE_PROTECT
+	bool "Write-protect"
+
+config BR2_MACHINE_UPM
+	bool
+
+choice
+	prompt "Machine select"
+
+config BR2_MACHINE_GPCM
+	bool "GPCM"
+
+config BR2_MACHINE_FCM
+	depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360
+	bool "FCM"
+
+config BR2_MACHINE_SDRAM
+	depends on ARCH_MPC8349 || ARCH_MPC8360
+	bool "SDRAM"
+
+config BR2_MACHINE_UPMA
+	select BR2_MACHINE_UPM
+	bool "UPM (A)"
+
+config BR2_MACHINE_UPMB
+	select BR2_MACHINE_UPM
+	bool "UPM (B)"
+
+config BR2_MACHINE_UPMC
+	select BR2_MACHINE_UPM
+	bool "UPM (C)"
+
+endchoice
+
+if ARCH_MPC8313 || ARCH_MPC8323 || ARCH_MPC8360
+
+choice
+	prompt "Atomic operations"
+
+config BR2_ATOMIC_NONE
+	bool "No atomic operations"
+
+config BR2_ATOMIC_RAWA
+	bool "Read-after-write-atomic"
+
+config BR2_ATOMIC_WARA
+	bool "Write-after-read-atomic"
+
+endchoice
+
+endif
+
+if BR2_MACHINE_GPCM || BR2_MACHINE_FCM || BR2_MACHINE_UPM || BR2_MACHINE_SDRAM
+
+choice
+	prompt "Address mask"
+
+config OR2_AM_32_KBYTES
+	depends on !BR2_MACHINE_SDRAM
+	bool "32 kb"
+
+config OR2_AM_64_KBYTES
+	bool "64 kb"
+
+config OR2_AM_128_KBYTES
+	bool "128 kb"
+
+config OR2_AM_256_KBYTES
+	bool "256 kb"
+
+config OR2_AM_512_KBYTES
+	bool "512 kb"
+
+config OR2_AM_1_MBYTES
+	bool "1 mb"
+
+config OR2_AM_2_MBYTES
+	bool "2 mb"
+
+config OR2_AM_4_MBYTES
+	bool "4 mb"
+
+config OR2_AM_8_MBYTES
+	bool "8 mb"
+
+config OR2_AM_16_MBYTES
+	bool "16 mb"
+
+config OR2_AM_32_MBYTES
+	bool "32 mb"
+
+config OR2_AM_64_MBYTES
+	bool "64 mb"
+
+# XXX: Some boards define 128MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR2_AM_128_MBYTES
+	bool "128 mb"
+
+# XXX: Some boards define 256MB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR2_AM_256_MBYTES
+	bool "256 mb"
+
+config OR2_AM_512_MBYTES
+	depends on BR2_MACHINE_FCM
+	bool "512 mb"
+
+# XXX: Some boards define 1GB AM with GPCM, even though it should not be
+# possible according to the manuals
+config OR2_AM_1_GBYTES
+	bool "1 gb"
+
+config OR2_AM_2_GBYTES
+	depends on BR2_MACHINE_FCM
+	bool "2 gb"
+
+config OR2_AM_4_GBYTES
+	depends on BR2_MACHINE_FCM
+	bool "4 gb"
+
+endchoice
+
+config OR2_XAM_SET
+	bool "Set unused bytes after address mask"
+choice
+	prompt "Buffer control disable"
+
+config OR2_BCTLD_ASSERTED
+	bool "Asserted"
+
+config OR2_BCTLD_NOT_ASSERTED
+	bool "Not asserted"
+
+endchoice
+
+endif
+
+if BR2_MACHINE_GPCM || BR2_MACHINE_FCM
+
+choice
+	prompt "Cycle length in bus clocks"
+
+config OR2_SCY_0
+	bool "No wait states"
+
+config OR2_SCY_1
+	bool "1 wait state"
+
+config OR2_SCY_2
+	bool "2 wait states"
+
+config OR2_SCY_3
+	bool "3 wait states"
+
+config OR2_SCY_4
+	bool "4 wait states"
+
+config OR2_SCY_5
+	bool "5 wait states"
+
+config OR2_SCY_6
+	bool "6 wait states"
+
+config OR2_SCY_7
+	bool "7 wait states"
+
+config OR2_SCY_8
+	depends on BR2_MACHINE_GPCM
+	bool "8 wait states"
+
+config OR2_SCY_9
+	depends on BR2_MACHINE_GPCM
+	bool "9 wait states"
+
+config OR2_SCY_10
+	depends on BR2_MACHINE_GPCM
+	bool "10 wait states"
+
+config OR2_SCY_11
+	depends on BR2_MACHINE_GPCM
+	bool "11 wait states"
+
+config OR2_SCY_12
+	depends on BR2_MACHINE_GPCM
+	bool "12 wait states"
+
+config OR2_SCY_13
+	depends on BR2_MACHINE_GPCM
+	bool "13 wait states"
+
+config OR2_SCY_14
+	depends on BR2_MACHINE_GPCM
+	bool "14 wait states"
+
+config OR2_SCY_15
+	depends on BR2_MACHINE_GPCM
+	bool "15 wait states"
+
+endchoice
+
+endif # BR2_MACHINE_GPCM || BR2_MACHINE_FCM
+
+if BR2_MACHINE_GPCM
+
+choice
+	prompt "Chip select negotiation time"
+
+config OR2_CSNT_NORMAL
+	bool "Normal"
+
+config OR2_CSNT_EARLIER
+	bool "Earlier"
+
+endchoice
+
+choice
+	prompt "Address to chip-select setup"
+
+config OR2_ACS_SAME_TIME
+	bool "At the same time"
+
+config OR2_ACS_HALF_CYCLE_EARLIER
+	bool "Half of a bus clock cycle earlier"
+
+config OR2_ACS_QUARTER_CYCLE_EARLIER
+	bool "Half/Quarter of a bus clock cycle earlier"
+
+endchoice
+
+choice
+	prompt "Extra address to check-select setup"
+
+config OR2_XACS_NORMAL
+	bool "Normal"
+
+config OR2_XACS_EXTENDED
+	bool "Extended"
+
+endchoice
+
+choice
+	prompt "External address termination"
+
+config OR2_SETA_INTERNAL
+	bool "Access is terminated internally"
+
+config OR2_SETA_EXTERNAL
+	bool "Access is terminated externally"
+
+endchoice
+
+endif # BR2_MACHINE_GPCM
+
+if BR2_MACHINE_FCM
+
+choice
+	prompt "NAND Flash EEPROM page size"
+
+config OR2_PGS_SMALL
+	bool "Small page device"
+
+config OR2_PGS_LARGE
+	bool "Large page device"
+
+endchoice
+
+choice
+	prompt "Chip select to command time"
+
+config OR2_CSCT_1_CYCLE
+	depends on OR2_TRLX_NORMAL
+	bool "1 cycle"
+
+config OR2_CSCT_2_CYCLE
+	depends on OR2_TRLX_RELAXED
+	bool "2 cycles"
+
+config OR2_CSCT_4_CYCLE
+	depends on OR2_TRLX_NORMAL
+	bool "4 cycles"
+
+config OR2_CSCT_8_CYCLE
+	depends on OR2_TRLX_RELAXED
+	bool "8 cycles"
+
+endchoice
+
+choice
+	prompt "Command setup time"
+
+config OR2_CST_COINCIDENT
+	depends on OR2_TRLX_NORMAL
+	bool "Coincident with any command"
+
+config OR2_CST_QUARTER_CLOCK
+	depends on OR2_TRLX_NORMAL
+	bool "0.25 clocks after"
+
+config OR2_CST_HALF_CLOCK
+	depends on OR2_TRLX_RELAXED
+	bool "0.5 clocks after"
+
+config OR2_CST_ONE_CLOCK
+	depends on OR2_TRLX_RELAXED
+	bool "1 clock after"
+
+endchoice
+
+choice
+	prompt "Command hold time"
+
+config OR2_CHT_HALF_CLOCK
+	depends on OR2_TRLX_NORMAL
+	bool "0.5 clocks before"
+
+config OR2_CHT_ONE_CLOCK
+	depends on OR2_TRLX_NORMAL
+	bool "1 clock before"
+
+config OR2_CHT_ONE_HALF_CLOCK
+	depends on OR2_TRLX_RELAXED
+	bool "1.5 clocks before"
+
+config OR2_CHT_TWO_CLOCK
+	depends on OR2_TRLX_RELAXED
+	bool "2 clocks before"
+
+endchoice
+
+choice
+	prompt "Reset setup time"
+
+config OR2_RST_THREE_QUARTER_CLOCK
+	depends on OR2_TRLX_NORMAL
+	bool "0.75 clocks prior"
+
+config OR2_RST_ONE_HALF_CLOCK
+	depends on OR2_TRLX_RELAXED
+	bool "0.5 clocks prior"
+
+config OR2_RST_ONE_CLOCK
+	bool "1 clock prior"
+
+endchoice
+
+endif # BR2_MACHINE_FCM
+
+if BR2_MACHINE_UPM
+
+choice
+	prompt "Burst inhibit"
+
+config OR2_BI_BURSTSUPPORT
+	bool "Support burst access"
+
+config OR2_BI_BURSTINHIBIT
+	bool "Inhibit burst access"
+
+endchoice
+
+endif # BR2_MACHINE_UPM
+
+if BR2_MACHINE_SDRAM
+
+choice
+	prompt "Number of column address lines"
+
+config OR2_COLS_7
+	bool "7"
+
+config OR2_COLS_8
+	bool "8"
+
+config OR2_COLS_9
+	bool "9"
+
+config OR2_COLS_10
+	bool "10"
+
+config OR2_COLS_11
+	bool "11"
+
+config OR2_COLS_12
+	bool "12"
+
+config OR2_COLS_13
+	bool "13"
+
+config OR2_COLS_14
+	bool "14"
+
+endchoice
+
+choice
+	prompt "Number of rows address lines"
+
+config OR2_ROWS_9
+	bool "9"
+
+config OR2_ROWS_10
+	bool "10"
+
+config OR2_ROWS_11
+	bool "11"
+
+config OR2_ROWS_12
+	bool "12"
+
+config OR2_ROWS_13
+	bool "13"
+
+config OR2_ROWS_14
+	bool "14"
+
+config OR2_ROWS_15
+	bool "15"
+
+endchoice
+
+choice
+	prompt "Page mode select"
+
+config OR2_PMSEL_BTB
+	bool "Back-to-back"
+
+config OR2_PMSEL_KEPT_OPEN
+	bool "Page kept open until page miss or refresh"
+
+endchoice
+
+endif # BR2_MACHINE_SDRAM
+
+choice
+	prompt "Relaxed timing"
+
+config OR2_TRLX_NORMAL
+	bool "Normal"
+
+config OR2_TRLX_RELAXED
+	bool "Relaxed"
+
+endchoice
+
+choice
+	prompt "Extended hold time"
+
+config OR2_EHTR_NORMAL
+	depends on OR2_TRLX_NORMAL
+	bool "Normal"
+
+config OR2_EHTR_1_CYCLE
+	depends on OR2_TRLX_NORMAL
+	bool "1 idle clock cycle inserted"
+
+config OR2_EHTR_4_CYCLE
+	depends on OR2_TRLX_RELAXED
+	bool "4 idle clock cycles inserted"
+
+config OR2_EHTR_8_CYCLE
+	depends on OR2_TRLX_RELAXED
+	bool "8 idle clock cycles inserted"
+
+endchoice
+
+if !ARCH_MPC8308
+
+choice
+	prompt "External address latch delay"
+
+config OR2_EAD_NONE
+	bool "None"
+
+config OR2_EAD_EXTRA
+	bool "Extra"
+
+endchoice
+
+endif # !ARCH_MPC8308
+
+endif # ELBC_BR2_OR2
+
+config BR2_PORTSIZE
+	hex
+	default 0x800 if BR2_PORTSIZE_8BIT
+	default 0x1000 if BR2_PORTSIZE_16BIT
+	default 0x1800 if BR2_PORTSIZE_32BIT
+
+config BR2_ERRORCHECKING
+	hex
+	default 0x0 if !BR2_MACHINE_FCM
+	default 0x0 if BR2_ERRORCHECKING_DISABLED
+	default 0x200 if BR2_ERRORCHECKING_ECC_CHECKING
+	default 0x400 if BR2_ERRORCHECKING_BOTH
+
+config BR2_WRITE_PROTECT_BIT
+	hex
+	default 0x0 if !BR2_WRITE_PROTECT
+	default 0x100 if BR2_WRITE_PROTECT
+
+config BR2_MACHINE
+	hex
+	default 0x0 if BR2_MACHINE_GPCM
+	default 0x20 if BR2_MACHINE_FCM
+	default 0x60 if BR2_MACHINE_SDRAM
+	default 0x80 if BR2_MACHINE_UPMA
+	default 0xa0 if BR2_MACHINE_UPMB
+	default 0xc0 if BR2_MACHINE_UPMC
+
+config BR2_ATOMIC
+	hex
+	default 0x0 if !ARCH_MPC8313 && !ARCH_MPC8323 && !ARCH_MPC8360
+	default 0x0 if BR2_ATOMIC_NONE
+	default 0x4 if BR2_ATOMIC_RAWA
+	default 0x8 if BR2_ATOMIC_WARA
+
+config BR2_VALID_BIT
+	hex
+	default 0x0 if !ELBC_BR2_OR2
+	default 0x1 if ELBC_BR2_OR2
+
+config OR2_AM
+	hex
+	default 0xffff8000 if OR2_AM_32_KBYTES && !BR2_MACHINE_SDRAM
+	default 0xffff0000 if OR2_AM_64_KBYTES
+	default 0xfffe0000 if OR2_AM_128_KBYTES
+	default 0xfffc0000 if OR2_AM_256_KBYTES
+	default 0xfff80000 if OR2_AM_512_KBYTES
+	default 0xfff00000 if OR2_AM_1_MBYTES
+	default 0xffe00000 if OR2_AM_2_MBYTES
+	default 0xffc00000 if OR2_AM_4_MBYTES
+	default 0xff800000 if OR2_AM_8_MBYTES
+	default 0xff000000 if OR2_AM_16_MBYTES
+	default 0xfe000000 if OR2_AM_32_MBYTES
+	default 0xfc000000 if OR2_AM_64_MBYTES
+	default 0xf8000000 if OR2_AM_128_MBYTES
+	default 0xf0000000 if OR2_AM_256_MBYTES
+	default 0xe0000000 if OR2_AM_512_MBYTES
+	default 0xc0000000 if OR2_AM_1_GBYTES
+	default 0x80000000 if OR2_AM_2_GBYTES
+	default 0x00000000 if OR2_AM_4_GBYTES
+
+config OR2_XAM
+	hex
+	default 0x0 if !OR2_XAM_SET
+	default 0x6000 if OR2_XAM_SET
+
+config OR2_BCTLD
+	hex
+	default 0x0 if OR2_BCTLD_ASSERTED
+	default 0x1000 if OR2_BCTLD_NOT_ASSERTED
+
+config OR2_BI
+	hex
+	default 0x0 if !BR2_MACHINE_UPM
+	default 0x0 if OR2_BI_BURSTSUPPORT
+	default 0x100 if OR2_BI_BURSTINHIBIT
+
+config OR2_COLS
+	hex
+	default 0x0 if !BR2_MACHINE_SDRAM
+	default 0x0 if OR2_COLS_7
+	default 0x400 if OR2_COLS_8
+	default 0x800 if OR2_COLS_9
+	default 0xc00 if OR2_COLS_10
+	default 0x1000 if OR2_COLS_11
+	default 0x1400 if OR2_COLS_12
+	default 0x1800 if OR2_COLS_13
+	default 0x1c00 if OR2_COLS_14
+
+config OR2_ROWS
+	hex
+	default 0x0 if !BR2_MACHINE_SDRAM
+	default 0x0 if OR2_ROWS_9
+	default 0x40 if OR2_ROWS_10
+	default 0x80 if OR2_ROWS_11
+	default 0xc0 if OR2_ROWS_12
+	default 0x100 if OR2_ROWS_13
+	default 0x140 if OR2_ROWS_14
+	default 0x180 if OR2_ROWS_15
+
+config OR2_PMSEL
+	hex
+	default 0x0 if !BR2_MACHINE_SDRAM
+	default 0x0 if OR2_PMSEL_BTB
+	default 0x20 if OR2_PMSEL_KEPT_OPEN
+
+config OR2_SCY
+	hex
+	default 0x0 if !BR2_MACHINE_GPCM && !BR2_MACHINE_FCM
+	default 0x0 if OR2_SCY_0
+	default 0x10 if OR2_SCY_1
+	default 0x20 if OR2_SCY_2
+	default 0x30 if OR2_SCY_3
+	default 0x40 if OR2_SCY_4
+	default 0x50 if OR2_SCY_5
+	default 0x60 if OR2_SCY_6
+	default 0x70 if OR2_SCY_7
+	default 0x80 if OR2_SCY_8
+	default 0x90 if OR2_SCY_9
+	default 0xa0 if OR2_SCY_10
+	default 0xb0 if OR2_SCY_11
+	default 0xc0 if OR2_SCY_12
+	default 0xd0 if OR2_SCY_13
+	default 0xe0 if OR2_SCY_14
+	default 0xf0 if OR2_SCY_15
+
+config OR2_PGS
+	hex
+	default 0x0 if !BR2_MACHINE_FCM
+	default 0x0 if OR2_PGS_SMALL
+	default 0x400 if OR2_PGS_LARGE
+
+config OR2_CSCT
+	hex
+	default 0x0 if !BR2_MACHINE_FCM
+	default 0x0 if OR2_CSCT_1_CYCLE
+	default 0x0 if OR2_CSCT_2_CYCLE
+	default 0x200 if OR2_CSCT_4_CYCLE
+	default 0x200 if OR2_CSCT_8_CYCLE
+
+config OR2_CST
+	hex
+	default 0x0 if !BR2_MACHINE_FCM
+	default 0x0 if OR2_CST_COINCIDENT
+	default 0x100 if OR2_CST_QUARTER_CLOCK
+	default 0x0 if OR2_CST_HALF_CLOCK
+	default 0x100 if OR2_CST_ONE_CLOCK
+
+config OR2_CHT
+	hex
+	default 0x0 if !BR2_MACHINE_FCM
+	default 0x0 if OR2_CHT_HALF_CLOCK
+	default 0x80 if OR2_CHT_ONE_CLOCK
+	default 0x0 if OR2_CHT_ONE_HALF_CLOCK
+	default 0x80 if OR2_CHT_TWO_CLOCK
+
+config OR2_RST
+	hex
+	default 0x0 if !BR2_MACHINE_FCM
+	default 0x0 if OR2_RST_THREE_QUARTER_CLOCK
+	default 0x8 if OR2_RST_ONE_CLOCK
+	default 0x0 if OR2_RST_ONE_HALF_CLOCK
+
+config OR2_CSNT
+	hex
+	default 0x0 if !BR2_MACHINE_GPCM
+	default 0x0 if OR2_CSNT_NORMAL
+	default 0x800 if OR2_CSNT_EARLIER
+
+config OR2_ACS
+	hex
+	default 0x0 if !BR2_MACHINE_GPCM
+	default 0x0 if OR2_ACS_SAME_TIME
+	default 0x400 if OR2_ACS_QUARTER_CYCLE_EARLIER
+	default 0x600 if OR2_ACS_HALF_CYCLE_EARLIER
+
+config OR2_XACS
+	hex
+	default 0x0 if !BR2_MACHINE_GPCM
+	default 0x0 if OR2_XACS_NORMAL
+	default 0x100 if OR2_XACS_EXTENDED
+
+config OR2_SETA
+	hex
+	default 0x0 if !BR2_MACHINE_GPCM
+	default 0x0 if OR2_SETA_INTERNAL
+	default 0x8 if OR2_SETA_EXTERNAL
+
+config OR2_TRLX
+	hex
+	default 0x0 if OR2_TRLX_NORMAL
+	default 0x4 if OR2_TRLX_RELAXED
+
+config OR2_EHTR
+	hex
+	default 0x0 if OR2_EHTR_NORMAL
+	default 0x2 if OR2_EHTR_1_CYCLE
+	default 0x0 if OR2_EHTR_4_CYCLE
+	default 0x2 if OR2_EHTR_8_CYCLE
+
+config OR2_EAD
+	hex
+	default 0x0 if ARCH_MPC8308
+	default 0x0 if OR2_EAD_NONE
+	default 0x1 if OR2_EAD_EXTRA

arch/powerpc/cpu/mpc83xx/elbc/elbc.h

+#ifdef CONFIG_ELBC_BR0_OR0
+#define CONFIG_SYS_BR0_PRELIM (\
+	CONFIG_BR0_OR0_BASE |\
+	CONFIG_BR0_PORTSIZE |\
+	CONFIG_BR0_ERRORCHECKING |\
+	CONFIG_BR0_WRITE_PROTECT_BIT |\
+	CONFIG_BR0_MACHINE |\
+	CONFIG_BR0_ATOMIC |\
+	CONFIG_BR0_VALID_BIT \
+)
+#define CONFIG_SYS_OR0_PRELIM (\
+	CONFIG_OR0_AM |\
+	CONFIG_OR0_XAM |\
+	CONFIG_OR0_BCTLD |\
+	CONFIG_OR0_BI |\
+	CONFIG_OR0_COLS |\
+	CONFIG_OR0_ROWS |\
+	CONFIG_OR0_PMSEL |\
+	CONFIG_OR0_SCY |\
+	CONFIG_OR0_PGS |\
+	CONFIG_OR0_CSCT |\
+	CONFIG_OR0_CST |\
+	CONFIG_OR0_CHT |\
+	CONFIG_OR0_RST |\
+	CONFIG_OR0_CSNT |\
+	CONFIG_OR0_ACS |\
+	CONFIG_OR0_XACS |\
+	CONFIG_OR0_SETA |\
+	CONFIG_OR0_TRLX |\
+	CONFIG_OR0_EHTR |\
+	CONFIG_OR0_EAD \
+)
+#endif /* CONFIG_ELBC_BR0_OR0 */
+
+#ifdef CONFIG_ELBC_BR1_OR1
+#define CONFIG_SYS_BR1_PRELIM (\
+	CONFIG_BR1_OR1_BASE |\
+	CONFIG_BR1_PORTSIZE |\
+	CONFIG_BR1_ERRORCHECKING |\
+	CONFIG_BR1_WRITE_PROTECT_BIT |\
+	CONFIG_BR1_MACHINE |\
+	CONFIG_BR1_ATOMIC |\
+	CONFIG_BR1_VALID_BIT \
+)
+#define CONFIG_SYS_OR1_PRELIM (\
+	CONFIG_OR1_AM |\
+	CONFIG_OR1_XAM |\
+	CONFIG_OR1_BCTLD |\
+	CONFIG_OR1_BI |\
+	CONFIG_OR1_COLS |\
+	CONFIG_OR1_ROWS |\
+	CONFIG_OR1_PMSEL |\
+	CONFIG_OR1_SCY |\
+	CONFIG_OR1_PGS |\
+	CONFIG_OR1_CSCT |\
+	CONFIG_OR1_CST |\
+	CONFIG_OR1_CHT |\
+	CONFIG_OR1_RST |\
+	CONFIG_OR1_CSNT |\
+	CONFIG_OR1_ACS |\
+	CONFIG_OR1_XACS |\
+	CONFIG_OR1_SETA |\
+	CONFIG_OR1_TRLX |\
+	CONFIG_OR1_EHTR |\
+	CONFIG_OR1_EAD \
+)
+#endif /* CONFIG_ELBC_BR1_OR1 */
+
+#ifdef CONFIG_ELBC_BR2_OR2
+#define CONFIG_SYS_BR2_PRELIM (\
+	CONFIG_BR2_OR2_BASE |\
+	CONFIG_BR2_PORTSIZE |\
+	CONFIG_BR2_ERRORCHECKING |\
+	CONFIG_BR2_WRITE_PROTECT_BIT |\
+	CONFIG_BR2_MACHINE |\
+	CONFIG_BR2_ATOMIC |\
+	CONFIG_BR2_VALID_BIT \
+)
+#define CONFIG_SYS_OR2_PRELIM (\
+	CONFIG_OR2_AM |\
+	CONFIG_OR2_XAM |\
+	CONFIG_OR2_BCTLD |\
+	CONFIG_OR2_BI |\
+	CONFIG_OR2_COLS |\
+	CONFIG_OR2_ROWS |\
+	CONFIG_OR2_PMSEL |\
+	CONFIG_OR2_SCY |\
+	CONFIG_OR2_PGS |\
+	CONFIG_OR2_CSCT |\
+	CONFIG_OR2_CST |\
+	CONFIG_OR2_CHT |\
+	CONFIG_OR2_RST |\
+	CONFIG_OR2_CSNT |\
+	CONFIG_OR2_ACS |\
+	CONFIG_OR2_XACS |\
+	CONFIG_OR2_SETA |\
+	CONFIG_OR2_TRLX |\
+	CONFIG_OR2_EHTR |\
+	CONFIG_OR2_EAD \
+)
+#endif /* CONFIG_ELBC_BR2_OR2 */
+
+#ifdef CONFIG_ELBC_BR3_OR3
+#define CONFIG_SYS_BR3_PRELIM (\
+	CONFIG_BR3_OR3_BASE |\
+	CONFIG_BR3_PORTSIZE |\
+	CONFIG_BR3_ERRORCHECKING |\
+	CONFIG_BR3_WRITE_PROTECT_BIT |\
+	CONFIG_BR3_MACHINE |\
+	CONFIG_BR3_ATOMIC |\
+	CONFIG_BR3_VALID_BIT \
+)
+#define CONFIG_SYS_OR3_PRELIM (\
+	CONFIG_OR3_AM |\
+	CONFIG_OR3_XAM |\
+	CONFIG_OR3_BCTLD |\
+	CONFIG_OR3_BI |\
+	CONFIG_OR3_COLS |\
+	CONFIG_OR3_ROWS |\
+	CONFIG_OR3_PMSEL |\
+	CONFIG_OR3_SCY |\
+	CONFIG_OR3_PGS |\
+	CONFIG_OR3_CSCT |\
+	CONFIG_OR3_CST |\
+	CONFIG_OR3_CHT |\
+	CONFIG_OR3_RST |\
+	CONFIG_OR3_CSNT |\
+	CONFIG_OR3_ACS |\
+	CONFIG_OR3_XACS |\
+	CONFIG_OR3_SETA |\
+	CONFIG_OR3_TRLX |\
+	CONFIG_OR3_EHTR |\
+	CONFIG_OR3_EAD \
+)
+#endif /* CONFIG_ELBC_BR3_OR3 */
+
+#ifdef CONFIG_ELBC_BR4_OR4
+#define CONFIG_SYS_BR4_PRELIM (\
+	CONFIG_BR4_OR4_BASE |\
+	CONFIG_BR4_PORTSIZE |\
+	CONFIG_BR4_ERRORCHECKING |\
+	CONFIG_BR4_WRITE_PROTECT_BIT |\
+	CONFIG_BR4_MACHINE |\
+	CONFIG_BR4_ATOMIC |\
+	CONFIG_BR4_VALID_BIT \
+)
+#define CONFIG_SYS_OR4_PRELIM (\
+	CONFIG_OR4_AM |\
+	CONFIG_OR4_XAM |\
+	CONFIG_OR4_BCTLD |\
+	CONFIG_OR4_BI |\
+	CONFIG_OR4_COLS |\
+	CONFIG_OR4_ROWS |\
+	CONFIG_OR4_PMSEL |\
+	CONFIG_OR4_SCY |\
+	CONFIG_OR4_PGS |\
+	CONFIG_OR4_CSCT |\
+	CONFIG_OR4_CST |\
+	CONFIG_OR4_CHT |\
+	CONFIG_OR4_RST |\
+	CONFIG_OR4_CSNT |\
+	CONFIG_OR4_ACS |\
+	CONFIG_OR4_XACS |\
+	CONFIG_OR4_SETA |\
+	CONFIG_OR4_TRLX |\
+	CONFIG_OR4_EHTR |\
+	CONFIG_OR4_EAD \
+)
+#endif /* CONFIG_ELBC_BR4_OR4 */
+
+#if defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_0)
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
+#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_1)
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
+#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_2)
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR2_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR2_PRELIM
+#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_3)
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR3_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR3_PRELIM
+#elif defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_4)
+#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR4_PRELIM
+#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR4_PRELIM
+#endif

arch/powerpc/cpu/mpc83xx/fdt.c

@@ -16,7 +16,7 @@ extern void ft_qe_setup(void *blob);
 DECLARE_GLOBAL_DATA_PTR;
 
 #if defined(CONFIG_BOOTCOUNT_LIMIT) && \
-	(defined(CONFIG_QE) && !defined(CONFIG_MPC831x))
+	(defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X))
 #include <linux/immap_qe.h>
 
 void fdt_fixup_muram (void *blob)
@@ -52,7 +52,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
     defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\
     defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5)
-#ifdef CONFIG_MPC8313
+#ifdef CONFIG_ARCH_MPC8313
 	/*
 	* mpc8313e erratum IPIC1 swapped TSEC interrupt ID numbers on rev. 1
 	* h/w (see AN3545).  The base device tree in use has rev. 1 ID numbers,
@@ -116,14 +116,14 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #endif
 
 #ifdef CONFIG_SYS_NS16550
-	do_fixup_by_compat_u32(blob, "ns16550",
-		"clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
+        do_fixup_by_compat_u32(blob, "ns16550",
+                "clock-frequency", get_serial_clock(), 1);
 #endif
 
 	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 
 #if defined(CONFIG_BOOTCOUNT_LIMIT) && \
-	(defined(CONFIG_QE) && !defined(CONFIG_MPC831x))
+	(defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X))
 	fdt_fixup_muram (blob);
 #endif
 }

arch/powerpc/cpu/mpc83xx/hid/hid.h

+#define CONFIG_SYS_HID0_FINAL ( \
+	CONFIG_HID0_FINAL_ABE_BIT |\
+	CONFIG_HID0_FINAL_CLKOUT |\
+	CONFIG_HID0_FINAL_DCE_BIT |\
+	CONFIG_HID0_FINAL_DCFI_BIT |\
+	CONFIG_HID0_FINAL_DECAREN_BIT |\
+	CONFIG_HID0_FINAL_DLOCK_BIT |\
+	CONFIG_HID0_FINAL_DOZE_BIT |\
+	CONFIG_HID0_FINAL_DPM_BIT |\
+	CONFIG_HID0_FINAL_EBA_BIT |\
+	CONFIG_HID0_FINAL_EBD_BIT |\
+	CONFIG_HID0_FINAL_ECLK_BIT |\
+	CONFIG_HID0_FINAL_ECPE_BIT |\
+	CONFIG_HID0_FINAL_EMCP_BIT |\
+	CONFIG_HID0_FINAL_FBIOB_BIT |\
+	CONFIG_HID0_FINAL_ICE_BIT |\
+	CONFIG_HID0_FINAL_ICFI_BIT |\
+	CONFIG_HID0_FINAL_IFEM_BIT |\
+	CONFIG_HID0_FINAL_ILOCK_BIT |\
+	CONFIG_HID0_FINAL_NAP_BIT |\
+	CONFIG_HID0_FINAL_NOOPTI_BIT |\
+	CONFIG_HID0_FINAL_PAR_BIT |\
+	CONFIG_HID0_FINAL_SBCLK_BIT |\
+	CONFIG_HID0_FINAL_SLEEP_BIT \
+)
+
+#define CONFIG_SYS_HID0_INIT ( \
+	CONFIG_HID0_INIT_ABE_BIT |\
+	CONFIG_HID0_INIT_CLKOUT |\
+	CONFIG_HID0_INIT_DCE_BIT |\
+	CONFIG_HID0_INIT_DCFI_BIT |\
+	CONFIG_HID0_INIT_DECAREN_BIT |\
+	CONFIG_HID0_INIT_DLOCK_BIT |\
+	CONFIG_HID0_INIT_DOZE_BIT |\
+	CONFIG_HID0_INIT_DPM_BIT |\
+	CONFIG_HID0_INIT_EBA_BIT |\
+	CONFIG_HID0_INIT_EBD_BIT |\
+	CONFIG_HID0_INIT_ECPE_BIT |\
+	CONFIG_HID0_INIT_EMCP_BIT |\
+	CONFIG_HID0_INIT_FBIOB_BIT |\
+	CONFIG_HID0_INIT_ICE_BIT |\
+	CONFIG_HID0_INIT_ICFI_BIT |\
+	CONFIG_HID0_INIT_IFEM_BIT |\
+	CONFIG_HID0_INIT_ILOCK_BIT |\
+	CONFIG_HID0_INIT_NAP_BIT |\
+	CONFIG_HID0_INIT_NOOPTI_BIT |\
+	CONFIG_HID0_INIT_PAR_BIT |\
+	CONFIG_HID0_INIT_SLEEP_BIT \
+)
+
+#ifdef CONFIG_TARGET_IDS8313
+/* IDS8313 defines a reserved bit; keep to not break compatibility */
+#define CONFIG_HID2_SPECIAL 0x00020000
+#else
+#define CONFIG_HID2_SPECIAL 0x0
+#endif
+
+#define CONFIG_SYS_HID2 ( \
+	CONFIG_HID2_LET_BIT |\
+	CONFIG_HID2_IFEB_BIT |\
+	CONFIG_HID2_MESISTATE_BIT |\
+	CONFIG_HID2_IFEC_BIT |\
+	CONFIG_HID2_EBQS_BIT |\
+	CONFIG_HID2_EBPX_BIT |\
+	CONFIG_HID2_ELRW_BIT |\
+	CONFIG_HID2_NOKS_BIT |\
+	CONFIG_HID2_HBE_BIT |\
+	CONFIG_HID2_IWLCK |\
+	CONFIG_HID2_ICWP_BIT |\
+	CONFIG_HID2_DWLCK |\
+	CONFIG_HID2_SPECIAL \
+)

arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h

+#ifdef CONFIG_ARCH_MPC8349
+#define TSEC1_MODE_SHIFT 17
+#define TSEC2_MODE_SHIFT 19
+#else
+#define TSEC1_MODE_SHIFT 18
+#define TSEC2_MODE_SHIFT 21
+#endif
+
+#define CONFIG_SYS_HRCW_LOW (\
+	(CONFIG_LBMC_CLOCK_MODE << (31 - 0)) |\
+	(CONFIG_DDR_MC_CLOCK_MODE << (31 - 1)) |\
+	(CONFIG_SYSTEM_PLL_VCO_DIV << (31 - 3)) |\
+	(CONFIG_SYSTEM_PLL_FACTOR << (31 - 7)) |\
+	(CONFIG_CORE_PLL_RATIO << (31 - 15)) |\
+	(CONFIG_QUICC_VCO_DIVIDER << (31 - 25)) |\
+	(CONFIG_QUICC_DIV_FACTOR << (31 - 26)) |\
+	(CONFIG_QUICC_MULT_FACTOR << (31 - 31)) \
+	)
+
+#define CONFIG_SYS_HRCW_HIGH (\
+	(CONFIG_PCI_HOST_MODE << (31 - 0)) |\
+	(CONFIG_PCI_64BIT_MODE << (31 - 1)) |\
+	(CONFIG_PCI_INT_ARBITER1 << (31 - 2)) |\
+	(CONFIG_PCI_INT_ARBITER2 << (31 - 3)) |\
+	(CONFIG_PCI_CLOCK_OUTPUT_DRIVE << (31 - 3)) |\
+	(CONFIG_CORE_DISABLE_MODE << (31 - 4)) |\
+	(CONFIG_BOOT_MEMORY_SPACE << (31 - 5)) |\
+	(CONFIG_BOOT_SEQUENCER << (31 - 7)) |\
+	(CONFIG_SOFTWARE_WATCHDOG << (31 - 8)) |\
+	(CONFIG_BOOT_ROM_INTERFACE << (31 - 13)) |\
+	(CONFIG_TSEC1_MODE << (31 - TSEC1_MODE_SHIFT)) |\
+	(CONFIG_TSEC2_MODE << (31 - TSEC2_MODE_SHIFT)) |\
+	(CONFIG_SECONDARY_DDR_IO << (31 - 27)) |\
+	(CONFIG_TRUE_LITTLE_ENDIAN << (31 - 28)) |\
+	(CONFIG_LALE_TIMING << (31 - 29)) |\
+	(CONFIG_LDP_PIN_MUX_STATE << (31 - 30)) \
+	)

arch/powerpc/cpu/mpc83xx/initreg/Kconfig

+menu "Initial register configuration"
+
+source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr"
+source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig.lcrr"
+
+endmenu

arch/powerpc/cpu/mpc83xx/lblaw/lblaw.h

+#if defined(CONFIG_LBLAW0)
+#define CONFIG_SYS_LBLAWBAR0_PRELIM \
+	CONFIG_LBLAW0_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM (\
+	CONFIG_LBLAW0_ENABLE_BIT |\
+	CONFIG_LBLAW0_LENGTH \
+)
+#endif
+
+#if defined(CONFIG_LBLAW1)
+#define CONFIG_SYS_LBLAWBAR1_PRELIM \
+	CONFIG_LBLAW1_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM (\
+	CONFIG_LBLAW1_ENABLE_BIT |\
+	CONFIG_LBLAW1_LENGTH \
+)
+#endif
+
+#if defined(CONFIG_LBLAW2)
+#define CONFIG_SYS_LBLAWBAR2_PRELIM \
+	CONFIG_LBLAW2_BASE
+#define CONFIG_SYS_LBLAWAR2_PRELIM (\
+	CONFIG_LBLAW2_ENABLE_BIT |\
+	CONFIG_LBLAW2_LENGTH \
+)
+#endif
+
+#if defined(CONFIG_LBLAW3)
+#define CONFIG_SYS_LBLAWBAR3_PRELIM \
+	CONFIG_LBLAW3_BASE
+#define CONFIG_SYS_LBLAWAR3_PRELIM (\
+	CONFIG_LBLAW3_ENABLE_BIT |\
+	CONFIG_LBLAW3_LENGTH \
+)
+#endif
+
+#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_0
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM
+#endif
+
+#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_1
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
+#endif
+
+#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_2
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR2_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR2_PRELIM
+#endif
+
+#ifdef CONFIG_NAND_LBLAWBAR_PRELIM_3
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR3_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR3_PRELIM
+#endif

arch/powerpc/cpu/mpc83xx/sysio/Kconfig

+menu "System I/O configuration"
+
+if ARCH_MPC8308
+source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig.mpc8308"
+endif
+
+endmenu

arch/powerpc/cpu/mpc83xx/u-boot.lds

@@ -52,6 +52,12 @@ SECTIONS
   __ex_table : { *(__ex_table) }
   __stop___ex_table = .;
 
+  /*
+   * _end - This is end of u-boot.bin image.
+   * dtb will be appended here to make u-boot-dtb.bin
+   */
+  _end = .;
+
   . = ALIGN(4096);
   __init_begin = .;
   .text.init : { *(.text.init) }

arch/powerpc/dts/.gitignore

+*.dtb