- 30 7月, 2016 6 次提交
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由 Lokesh Vutla 提交于
According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz clock, so that driver can use the same. Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Wenyou Yang 提交于
Add AT25DF321 flash support. Fix AT25DF321A device name. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Vignesh R 提交于
As per commit b545a98f ("spi: ti_qspi: Add delay for successful bulk erase) says its added to meet bulk erase timing constraints. But bulk erase is a cmd to flash and delay in read path does not make sense. Morever, testing on DRA74/DRA72 evm has shown that this delay is no longer required. Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NJagan Teki <jteki@openedev.com> Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>
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由 Vignesh R 提交于
clk_div is uninitialized at the beginning of ti_spi_set_speed(), move debug() print after clk_div calculation to avoid compiler warning and to have proper value of clk_div printed during debugging. Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NJagan Teki <jteki@openedev.com> Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>
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由 Vignesh R 提交于
Populating QSPI_RD_SNGL bit(0x1) in priv->cmd means that value QSPI_INVAL (0x4) is not written to CMD field of QSPI_SPI_CMD_REG in ti_qspi_cs_deactivate(). Therefore CS is never deactivated between successive READ ID which results in sf probe to fail. Fix this by not populating priv->cmd with QSPI_RD_SNGL and OR it wih priv->cmd as required (similar to the convention followed in the driver). Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NJagan Teki <jteki@openedev.com> Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>
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由 Moritz Fischer 提交于
This commit adds support in the spi-nor driver for the N25Q016A, a 16Mbit SPI NOR flash from Micron. Signed-off-by: NMoritz Fischer <moritz.fischer@ettus.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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- 28 7月, 2016 34 次提交
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由 Fabio Estevam 提交于
Pass the board/freescale/*mx*/ path as files maintained by Stefano Babic. While this is not ideal and does not cover all the i.MX board cases, it gives at least a better hint for the /scripts/get_maintainer.pl tool. Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
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由 Fabio Estevam 提交于
Add an entry for the mx7dsabresd_secure_defconfig target. Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
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由 Stefan Agner 提交于
Use CONFIG_TIMER_CLK_FREQ to let the non-secure init code initialize the generic timer on all CPU's. This allows to make use of the timer freuquency register also on other CPU than the start CPU which is important for KVM. Signed-off-by: NStefan Agner <stefan.agner@toradex.com>
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由 Diego Dorta 提交于
Remove unused define constant. Signed-off-by: NDiego Dorta <diego.dorta@nxp.com> Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
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由 Fabio Estevam 提交于
cgtqmx6eval uses the imx_ddr_size() function to calculate the DDR size in runtime, so there is no need to define PHYS_SDRAM_SIZE. Remove the unneeded definition. Cc: Otavio Salvador <otavio@ossystems.com.br> Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com> Acked-by: NOtavio Salvador <otavio@ossystems.com.br>
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由 Fabio Estevam 提交于
novena uses the imx_ddr_size() function to calculate the DDR size in runtime, so there is no need to define PHYS_SDRAM_SIZE. Remove the unneeded definition. Cc: Marek Vasut <marex@denx.de> Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com> Acked-by: NMarek Vasut <marex@denx.de>
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由 Fabio Estevam 提交于
imx_ddr_size() can be used to calculate the DDR size in runtime. By using this function we no longer need to define PHYS_SDRAM_SIZE. Cc: Martin Donnelly <martin.donnelly@ge.com> Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
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由 Fabio Estevam 提交于
imx_ddr_size() can be used to calculate the DDR size in runtime. By using this function we no longer need to define PHYS_SDRAM_SIZE. Cc: Heiko Schocher <hs@denx.de> Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com> Acked-by: NHeiko Schocher <hs@denx.de>
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由 Fabio Estevam 提交于
imx_ddr_size() can be used to calculate the DDR size in runtime. By using this function we no longer need to define PHYS_SDRAM_SIZE. Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
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由 Breno Lima 提交于
Currently it's recommended to move some configuration options to the defconfig file. Move some USB related options to the defconfig file. Signed-off-by: NBreno Lima <breno.lima@nxp.com>
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由 Stefan Agner 提交于
This commit adds support for the Toradex Computer on Modules Colibri iMX7S/iMX7D. The two modules/SoC's are very similar hence can be easily supported by one board. The board code detects RAM size at runtime which is one of the differences between the two boards. The board also uses the UART's in DTE mode, hence making use of the new DTE support via serial DM. Signed-off-by: NStefan Agner <stefan.agner@toradex.com>
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由 Breno Lima 提交于
It's not necessary to implement the is_mx6q function, there is a macro in sys_proto.h already implemented. Signed-off-by: NBreno Lima <breno.lima@nxp.com> Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
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由 Breno Lima 提交于
It's not necessary to implement the is_mx6q function, there is a macro in sys_proto.h already implemented. Signed-off-by: NBreno Lima <breno.lima@nxp.com> Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
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由 Breno Lima 提交于
It's not necessary to use the is_cpu_type function, there is a macro in sys_proto.h already implemented. Signed-off-by: NBreno Lima <breno.lima@nxp.com> Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
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由 Tim Harvey 提交于
Added removal of the fsl,ext-reset-output property in the wdog node for board revisions that pre-date the addition of the external watchdog reset signal. This property is a recent addition to mainline linux kernel in order to specify that the IMX watchdog external reset should be used instead of the internal chip-level reset. Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
Re-factor the board-specific dt fixups so that they are easier to follow and extend in the future: - use defines for DT paths - use switch/case per board - order models numerically There is no functional change in the code Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
The hwconfig env var allows user to control hardware specific configuration of board specific features but not all Ventana boards have the same features. We will use the magic default value of "_UNKNOWN_" to signify that the bootloader should create this based on detected board model. Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
The GW5520 has 10 DIO's instead of the typical 4 found on the Ventana product family. Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
Replace the static list of board-specific digital I/O's with a dynamic list. Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
Not all Ventana boards have an RS232 transceiver, make it board specific. Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
3b1f6811 caused a regression that removes board info dispaly for Gateworks Ventana boards because it made the invalid assumption that CONFIG_DISPLAY_BOARDINFO_LATE was the same thing as CONFIG_DISPLAY_BOARDINFO. Ventana needs to call show_board_info in late init because we need to have the i2c eeprom based model info. Re-define CONFIG_DISPLAY_BOARDINFO_LATE to allow that to happen. Cc: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
The IMX6 PCIe host controller does not have a proper reset and as such there are several issues that can arise if PCI is enabled in the bootloader follwed by Linux trying to re-configure LTSSM and/or toggling PERST# to the devices. For now, the best approach seems to default to disabling PCI by defaulting pciedisable=1. This can be overridden by the user if they need PCI in the bootloader, for example: - GW552x needing ethernet access in bootloader - GW16082 expansion board needing a device-tree fixup for irq mapping Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
Ventana boards with a PCI Marvell Sky2 GigE MAC require the MAC address to be placed in a DT node in order for the mainline linux driver to obtain it. Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Tim Harvey 提交于
The GW16082 mini-PCI expansion mezzanine uses a TI XIO2001 PCIe-to-PCI bridge with legacy INTA/B/C/D interrupts. These interrupts are assigned in the reverse order according to the PCI spec. If the TI bridge is found on the Ventana PCI bus, add device-tree nodes according to bus enumeration explicitly defining the interrupt mapping to override the default PCI mapping in the Linux kernel. This allows the GW16082 to work with upstream kernels that support device-tree irq parsing. Signed-off-by: NTim Harvey <tharvey@gateworks.com>
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由 Fabio Estevam 提交于
There is no need for introducing MX7_SEC, as there is the CONFIG_ARMV7_BOOT_SEC_DEFAULT option for this purpose. Switch to CONFIG_ARMV7_BOOT_SEC_DEFAULT and get rid of MX7_SEC. Tested by booting a 4.1.15 NXP kernel with mx7dsabresd_secure_defconfig target. Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com> Acked-by: NStefan Agner <stefan.agner@toradex.com>
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由 Stefano Babic 提交于
USB gadget configuration is set in defconfig and must be removed from pico-imx6ul.h. Signed-off-by: NStefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
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由 Stefano Babic 提交于
Signed-off-by: NStefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>
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由 Stefano Babic 提交于
After moving CONFIG_USB_EHCI_MX7 to Kconfig, the flag must be set in defconfig for mx7dsabresd. It is already for the not secure config, it is missing in the secure configuration. Signed-off-by: NStefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@nxp.com> Tested-by: NFabio Estevam <fabio.estevam@nxp.com>
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由 Xu Ziyuan 提交于
It's no need to speed 10 seconds to wait the mmc device out from busy status. 500 milliseconds enough. Signed-off-by: NZiyuan Xu <xzy.xu@rock-chips.com> Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com> Tested-by: NJaehoon Chung <jh80.chung@samsung.com>
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由 Stephen Warren 提交于
Many SoCs allow power to be applied to or removed from portions of the SoC (power domains). This may be used to save power. This API provides the means to control such power management hardware. Signed-off-by: NStephen Warren <swarren@nvidia.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Fix up the call in mmc_load_image_raw_partition() to use the correct function to obtain the MMC device, so that this code can support driver model. Signed-off-by: NSimon Glass <sjg@chromium.org>
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