Move the SUNXI_GMAC config option to Kconfig, remove it
from SYS_EXTRA_OPTIONS and rename it into SUN7I_GMAC.
Signed-off-by: NMylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Add myself as maintainer of the NanoPi NEO Air board.
Signed-off-by: NJelle van der Waa <jelle@vdwaa.nl>
Reviewed-by: NJagan Teki <jagan@openedev.com>

Signed-off-by: NTom Rini <trini@konsulko.com>

The RK3399-Q7 ("Puma") SoM exposes UART0 as the Qseven UART (i.e. the
serial line available via standardised pins on the edge connector and
available on a RS232 connector).

To support boards (such as the RK3399-Q7) that require UART0 as a
debug console, we match CONFIG_DEBUG_UART_BASE and add the appropriate
iomux setup to the rk3399 SPL code.

As we are already touching this code, we also move the board-specific
UART setup (i.e. iomux setup) into board_debug_uart_init(). This will
be called from the debug UART init when CONFIG_DEBUG_UART_BOARD_INIT
is set.

As the RK3399 needs to use its board_debug_uart_init() function, we
have Kconfig enable it by default for RK3399 builds.

With everything set up to define CONFIG_BAUDRATE via defconfig and
with to have the SPL debug UART either on UART0 or UART2, the configs
for the RK3399 EVB are then update (the change for the RK3399-Q7 is
left for later to not cause issues on applying the change).
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

For using mipi display, we need to enable lcd3v3
which supplied by rk808,so enable rk808 first.
Signed-off-by: NEric Gao <eric.gao@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

To enable mipi display, we need to enable pmic
rk808 first for lcd3v3 power,which use i2c0 to
communicate with soc. So enable i2c0.
Signed-off-by: NEric Gao <eric.gao@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

when enable PMIC rk808,the system will halt at very
 early stage,log is shown as bellow.

INFO:    plat_rockchip_pmu_init(1211): pd status 3e
INFO:    BL31: Initializing runtime services
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0x200000
INFO:    SPSR = 0x3c9
time 44561b, 0 (<<----Just stop here)

It's caused by the absence of "{ }" in syscon_rk3399.c
,which will lead to memory overflow like below.According
 to Sysmap file ,we can find the function buck_get_value
of rk808 is just follow the compatible struct,the pointer
"of_match" point to "buck_get_value",but it is not a
struct and don't have member of compatible, In this case,
system crash. So,on the face, it looks like that rk808 is
guilty.but he is really innocent.

while (of_match->compatible) { <<----------
    if (!strcmp(of_match->compatible, compat)) {
    *of_idp = of_match;
    return 0;
    }
    of_match++;
}
Signed-off-by: NEric Gao <eric.gao@rock-chips.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
Tested-by: NKever Yang <kever.yang@rock-chips.com>

The RK3399-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230
connector) system-on-module from Theobroma Systems, featuring the
Rockchip RK3399.

It provides the following feature set:
 * up to 4GB DDR3
 * on-module SPI-NOR flash
 * on-module eMMC (with 8-bit interace)
 * SD card (on a baseboad) via edge connector
 * Gigabit Ethernet w/ on-module Micrel KSZ9031 GbE PHY
 * HDMI/eDP/MIPI displays
 * 2x MIPI-CSI
 * USB
   - 1x USB 3.0 dual-role (direct connection)
   - 2x USB 3.0 host + 1x USB 2.0 (on-module USB 3.0 hub)
 * on-module STM32 Cortex-M0 companion controller, implementing:
   - low-power RTC functionality (ISL1208 emulation)
   - fan controller (AMC6821 emulation)
   - USB<->CAN bridge controller

Note that we use a multi-payload FIT image for booting and have
Cortex-M0 payload in a separate subimage: we thus rely on the FIT
image loader to put it into the SRAM region that ATF expects it in.
Signed-off-by: NKlaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Fixed build warning on puma-rk3399:
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The RK3399-Q7 (Puma) DTS should (of course) be dual-licensed.
This updates the licensing info in the rk3399-puma.dts.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The warm-reset of rk3188 socs keeps the remap setting as it was, so if
it was enabled, the cpu would start from address 0x0 of the sram instead
of address 0x0 of the bootrom, thus making the reset hang.

Therefore make sure the remap is disabled before attempting a warm reset.

Cold reset is not affected by this at all.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NSimon Glass <sjg@chromium.org>

The lower address is reserved for ATF, do not use it.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Most Rockchip socs have the ability to either map the bootrom or a sram
area to the starting address of the cpu by flipping a bit in the GRF.

Newer socs leave this untouched and mapped to the bootrom but the legacy
loaders on rk3188 and before enabled the remap functionality and the
current smp implementation in the Linux kernel also requires it to be
enabled, to bring up secondary cpus.

So to keep smp working in the kernel, mimic the behaviour of the legacy
bootloaders and enable the remap functionality.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NSimon Glass <sjg@chromium.org>

Somehow 43b5c78d ("rockchip: cosmetic: Sort RK3288 boards") moved
the rock board in between some rk3288 board, probably as a result of
rebasing.

So move it back to its original position above all rk3288 boards.

Fixes: 43b5c78d ("rockchip: cosmetic: Sort RK3288 boards")
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NSimon Glass <sjg@chromium.org>

Now that most rockchip SoC based board have usb host support, enable
USB boot targets by default.
Signed-off-by: NEddie Cai <eddie.cai.linux@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Fixed build errors when CONFIG_CMD_USB not defined:
Signed-off-by: NSimon Glass <sjg@chromium.org>

tinker board support ethernet and usb host, so enable USB, PXE and DHCP support.
Signed-off-by: NEddie Cai <eddie.cai.linux@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: NSimon Glass <sjg@chromium.org>

The RK3399 hangs during DMA of the Designware MMC controller, when
performing DMA-based transactions in SPL due to the DDR security settings
left behind by the BootROM (i.e. accesses to the first MB of DRAM are
restricted... however, the DMA is likely to target this first MB, as it
transfers from/to the stack).

System security is not affected, as the final security configuration is
performed by the ATF, which is executed after the SPL stage.

With this fix in place, we can now drop 'fifo-mode' in the DTS for the
RK3399-Q7 (Puma).
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>

Due to the introduction of the pinctrl and clk driver, and using
device tree files, remove the unneeded hardcoded pin configuration
and clock enabling code from the board file.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>

Update the configuration files to support the device tree and driver
model, so do SPL. The device clock and pins configuration are handled
by the clock and the pinctrl drivers respectively.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Fix build error with sama5d3_xplained_mmc:
Signed-off-by: NSimon Glass <sjg@chromium.org>

Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>

Due to the introduction of the pinctrl and clk driver, and using
device tree files, remove the unneeded hardcoded pin configuration
and clock enabling code from the board file.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Remove CONFIG_PHY_MICREL as per previous patch:
Signed-off-by: NSimon Glass <sjg@chromium.org>

Update the configuration files to support the device tree and
driver model, so do SPL. The device clock and pins configuration
are handled by the clock and the pinctrl drivers respectively.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Add back CONFIG_PHY_MICREL to prevent a build error:
Signed-off-by: NSimon Glass <sjg@chromium.org>

When driver model is used for LEDs, provide a command to allow LED access.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NZiping Chen <techping.chan@gmail.com>

The existing 'led' command does not support driver model. Rename it to
indicate that it is legacy code.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NZiping Chen <techping.chan@gmail.com>

Allow LEDs to be blinked if the driver supports it. Enable this for
sandbox so that the tests run.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NZiping Chen <techping.chan@gmail.com>

Add support for toggling an LED into the uclass interface. This can be
efficiently implemented by the driver.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NZiping Chen <techping.chan@gmail.com>

It is useful to be able to read the LED as well as write it. Add this to
the uclass and update the GPIO driver.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NZiping Chen <techping.chan@gmail.com>

At present this is very simple, supporting only on and off. We want to
also support toggling and blinking. As a first step, change the name of
the main method and use an enum to indicate the state.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NZiping Chen <techping.chan@gmail.com>

These structures are normally named with 'uc' instead of 'uclass'. Change
this one for consistency.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NZiping Chen <techping.chan@gmail.com>

There should be a blank line between each option. Add one before LED_GPIO.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NZiping Chen <techping.chan@gmail.com>

Add some LEDs to the standard sandbox device tree.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NZiping Chen <techping.chan@gmail.com>

With DM_SCSI enabled, blk_create_devicef() is called with blkz = 0, leading
to a divide-by-0 exception.
scsi_detect_dev() can be used to get the required parameters (block size
and number of blocks) from the drive before calling blk_create_devicef().
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

We might want to get information about the scsi device without initializing the partition.
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This is a cosmetic change. target and LUN have kind of the same role in
this function. One of them was passed as a parameter and the other was
embedded in a structure. For consistency, pass both of them as parameters.
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

When CONFIG_DM_SCSI is defined, the SATA initialization will be implemented
in the scsi-uclass driver.
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

All the clocks which has to be enabled has to be done in
enable_basic_clocks(), so moving enable sata clock to common
clocks enable function.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>