- Move ANDROID_IMAGE_SUPPORT to top level Kconfig under images as it's
  not strictly part of fastboot.
- Add some defaults for the fastboot buffer location and size
- Migrate all options listed in cmd/fastboot/Kconfig
- Cleanup the README
Signed-off-by: NTom Rini <trini@konsulko.com>

This syncs all of the currently Kconfig'd symbols out of the headers and
into the defconfig files.  This has two exceptions, first am335x_evm
needs to be converted to DM in SPL and then it can stop undef'ing
CONFIG_DM_USB.  Leaving this as-is results in a build failure, and
without work, run time failure.  The other case is am43xx_evm.h and in
turn am43xx_evm_usbhost_boot.  The problem here is that we need DWC3 USB
host mode in SPL, but still desire to have gadget mode in U-Boot proper.
Signed-off-by: NTom Rini <trini@konsulko.com>

This reverts commit 1d201704, reversing
changes made to 6aee2ab6.

The mxc_ipuv3_fb.c changes introduce build failures on some targets.
Signed-off-by: NTom Rini <trini@konsulko.com>

SUNXI_GMAC was still used to configure the code where as the
same has been renamed and moved to Kconfig in below commit
"sunxi: Move SUNXI_GMAC to Kconfig"
(sha1: 4d43d065)
Signed-off-by: NDave Prue <dave@prue.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJagan Teki <jagan@openedev.com>
Reviewed-by: NMark Kettenis <kettenis@openbsd.org>
Tested-by: NMark Kettenis <kettenis@openbsd.org>
[Tweek commit message, config_whitelist.txt, build-whitelist.sh]
Signed-off-by: NJagan Teki <jagan@openedev.com>

Signed-off-by: NTom Rini <trini@konsulko.com>

Conflicts:
	configs/imx6qdl_icore_mmc_defconfig
	configs/imx6qdl_icore_rqs_defconfig

- add {ofnode,dev}_read_resource_byname
- provide DT probe hook to Denali NAND driver
- update clk/reset driver
- update DT
- misc cleanups

When enabling the new mmc timing mode, we inadvertently clear all the
remaining bits in the new timing mode register. The bits cleared
include a default phase delay on the output clock. The BSP kernel
states that the default values are supposed to be used. Clearing them
results in decreased performance or transfer errors on some boards.

Fixes: de9b1771 ("mmc: sunxi: Support new mode")
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>

Add Falcon mode support in Engicam i.CoreM6 board.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

Memory dt node update introduced by spl_fixup_fdt() in below
commit was making DDR configuration in-appropriate
to boot falcon mode. Hence added dram_init_banksize for
explicit assignment of  proper base and size of DDR.

"boot: fdt: Perform arch_fixup_fdt() on the given device tree for falcon boot"
(sha1: 6e7585bb)
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

The NXP i.MX 6UL and 6ULL do not support SATA and have no SATA
boot mode, hence remove it from the boot device detecion. This
fixes a build error introduced with 3bd1642d ("imx: fix USB
boot mode detection for i.MX 6UL and 6ULL")

Fixes: 3bd1642d ("imx: fix USB boot mode detection for i.MX 6UL and 6ULL")
Signed-off-by: NStefan Agner <stefan.agner@toradex.com>
Reviewed-by: NStefano Babic <sbabic@denx.de>
Reviewed-by: NJagan Teki <jagan@openedev.com>

U-boots spi-nor support is currently considered a work in progress. For
now to avoid issues it is necessary to add a "spi-flash" compatible
string. Eventually the "jedec,spi-nor" will be sufficient when the core
U-boot code is updated to support it.
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Now the entry to the NAND driver init can be is controlled by DT;
it should not hurt to compile the driver all the time.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The system bus is not enabled by default for NAND, eMMC boot
etc. of PXs3.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This imply was added when the option was moved by the moveconfig tool,
but the intention is not clear.  Move it to defconfig.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Support PXs3 SoC and its reference development board.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Import updates queued up for Linux 4.14-rc1.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

LD20 has SD ctrl instead of MIO ctrl.  LD11 has both of them.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Support system clocks for LD4, Pro4, sLD8, Pro5, PXs2/LD6b, LD11, LD20.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Signed-off-by: NDai Okamura <okamura.dai@socionext.com>
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This is now set up by the pinctrl driver when the NAND driver is
probed.  Remove the legacy code.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Migrate to the DT-based NAND init entry.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

CONFIG_NAND_DENALI select's CONFIG_SYS_NAND_SELF_INIT, so the
NAND initialization process is driven by the driver itself.
CONFIG_SYS_NAND_MAX_CHIPS and CONFIG_SYS_NAND_BASE are unused.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The new SoC PXs3 changed the address of PLL, but still uses the
same PLL name.  We can not define SC_*PLLCTRL in the common header.
Move them to per-SoC .c file.  Also, fix some PLL comments.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The #include <common.h> was added for mdelay().  Later, the declaration
of mdelay was moved to <linux/delay.h> by commit 5bc516ed ("delay:
collect {m, n, u}delay declarations to include/linux/delay.h").

There is no need to include <common.h> now.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

A patch for NAND uclass support was proposed about half a year ago:
https://patchwork.ozlabs.org/patch/722282/

It was not merged and I do not see on-going work for this.

Without DM-based probing, we need to set up pinctrl etc. in an ad-hoc
way and give lots of crappy CONFIG options for base addresses and
properties, which are supposed to be specified by DT.  This is painful.

This commit just provides a probe hook to retrieve "reg" from DT and
allocate private data in a DM manner.  This DT driver is not essentially
a NAND driver, in fact it is (ab)using UCLASS_MISC.  Once UCLASS_NAND is
supported, it would be possible to migrate to it.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Linux supports platform_get_resource_byname() to look up a resource
by name.

We want a similar helper.  It is useful when a device node has named
register regions.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Boards can skip display interface init using board_video_skip().
If display interface was not initialized (e.g. no ipuv3 framebuffer
registered or IPU clock disabled), booting Linux stops due to the
crash in IPU shutdown function, when accessing IPU registers.
Check IPU clock and skip shutdown if clock is not enabled.
Signed-off-by: NAnatolij Gustschin <agust@denx.de>

U-Boot proper is using DM_MMC so, enable CONFIG_BLK otherwise
find_mmc_device failed to detect MMC device.
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
Reviewed-by: NStefano Babic <sbabic@denx.de>

The soc_boot_modes array is only used by bmode command
and not needed in SPL. Don't include it into SPL.
Signed-off-by: NAnatolij Gustschin <agust@denx.de>
Reviewed-by: NStefano Babic <sbabic@denx.de>

The GPT timer was already initialised in board_init_f() as
it is needed in dram init. Do not repeat timer init in
board_init_r().
Signed-off-by: NAnatolij Gustschin <agust@denx.de>
Acked-by: NStefano Babic <sbabic@denx.de>

There is no need to clear the control register 100 times in a
loop, a single zero write clears the register. I didn't find any
justification why clearing this register in a loop is needed
(no info in i.MX6 errata or GPT timer linux driver, linux driver
uses single write to clear this control register).
Signed-off-by: NAnatolij Gustschin <agust@denx.de>
Acked-by: NStefano Babic <sbabic@denx.de>

In case of 2 banks, the address space of the first CS must be defined
and not let to the higher value.

Add support for SOM with a single bank of RAM. It was tested with i.MX6Q
modules in the following configurations:

- 2 Banks, 4 GB
- 2 Banks, 1 GB
- 1 Bank,  1 GB
Signed-off-by: NStefano Babic <sbabic@denx.de>

Signed-off-by: NTom Rini <trini@konsulko.com>