- 20 2月, 2007 5 次提交
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
This patch switches to the desired I2C bus when the date/dtt commands are called. This can be configured using the CFG_RTC_BUS_NUM and/or CFG_DTT_BUS_NUM defines. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
This patch adds support for the DDR2 controller used on the 440SP and 440SPe. It is tested on the Katmai (440SPe) eval board and works fine with the following DIMM modules: - Corsair CM2X512-5400C4 (512MByte per DIMM) - Kingston ValueRAM KVR667D2N5/512 (512MByte per DIMM) - Kingston ValueRAM KVR667D2N5K2/2G (1GByte per DIMM) This patch also adds the nice functionality to dynamically create the TLB entries for the SDRAM (tlb.c). So we should never run into such problems with wrong (too short) TLB initialization again on these platforms. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Since the existing 4xx SPD SDRAM initialization routines for the 405 SDRAM controller and the 440 DDR controller don't have much in common this patch splits both drivers into different files. This is in preparation for the 440 DDR2 controller support (440SP/e). Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
This patch adds support for multiple I2C busses on the PPC4xx platforms. Define CONFIG_I2C_MULTI_BUS in the board config file to make use of this feature. It also merges the 405 and 440 i2c header files into one common file 4xx_i2c.h. Also the 4xx i2c reset procedure is reworked since I experienced some problems with the first access on the 440SPe Katmai board. Signed-off-by: NStefan Roese <sr@denx.de>
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- 02 2月, 2007 2 次提交
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由 Stefan Roese 提交于
Previously the strapping DCR/SDR was read to determine if the internal PCI arbiter is enabled or not. This strapping bit can be overridden, so now the current status is read from the correct DCR/SDR register. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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- 01 2月, 2007 1 次提交
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由 Stefan Roese 提交于
When PCI PNP is enabled the pci pnp configuration routine is called which sets the PCI_CACHE_SIZE_LINE to 8. This seems to generate some problems with some PCI cards. For now disable the PCI PNP configuration. Signed-off-by: NStefan Roese <sr@denx.de>
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- 31 1月, 2007 7 次提交
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Signed-off-by: NReinhard Arlt <reinhard.arlt@esd-electronics.com>
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由 Stefan Roese 提交于
Signed-off-by: NReinhard Arlt <reinhard.arlt@esd-electronics.com>
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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由 Wolfgang Denk 提交于
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由 Stefan Roese 提交于
The config file now handles the 2nd target, the Rainier (440GRx) evaluation board better. Additionally the PPC input clock was adjusted to match the correct value of 33.0 MHz. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Now the AMCC eval boards Yosemite (440EP) and Yellowstone (440GR) share one config file and all board specific files. This way we don't have to maintain two different sets of files for nearly identical boards. Signed-off-by: NStefan Roese <sr@denx.de>
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- 30 1月, 2007 4 次提交
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由 Stefan Roese 提交于
SCPU doesn't use redundant environment in flash. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Wolfgang Denk 提交于
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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由 Wolfgang Denk 提交于
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- 24 1月, 2007 3 次提交
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由 Gary Jennejohn 提交于
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由 Wolfgang Denk 提交于
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由 Bartlomiej Sieka 提交于
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- 23 1月, 2007 3 次提交
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由 Bartlomiej Sieka 提交于
currently sectors 0-3. Sector 3 does not need to be protected, though (U-boot occupies sectors 0-1 and the environment sector 2). This commit fixes this, i.e., only sectors 0-2 are protected.
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由 Bartlomiej Sieka 提交于
"mii device" results in "Unexpected exception"). Fixing this properly requires some clean-up in the FEC drivers infrastructure for ColdFire, so this commit disables MII commads for now.
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由 Bartlomiej Sieka 提交于
Identification Register (CIR).
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- 20 1月, 2007 4 次提交
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由 Wolfgang Denk 提交于
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由 Wolfgang Denk 提交于
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由 Heiko Schocher 提交于
Signed-off-by: NHeiko Schocher <hs@denx.de>
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由 Heiko Schocher 提交于
if you must swap the bytes between reading/writing. (Needed for the SC3 board) Signed-off-by: NHeiko Schocher <hs@denx.de>
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- 19 1月, 2007 1 次提交
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由 Wolfgang Denk 提交于
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- 18 1月, 2007 6 次提交
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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由 Heiko Schocher 提交于
The EBC Configuration Register is now by CFG_EBC_CFG definable Added JFFS2 support for the SC3 board. Signed-off-by: NHeiko Schocher <hs@denx.de>
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由 Stefan Roese 提交于
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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- 17 1月, 2007 1 次提交
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由 Wolfgang Denk 提交于
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- 16 1月, 2007 1 次提交
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由 Wolfgang Denk 提交于
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- 15 1月, 2007 2 次提交
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由 Wolfgang Denk 提交于
Some code cleanup.
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由 Wolfgang Denk 提交于
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