This is the first step to use DM support for the KM powerpc boards.
Signed-off-by: NHolger Brunck <holger.brunck@ch.abb.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
CC: Mario Six <mario.six@gdsys.cc>
CC: Wolfgang Denk <wd@denx.de>
CC: Valentin Longchamp <valentin.longchamp@ch.abb.com>
CC: Priyanka Jain <priyanka.jain@nxp.com>

Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Signed-off-by: NRan Wang <ran.wang_1@nxp.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>

Some of t1042 boards fails DDR init with an Automatic calibration error
every now and then. Investigations revealed that true Warm boots
never failed. Warm boots has some extra steps performed, one being
to start DDRC in Self Refresh and then clearing SR right after.
Applying this SR method unconditionally made all our boards
stable again, regardless of Cold/Warm boot.
Signed-off-by: NJoakim Tjernlund <joakim.tjernlund@infinera.com>
Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>

CONFIG_CONS_INDEX is nowhere used for this board, we can drop it.
Signed-off-by: NHolger Brunck <holger.brunck@ch.abb.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
CC: Priyanka Jain <priyanka.jain@nxp.com>
CC: Valentin Longchamp <valentin.longchamp@ch.abb.com>

We can use the existing CONFIG_SYS_CONFIG_NAME define for that and
remove the option. Also fix the boot string for all km83xx boards.
Signed-off-by: NHolger Brunck <holger.brunck@ch.abb.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
CC: Priyanka Jain <priyanka.jain@nxp.com>
CC: Valentin Longchamp <valentin.longchamp@ch.abb.com>

Remove this from the board header files and move it to Kconfig. Also use
the correct default address for kmtegr1.
Signed-off-by: NHolger Brunck <holger.brunck@ch.abb.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
CC: Priyanka Jain <priyanka.jain@nxp.com>
CC: Valentin Longchamp <valentin.longchamp@ch.abb.com>

On kmtegr1 we have to specify the second localbus clock signal also
instead of using the default for our ppc 8309 boards.
Signed-off-by: NHolger Brunck <holger.brunck@ch.abb.com>
Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
CC: Priyanka Jain <priyanka.jain@nxp.com>
CC: Valentin Longchamp <valentin.longchamp@ch.abb.com>

- Various x86 common codes updated for TPL/SPL
- I2C designware driver updated for PCI
- ICH SPI driver updated to support Apollo Lake
- Add Intel FSP2 base support
- Intel Apollo Lake platform specific drivers support
- Add a new board Google Chromebook Coral

i2c: for next
- misc: i2c_eeprom:
  Add partition support and add ability to query size
  of eeprom device and partitions
- i2c common:
  add support for offset overflow in to address and add
  sandbox tests for it.

Add ability to query size of eeprom device and partitions
Signed-off-by: NRobert Beckett <bob.beckett@collabora.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

Add ability to partition eeprom via devicetree bindings
Signed-off-by: NRobert Beckett <bob.beckett@collabora.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

Add support for setting the chip address offset mask to EEPROM sumulator
and add tests to test it.
Signed-off-by: NRobert Beckett <bob.beckett@collabora.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

Improve i2c EEPROM simulator testing by providing access functions to
check the previous chip addr and offset.

Given that we can now directly test the offsets, also simplified the
offset mapping and allow for wrapping acceses.
Signed-off-by: NRobert Beckett <bob.beckett@collabora.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

Some devices (2 wire eeproms for example) use some bits from the chip
address to represent the high bits of the offset instead of or as well
as using multiple bytes for the offset, effectively stealing chip
addresses on the bus.

Add a chip offset mask that can be set for any i2c chip which gets
filled with the offset overflow during offset setup.
Signed-off-by: NRobert Beckett <bob.beckett@collabora.com>
Signed-off-by: NIan Ray <ian.ray@ge.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

Add support for coral which is a range of Apollo Lake-based Chromebook
released in 2017. This also includes reef released in 2016, since it is
based on the same SoC.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

The memory and silicon init parts of the FSP need support code to work.
Add this for Apollo Lake.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

These are mostly specific to a particular SoC. Add the definitions for
Apollo Lake.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Add basic plumbing to allow Apollo Lake support to be used.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Adds a driver for the Apollo Lake Primary-to-sideband bus. This supports
various child devices. It supposed both device tree and of-platdata.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Add code to init the system both in TPL and SPL. Each phase has its own
procedure.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Add a bare-bones CPU driver so that CPUs can be probed.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Add loaders for SPL and TPL so that the next stage can be loaded from
memory-mapped SPI or, failing that, the Fast SPI driver.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>