Skip to content

U
U-Boot.Mirror

OS / U-Boot.Mirror

通知 1
Star 0
Fork 0
U
U-Boot.Mirror

体验新版 GitCode，发现更多精彩内容 >>

提交 c0912f9b 编写于 作者: T Tom Rini
浏览文件
操作

Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-x86 into next 

- Various x86 common codes updated for TPL/SPL
- I2C designware driver updated for PCI
- ICH SPI driver updated to support Apollo Lake
- Add Intel FSP2 base support
- Intel Apollo Lake platform specific drivers support
- Add a new board Google Chromebook Coral
上级 533c9f57 a1d6dc3f
展开全部 隐藏空白更改
内联 并排
Showing with 12370 addition and 706 deletion
Kconfig
浏览文件 @ c0912f9b
......@@ -545,9 +545,14 @@ config SYS_EXTRA_OPTIONS
configuration to Kconfig. Since this option will be removed sometime,
new boards should not use this option.
config SYS_TEXT_BASE
config HAVE_SYS_TEXT_BASE
bool
depends on !NIOS2 && !XTENSA
depends on !EFI_APP
default y
config SYS_TEXT_BASE
depends on HAVE_SYS_TEXT_BASE
default 0x80800000 if ARCH_OMAP2PLUS || ARCH_K3
default 0x4a000000 if ARCH_SUNXI && !MACH_SUN9I && !MACH_SUN8I_V3S
default 0x2a000000 if ARCH_SUNXI && MACH_SUN9I
......@@ -556,8 +561,6 @@ config SYS_TEXT_BASE
help
The address in memory that U-Boot will be running from, initially.
config SYS_CLK_FREQ
depends on ARC || ARCH_SUNXI || MPC83xx
int "CPU clock frequency"
......
arch/Kconfig
浏览文件 @ c0912f9b
......@@ -133,6 +133,9 @@ config SANDBOX
imply PHYLIB
imply DM_MDIO
imply DM_MDIO_MUX
imply ACPI_PMC
imply ACPI_PMC_SANDBOX
imply CMD_PMC
config SH
bool "SuperH architecture"
......@@ -183,12 +186,14 @@ config X86
imply USB_HOST_ETHER
imply PCH
imply RTC_MC146818
imply IRQ
# Thing to enable for when SPL/TPL are enabled: SPL
imply SPL_DM
imply SPL_OF_LIBFDT
imply SPL_DRIVERS_MISC_SUPPORT
imply SPL_GPIO_SUPPORT
imply SPL_PINCTRL
imply SPL_LIBCOMMON_SUPPORT
imply SPL_LIBGENERIC_SUPPORT
imply SPL_SERIAL_SUPPORT
......@@ -200,14 +205,12 @@ config X86
imply SPL_SYSCON
# TPL
imply TPL_DM
imply TPL_OF_LIBFDT
imply TPL_DRIVERS_MISC_SUPPORT
imply TPL_GPIO_SUPPORT
imply TPL_PINCTRL
imply TPL_LIBCOMMON_SUPPORT
imply TPL_LIBGENERIC_SUPPORT
imply TPL_SERIAL_SUPPORT
imply TPL_SPI_FLASH_SUPPORT
imply TPL_SPI_SUPPORT
imply TPL_OF_CONTROL
imply TPL_TIMER
imply TPL_REGMAP
......
arch/arm/include/asm/omap_gpio.h
浏览文件 @ c0912f9b
......@@ -22,7 +22,7 @@
#include <asm/arch/cpu.h>
#ifdef CONFIG_DM_GPIO
#if CONFIG_IS_ENABLED(DM_GPIO)
/* Information about a GPIO bank */
struct omap_gpio_platdata {
......
arch/arm/mach-at91/include/mach/at91sam9260.h
浏览文件 @ c0912f9b
......@@ -133,7 +133,7 @@
/*
* Other misc defines
*/
#ifndef CONFIG_DM_GPIO
#if !CONFIG_IS_ENABLED(DM_GPIO)
#define ATMEL_PIO_PORTS 3 /* these SoCs have 3 PIO */
#define ATMEL_BASE_PIO ATMEL_BASE_PIOA
#endif
......
arch/arm/mach-davinci/include/mach/gpio.h
浏览文件 @ c0912f9b
......@@ -18,7 +18,7 @@
#define davinci_gpio_bank67 ((struct davinci_gpio *)DAVINCI_GPIO_BANK67)
#define davinci_gpio_bank8 ((struct davinci_gpio *)DAVINCI_GPIO_BANK8)
#ifndef CONFIG_DM_GPIO
#if !CONFIG_IS_ENABLED(DM_GPIO)
#define gpio_status() gpio_info()
#endif
#define GPIO_NAME_SIZE 20
......
arch/arm/mach-omap2/am33xx/board.c
浏览文件 @ c0912f9b
......@@ -116,7 +116,7 @@ U_BOOT_DEVICES(am33xx_i2c) = {
};
#endif
#ifdef CONFIG_DM_GPIO
#if CONFIG_IS_ENABLED(DM_GPIO)
static const struct omap_gpio_platdata am33xx_gpio[] = {
{ 0, AM33XX_GPIO0_BASE },
{ 1, AM33XX_GPIO1_BASE },
......@@ -141,7 +141,7 @@ U_BOOT_DEVICES(am33xx_gpios) = {
#endif
#endif
#ifndef CONFIG_DM_GPIO
#if !CONFIG_IS_ENABLED(DM_GPIO)
static const struct gpio_bank gpio_bank_am33xx[] = {
{ (void *)AM33XX_GPIO0_BASE },
{ (void *)AM33XX_GPIO1_BASE },
......
arch/arm/mach-omap2/omap3/board.c
浏览文件 @ c0912f9b
......@@ -33,7 +33,7 @@ extern omap3_sysinfo sysinfo;
static void omap3_invalidate_l2_cache_secure(void);
#endif
#ifdef CONFIG_DM_GPIO
#if CONFIG_IS_ENABLED(DM_GPIO)
#if !CONFIG_IS_ENABLED(OF_CONTROL)
/* Manually initialize GPIO banks when OF_CONTROL doesn't */
static const struct omap_gpio_platdata omap34xx_gpio[] = {
......
arch/arm/mach-omap2/omap5/hwinit.c
浏览文件 @ c0912f9b
......@@ -25,7 +25,7 @@
u32 *const omap_si_rev = (u32 *)OMAP_SRAM_SCRATCH_OMAP_REV;
#ifndef CONFIG_DM_GPIO
#if !CONFIG_IS_ENABLED(DM_GPIO)
static struct gpio_bank gpio_bank_54xx[8] = {
{ (void *)OMAP54XX_GPIO1_BASE },
{ (void *)OMAP54XX_GPIO2_BASE },
......
arch/sandbox/cpu/state.c
浏览文件 @ c0912f9b
......@@ -356,6 +356,7 @@ void state_reset_for_test(struct sandbox_state *state)
/* No reset yet, so mark it as such. Always allow power reset */
state->last_sysreset = SYSRESET_COUNT;
state->sysreset_allowed[SYSRESET_POWER_OFF] = true;
state->allow_memio = false;
memset(&state->wdt, '\0', sizeof(state->wdt));
memset(state->spi, '\0', sizeof(state->spi));
......
arch/sandbox/dts/sandbox.dtsi
浏览文件 @ c0912f9b
......@@ -100,6 +100,17 @@
};
pci-controller {
pci@1e,0 {
compatible = "sandbox,pmc";
reg = <0xf000 0 0 0 0>;
sandbox,emul = <&pmc_emul>;
gpe0-dwx-mask = <0xf>;
gpe0-dwx-shift-base = <4>;
gpe0-dw = <6 7 9>;
gpe0-sts = <0x20>;
gpe0-en = <0x30>;
};
pci@1f,0 {
compatible = "pci-generic";
reg = <0xf800 0 0 0 0>;
......@@ -109,6 +120,9 @@
emul {
compatible = "sandbox,pci-emul-parent";
pmc_emul: emul@1e,0 {
compatible = "sandbox,pmc-emul";
};
swap_case_emul: emul@1f,0 {
compatible = "sandbox,swap-case";
};
......
arch/sandbox/dts/test.dts
浏览文件 @ c0912f9b
......@@ -353,6 +353,10 @@
vss-microvolts = <0>;
};
irq {
compatible = "sandbox,irq";
};
lcd {
u-boot,dm-pre-reloc;
compatible = "sandbox,lcd-sdl";
......@@ -471,6 +475,27 @@
0x01000810 0 0 0 0>;
sandbox,emul = <&swap_case_emul0_1>;
};
p2sb-pci@2,0 {
compatible = "sandbox,p2sb";
reg = <0x02001010 0 0 0 0>;
sandbox,emul = <&p2sb_emul>;
adder {
intel,p2sb-port-id = <3>;
compatible = "sandbox,adder";
};
};
pci@1e,0 {
compatible = "sandbox,pmc";
reg = <0xf000 0 0 0 0>;
sandbox,emul = <&pmc_emul1e>;
acpi-base = <0x400>;
gpe0-dwx-mask = <0xf>;
gpe0-dwx-shift-base = <4>;
gpe0-dw = <6 7 9>;
gpe0-sts = <0x20>;
gpe0-en = <0x30>;
};
pci@1f,0 {
compatible = "pci-generic";
/* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
......@@ -491,6 +516,12 @@
swap_case_emul0_1f: emul0@1f,0 {
compatible = "sandbox,swap-case";
};
p2sb_emul: emul@2,0 {
compatible = "sandbox,p2sb-emul";
};
pmc_emul1e: emul@1e,0 {
compatible = "sandbox,pmc-emul";
};
};
pci1: pci-controller1 {
......
arch/sandbox/include/asm/test.h
浏览文件 @ c0912f9b
......@@ -13,6 +13,8 @@
#define SANDBOX_PCI_VENDOR_ID 0x1234
#define SANDBOX_PCI_SWAP_CASE_EMUL_ID 0x5678
#define SANDBOX_PCI_PMC_EMUL_ID 0x5677
#define SANDBOX_PCI_P2SB_EMUL_ID 0x5676
#define SANDBOX_PCI_CLASS_CODE PCI_CLASS_CODE_COMM
#define SANDBOX_PCI_CLASS_SUB_CODE PCI_CLASS_SUB_CODE_COMM_SERIAL
......
arch/x86/Kconfig
浏览文件 @ c0912f9b
......@@ -106,6 +106,7 @@ source "board/google/Kconfig"
source "board/intel/Kconfig"
# platform-specific options below
source "arch/x86/cpu/apollolake/Kconfig"
source "arch/x86/cpu/baytrail/Kconfig"
source "arch/x86/cpu/braswell/Kconfig"
source "arch/x86/cpu/broadwell/Kconfig"
......@@ -217,6 +218,14 @@ config SYS_X86_START16
depends on X86_RESET_VECTOR
default 0xfffff800
config HAVE_X86_FIT
bool
help
Enable inclusion of an Intel Firmware Interface Table (FIT) into the
image. This table is supposed to point to microcode and the like. So
far it is just a fixed table with the minimum set of headers, so that
it is actually present.
config X86_LOAD_FROM_32_BIT
bool "Boot from a 32-bit program"
help
......@@ -326,7 +335,7 @@ config X86_RAMTEST
config FLASH_DESCRIPTOR_FILE
string "Flash descriptor binary filename"
depends on HAVE_INTEL_ME
depends on HAVE_INTEL_ME || FSP_VERSION2
default "descriptor.bin"
help
The filename of the file to use as flash descriptor in the
......@@ -411,6 +420,54 @@ config FSP_ADDR
The default base address of 0xfffc0000 indicates that the binary must
be located at offset 0xc0000 from the beginning of a 1MB flash device.
if FSP_VERSION2
config FSP_FILE_T
string "Firmware Support Package binary filename (Temp RAM)"
default "fsp_t.bin"
help
The filename of the file to use for the temporary-RAM init phase from
the Firmware Support Package binary. Put this in the board directory.
It is used to set up an initial area of RAM which can be used for the
stack and other purposes, while bringing up the main system DRAM.
config FSP_ADDR_T
hex "Firmware Support Package binary location (Temp RAM)"
default 0xffff8000
help
FSP is not Position-Independent Code (PIC) and FSP components have to
be rebased if placed at a location which is different from the
perferred base address specified during the FSP build. Use Intel's
Binary Configuration Tool (BCT) to do the rebase.
config FSP_FILE_M
string "Firmware Support Package binary filename (Memory Init)"
default "fsp_m.bin"
help
The filename of the file to use for the RAM init phase from the
Firmware Support Package binary. Put this in the board directory.
It is used to set up the main system DRAM and runs in SPL, once
temporary RAM (CAR) is working.
config FSP_FILE_S
string "Firmware Support Package binary filename (Silicon Init)"
default "fsp_s.bin"
help
The filename of the file to use for the Silicon init phase from the
Firmware Support Package binary. Put this in the board directory.
It is used to set up the silicon to work correctly and must be
executed after DRAM is running.
config IFWI_INPUT_FILE
string "Filename containing FIT (Firmware Interface Table) with IFWI"
default "fitimage.bin"
help
The IFWI is obtained by running a tool on this file to extract the
IFWI. Put this in the board directory. The IFWI contains U-Boot TPL,
microcode and other internal items.
endif
config FSP_TEMP_RAM_ADDR
hex
depends on FSP_VERSION1
......@@ -532,6 +589,10 @@ config HAVE_REFCODE
broadwell) U-Boot will be missing some critical setup steps.
Various peripherals may fail to work.
config HAVE_MICROCODE
bool
default y if !FSP_VERSION2
config SMP
bool "Enable Symmetric Multiprocessing"
default n
......@@ -595,7 +656,7 @@ config VGA_BIOS_ADDR
config HAVE_VBT
bool "Add a Video BIOS Table (VBT) image"
depends on FSP_VERSION1
depends on HAVE_FSP
help
Select this option if you have a Video BIOS Table (VBT) image that
you would like to add to your ROM. This is normally required if you
......@@ -823,4 +884,30 @@ config HIGH_TABLE_SIZE
Increse it if the default size does not fit the board's needs.
This is most likely due to a large ACPI DSDT table is used.
config INTEL_CAR_CQOS
bool "Support Intel Cache Quality of Service"
help
Cache Quality of Service allows more fine-grained control of cache
usage. As result, it is possible to set up a portion of L2 cache for
CAR and use the remainder for actual caching.
#
# Each bit in QOS mask controls this many bytes. This is calculated as:
# (CACHE_WAYS / CACHE_BITS_PER_MASK) * CACHE_LINE_SIZE * CACHE_SETS
#
config CACHE_QOS_SIZE_PER_BIT
hex
depends on INTEL_CAR_CQOS
default 0x20000 # 128 KB
config X86_OFFSET_U_BOOT
hex "Offset of U-Boot in ROM image"
depends on HAVE_SYS_TEXT_BASE
default SYS_TEXT_BASE
config X86_OFFSET_SPL
hex "Offset of SPL in ROM image"
depends on SPL && X86
default SPL_TEXT_BASE
endmenu
arch/x86/cpu/Makefile
浏览文件 @ c0912f9b
......@@ -41,6 +41,7 @@ extra-y += call32.o
endif
obj-y += intel_common/
obj-$(CONFIG_INTEL_APOLLOLAKE) += apollolake/
obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/
obj-$(CONFIG_INTEL_BRASWELL) += braswell/
obj-$(CONFIG_INTEL_BROADWELL) += broadwell/
......@@ -53,7 +54,8 @@ obj-$(CONFIG_INTEL_QUARK) += quark/
obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/
obj-$(CONFIG_INTEL_TANGIER) += tangier/
obj-$(CONFIG_APIC) += lapic.o ioapic.o
obj-y += irq.o
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += irq.o
obj-$(CONFIG_QFW) += qfw_cpu.o
ifndef CONFIG_$(SPL_)X86_64
obj-$(CONFIG_SMP) += mp_init.o
endif
......
arch/x86/cpu/apollolake/Kconfig 0 → 100644
浏览文件 @ c0912f9b
# SPDX-License-Identifier: GPL-2.0
#
# Copyright 2019 Google LLC
#
config INTEL_APOLLOLAKE
bool
select FSP_VERSION2
select HAVE_FSP
select ARCH_MISC_INIT
select USE_CAR
select INTEL_PMC
select TPL_X86_TSC_TIMER_NATIVE
select SPL_PCH_SUPPORT
select TPL_PCH_SUPPORT
select PCH_SUPPORT
select P2SB
imply ENABLE_MRC_CACHE
imply AHCI_PCI
imply SCSI
imply SCSI_AHCI
imply SPI_FLASH
imply USB
imply USB_EHCI_HCD
imply TPL
imply SPL
imply TPL_X86_16BIT_INIT
imply TPL_OF_PLATDATA
imply ACPI_PMC
imply MMC
imply DM_MMC
imply MMC_PCI
imply MMC_SDHCI
imply CMD_MMC
imply VIDEO_FSP
imply PINCTRL_INTEL
imply PINCTRL_INTEL_APL
imply HAVE_VBT
imply HAVE_X86_FIT
imply INTEL_GPIO
imply SMP
if INTEL_APOLLOLAKE
config DCACHE_RAM_BASE
default 0xfef00000
config DCACHE_RAM_SIZE
default 0xc0000
config DCACHE_RAM_MRC_VAR_SIZE
default 0xb0000
config CPU_SPECIFIC_OPTIONS
def_bool y
select SMM_TSEG
select X86_RAMTEST
config SMM_TSEG_SIZE
hex
default 0x800000
config MMCONF_BASE_ADDRESS
hex
default 0xe0000000
config TPL_SIZE_LIMIT
default 0x7800
config CPU_ADDR_BITS
default 39
config APL_SPI_FLASH_BOOT
bool "Support booting with SPI-flash driver instead memory-mapped SPI"
select TPL_SPI_FLASH_SUPPORT
select TPL_SPI_SUPPORT
help
This enables SPI and SPI flash in TPL. Without the this only
available boot method is to use memory-mapped SPI. Since this is
actually fast and produces a TPL which is 7KB smaller, memory-mapped
SPI is the default.
config APL_BOOT_FROM_FAST_SPI_FLASH
bool "Boot using SPI flash driver"
select APL_SPI_FLASH_BOOT
help
This option is separate from APL_SPI_FLASH_BOOT since it is useful to
be able to compare booting speed with the same build. Enable this to
use the SPI-flash driver to load SPL, U-Boot and FSP-M. For technical
reasons FSP-S is currently always loaded from memory-mapped SPI. See
Apollo Lake's arch_fsp_init_r() for details about that.
config VBT_ADDR
default 0xff3f1000
endif
arch/x86/cpu/apollolake/Makefile 0 → 100644
浏览文件 @ c0912f9b
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2019 Google LLC
obj-$(CONFIG_SPL_BUILD) += cpu_spl.o
obj-$(CONFIG_SPL_BUILD) += spl.o
obj-$(CONFIG_SPL_BUILD) += systemagent.o
obj-y += cpu_common.o
ifndef CONFIG_TPL_BUILD
obj-y += cpu.o
obj-y += punit.o
ifdef CONFIG_SPL_BUILD
obj-y += fsp_m.o
endif
endif
ifndef CONFIG_SPL_BUILD
obj-y += fsp_s.o
endif
obj-y += hostbridge.o
obj-y += itss.o
obj-y += lpc.o
obj-y += p2sb.o
obj-y += pch.o
obj-y += pmc.o
obj-y += uart.o
arch/x86/cpu/apollolake/cpu.c 0 → 100644
浏览文件 @ c0912f9b
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 Google LLC
*/
#include <common.h>
#include <cpu.h>
#include <dm.h>
#include <asm/cpu_common.h>
#include <asm/cpu_x86.h>
static int apl_get_info(struct udevice *dev, struct cpu_info *info)
{
return cpu_intel_get_info(info, INTEL_BCLK_MHZ);
}
static int apl_get_count(struct udevice *dev)
{
return 4;
}
static const struct cpu_ops cpu_x86_apl_ops = {
.get_desc = cpu_x86_get_desc,
.get_info = apl_get_info,
.get_count = apl_get_count,
.get_vendor = cpu_x86_get_vendor,
};
static const struct udevice_id cpu_x86_apl_ids[] = {
{ .compatible = "intel,apl-cpu" },
{ }
};
U_BOOT_DRIVER(cpu_x86_apl_drv) = {
.name = "cpu_x86_apl",
.id = UCLASS_CPU,
.of_match = cpu_x86_apl_ids,
.bind = cpu_x86_bind,
.ops = &cpu_x86_apl_ops,
.flags = DM_FLAG_PRE_RELOC,
};
arch/x86/cpu/apollolake/cpu_common.c 0 → 100644
浏览文件 @ c0912f9b
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 Google LLC
*/
#include <common.h>
#include <asm/cpu_common.h>
#include <asm/msr.h>
void cpu_flush_l1d_to_l2(void)
{
struct msr_t msr;
msr = msr_read(MSR_POWER_MISC);
msr.lo |= FLUSH_DL1_L2;
msr_write(MSR_POWER_MISC, msr);
}
arch/x86/cpu/apollolake/cpu_spl.c 0 → 100644
浏览文件 @ c0912f9b
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 Google LLC
*
* Portions taken from coreboot
*/
#include <common.h>
#include <acpi_s3.h>
#include <dm.h>
#include <ec_commands.h>
#include <log.h>
#include <spi_flash.h>
#include <spl.h>
#include <syscon.h>
#include <asm/cpu.h>
#include <asm/cpu_common.h>
#include <asm/cpu_x86.h>
#include <asm/fast_spi.h>
#include <asm/intel_pinctrl.h>
#include <asm/intel_regs.h>
#include <asm/io.h>
#include <asm/msr.h>
#include <asm/mtrr.h>
#include <asm/pci.h>
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
#include <asm/arch/iomap.h>
#include <asm/arch/lpc.h>
#include <asm/arch/pch.h>
#include <asm/arch/systemagent.h>
#include <asm/arch/uart.h>
#include <asm/fsp2/fsp_api.h>
#include <linux/sizes.h>
#include <power/acpi_pmc.h>
/* Define this here to avoid referencing any drivers for the debug UART 1 */
#define PCH_DEV_P2SB PCI_BDF(0, 0x0d, 0)
static void pch_uart_init(void)
{
/*
* Set up the pinmux so that the UART rx/tx signals are connected
* outside the SoC.
*
* There are about 500 lines of code required to program the GPIO
* configuration for the UARTs. But it boils down to four writes, and
* for the debug UART we want the minimum possible amount of code before
* the UART is running. So just add the magic writes here. See
* apl_hostbridge_early_init_pinctrl() for the full horror.
*/
if (PCI_FUNC(PCH_DEV_UART) == 1) {
writel(0x40000402, 0xd0c50650);
writel(0x3c47, 0xd0c50654);
writel(0x40000400, 0xd0c50658);
writel(0x3c48, 0xd0c5065c);
} else { /* UART2 */
writel(0x40000402, 0xd0c50670);
writel(0x3c4b, 0xd0c50674);
writel(0x40000400, 0xd0c50678);
writel(0x3c4c, 0xd0c5067c);
}
#ifdef CONFIG_DEBUG_UART
apl_uart_init(PCH_DEV_UART, CONFIG_DEBUG_UART_BASE);
#endif
}
static void p2sb_enable_bar(ulong bar)
{
/* Enable PCR Base address in PCH */
pci_x86_write_config(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, bar,
PCI_SIZE_32);
pci_x86_write_config(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
/* Enable P2SB MSE */
pci_x86_write_config(PCH_DEV_P2SB, PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY,
PCI_SIZE_8);
}
/*
* board_debug_uart_init() - Init the debug UART ready for use
*
* This is the minimum init needed to get the UART running. It avoids any
* drivers or complex code, so that the UART is running as soon as possible.
*/
void board_debug_uart_init(void)
{
p2sb_enable_bar(IOMAP_P2SB_BAR);
pch_uart_init();
}
static int fast_spi_cache_bios_region(void)
{
uint map_size, offset;
ulong map_base, base;
int ret;
ret = fast_spi_early_init(PCH_DEV_SPI, IOMAP_SPI_BASE);
if (ret)
return log_msg_ret("early_init", ret);
ret = fast_spi_get_bios_mmap(PCH_DEV_SPI, &map_base, &map_size,
&offset);
if (ret)
return log_msg_ret("get_mmap", ret);
base = SZ_4G - map_size;
mtrr_set_next_var(MTRR_TYPE_WRPROT, base, map_size);
log_debug("BIOS cache base=%lx, size=%x\n", base, (uint)map_size);
return 0;
}
static void enable_pm_timer_emulation(struct udevice *pmc)
{
struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(pmc);
msr_t msr;
/*
* The derived frequency is calculated as follows:
* (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
*
* Back-solve the multiplier so the 3.579545MHz ACPI timer frequency is
* used.
*/
msr.hi = (3579545ULL << 32) / CTC_FREQ;
/* Set PM1 timer IO port and enable */
msr.lo = EMULATE_PM_TMR_EN | (upriv->acpi_base + R_ACPI_PM1_TMR);
debug("PM timer %x %x\n", msr.hi, msr.lo);
msr_write(MSR_EMULATE_PM_TIMER, msr);
}
static void google_chromeec_ioport_range(uint *out_basep, uint *out_sizep)
{
uint base;
uint size;
if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_MEC)) {
base = MEC_EMI_BASE;
size = MEC_EMI_SIZE;
} else {
base = EC_HOST_CMD_REGION0;
size = 2 * EC_HOST_CMD_REGION_SIZE;
/* Make sure MEMMAP region follows host cmd region */
assert(base + size == EC_LPC_ADDR_MEMMAP);
size += EC_MEMMAP_SIZE;
}
*out_basep = base;
*out_sizep = size;
}
static void early_ec_init(void)
{
uint base, size;
/*
* Set up LPC decoding for the Chrome OS EC I/O port ranges:
* - Ports 62/66, 60/64, and 200->208
* - Chrome OS EC communication I/O ports
*/
lpc_enable_fixed_io_ranges(LPC_IOE_EC_62_66 | LPC_IOE_KBC_60_64 |
LPC_IOE_LGE_200);
google_chromeec_ioport_range(&base, &size);
lpc_open_pmio_window(base, size);
}
static int arch_cpu_init_tpl(void)
{
struct udevice *pmc, *sa, *p2sb, *serial, *spi, *lpc;
int ret;
ret = uclass_first_device_err(UCLASS_ACPI_PMC, &pmc);
if (ret)
return log_msg_ret("PMC", ret);
/* Clear global reset promotion bit */
ret = pmc_global_reset_set_enable(pmc, false);
if (ret)
return log_msg_ret("disable global reset", ret);
enable_pm_timer_emulation(pmc);
ret = uclass_first_device_err(UCLASS_P2SB, &p2sb);
if (ret)
return log_msg_ret("p2sb", ret);
ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &sa);
if (ret)
return log_msg_ret("northbridge", ret);
gd->baudrate = CONFIG_BAUDRATE;
ret = uclass_first_device_err(UCLASS_SERIAL, &serial);
if (ret)
return log_msg_ret("serial", ret);
if (CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)) {
ret = uclass_first_device_err(UCLASS_SPI, &spi);
if (ret)
return log_msg_ret("SPI", ret);
} else {
/* Alternative code if we don't have SPI in TPL */
if (IS_ENABLED(CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH))
printf("Warning: Enable APL_SPI_FLASHBOOT to use SPI-flash driver in TPL");
ret = fast_spi_cache_bios_region();
if (ret)
return log_msg_ret("BIOS cache", ret);
}
ret = pmc_disable_tco(pmc);
if (ret)
return log_msg_ret("disable TCO", ret);
ret = pmc_gpe_init(pmc);
if (ret)
return log_msg_ret("pmc_gpe", ret);
ret = uclass_first_device_err(UCLASS_LPC, &lpc);
if (ret)
return log_msg_ret("lpc", ret);
early_ec_init();
return 0;
}
/*
* Enables several BARs and devices which are needed for memory init
* - MCH_BASE_ADDR is needed in order to talk to the memory controller
* - HPET is enabled because FSP wants to store a pointer to global data in the
* HPET comparator register
*/
static int arch_cpu_init_spl(void)
{
struct udevice *pmc, *p2sb;
int ret;
ret = uclass_first_device_err(UCLASS_ACPI_PMC, &pmc);
if (ret)
return log_msg_ret("Could not probe PMC", ret);
ret = uclass_first_device_err(UCLASS_P2SB, &p2sb);
if (ret)
return log_msg_ret("Cannot set up p2sb", ret);
lpc_io_setup_comm_a_b();
/* TODO(sjg@chromium.org): Enable upper RTC bank here */
ret = pmc_init(pmc);
if (ret < 0)
return log_msg_ret("Could not init PMC", ret);
#ifdef CONFIG_HAVE_ACPI_RESUME
ret = pmc_prev_sleep_state(pmc);
if (ret < 0)
return log_msg_ret("Could not get PMC sleep state", ret);
gd->arch.prev_sleep_state = ret;
#endif
return 0;
}
int arch_cpu_init(void)
{
int ret = 0;
if (spl_phase() == PHASE_TPL)
ret = arch_cpu_init_tpl();
else if (spl_phase() == PHASE_SPL)
ret = arch_cpu_init_spl();
if (ret)
printf("%s: Error %d\n", __func__, ret);
return ret;
}
arch/x86/cpu/apollolake/fsp_m.c 0 → 100644
浏览文件 @ c0912f9b
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 Google LLC
* Written by Simon Glass <sjg@chromium.org>
*/
#include <common.h>
#include <dm.h>
#include <asm/arch/iomap.h>
#include <asm/arch/fsp/fsp_configs.h>
#include <asm/arch/fsp/fsp_m_upd.h>
#include <asm/fsp2/fsp_internal.h>
#include <dm/uclass-internal.h>
/*
* ODT settings:
* If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A and HIGH for ODT_B,
* choose ODT_A_B_HIGH_HIGH. If ODT PIN to LP4 DRAM is pulled HIGH for ODT_A
* and LOW for ODT_B, choose ODT_A_B_HIGH_LOW.
*
* Note that the enum values correspond to the interpreted UPD fields
* within Ch[3:0]_OdtConfig parameters.
*/
enum {
ODT_A_B_HIGH_LOW = 0 << 1,
ODT_A_B_HIGH_HIGH = 1 << 1,
N_WR_24 = 1 << 5,
};
/*
* LPDDR4 helper routines for configuring the memory UPD for LPDDR4 operation.
* There are four physical LPDDR4 channels, each 32-bits wide. There are two
* logical channels using two physical channels together to form a 64-bit
* interface to memory for each logical channel.
*/
enum {
LP4_PHYS_CH0A,
LP4_PHYS_CH0B,
LP4_PHYS_CH1A,
LP4_PHYS_CH1B,
LP4_NUM_PHYS_CHANNELS,
};
/*
* The DQs within a physical channel can be bit-swizzled within each byte.
* Within a channel the bytes can be swapped, but the DQs need to be routed
* with the corresponding DQS (strobe).
*/
enum {
LP4_DQS0,
LP4_DQS1,
LP4_DQS2,
LP4_DQS3,
LP4_NUM_BYTE_LANES,
DQ_BITS_PER_DQS = 8,
};
/* Provide bit swizzling per DQS and byte swapping within a channel */
struct lpddr4_chan_swizzle_cfg {
u8 dqs[LP4_NUM_BYTE_LANES][DQ_BITS_PER_DQS];
};
struct lpddr4_swizzle_cfg {
struct lpddr4_chan_swizzle_cfg phys[LP4_NUM_PHYS_CHANNELS];
};
static void setup_sdram(struct fsp_m_config *cfg,
const struct lpddr4_swizzle_cfg *swizzle_cfg)
{
const struct lpddr4_chan_swizzle_cfg *sch;
/* Number of bytes to copy per DQS */
const size_t sz = DQ_BITS_PER_DQS;
int chan;
cfg->memory_down = 1;
cfg->scrambler_support = 1;
cfg->channel_hash_mask = 0x36;
cfg->slice_hash_mask = 9;
cfg->interleaved_mode = 2;
cfg->channels_slices_enable = 0;
cfg->min_ref_rate2x_enable = 0;
cfg->dual_rank_support_enable = 1;
/* LPDDR4 is memory down so no SPD addresses */
cfg->dimm0_spd_address = 0;
cfg->dimm1_spd_address = 0;
for (chan = 0; chan < 4; chan++) {
struct fsp_ram_channel *ch = &cfg->chan[chan];
ch->rank_enable = 1;
ch->device_width = 1;
ch->dram_density = 2;
ch->option = 3;
ch->odt_config = ODT_A_B_HIGH_HIGH;
}
/*
* CH0_DQB byte lanes in the bit swizzle configuration field are
* not 1:1. The mapping within the swizzling field is:
* indices [0:7] - byte lane 1 (DQS1) DQ[8:15]
* indices [8:15] - byte lane 0 (DQS0) DQ[0:7]
* indices [16:23] - byte lane 3 (DQS3) DQ[24:31]
* indices [24:31] - byte lane 2 (DQS2) DQ[16:23]
*/
sch = &swizzle_cfg->phys[LP4_PHYS_CH0B];
memcpy(&cfg->ch_bit_swizzling[0][0], &sch->dqs[LP4_DQS1], sz);
memcpy(&cfg->ch_bit_swizzling[0][8], &sch->dqs[LP4_DQS0], sz);
memcpy(&cfg->ch_bit_swizzling[0][16], &sch->dqs[LP4_DQS3], sz);
memcpy(&cfg->ch_bit_swizzling[0][24], &sch->dqs[LP4_DQS2], sz);
/*
* CH0_DQA byte lanes in the bit swizzle configuration field are 1:1.
*/
sch = &swizzle_cfg->phys[LP4_PHYS_CH0A];
memcpy(&cfg->ch_bit_swizzling[1][0], &sch->dqs[LP4_DQS0], sz);
memcpy(&cfg->ch_bit_swizzling[1][8], &sch->dqs[LP4_DQS1], sz);
memcpy(&cfg->ch_bit_swizzling[1][16], &sch->dqs[LP4_DQS2], sz);
memcpy(&cfg->ch_bit_swizzling[1][24], &sch->dqs[LP4_DQS3], sz);
sch = &swizzle_cfg->phys[LP4_PHYS_CH1B];
memcpy(&cfg->ch_bit_swizzling[2][0], &sch->dqs[LP4_DQS1], sz);
memcpy(&cfg->ch_bit_swizzling[2][8], &sch->dqs[LP4_DQS0], sz);
memcpy(&cfg->ch_bit_swizzling[2][16], &sch->dqs[LP4_DQS3], sz);
memcpy(&cfg->ch_bit_swizzling[2][24], &sch->dqs[LP4_DQS2], sz);
/*
* CH0_DQA byte lanes in the bit swizzle configuration field are 1:1.
*/
sch = &swizzle_cfg->phys[LP4_PHYS_CH1A];
memcpy(&cfg->ch_bit_swizzling[3][0], &sch->dqs[LP4_DQS0], sz);
memcpy(&cfg->ch_bit_swizzling[3][8], &sch->dqs[LP4_DQS1], sz);
memcpy(&cfg->ch_bit_swizzling[3][16], &sch->dqs[LP4_DQS2], sz);
memcpy(&cfg->ch_bit_swizzling[3][24], &sch->dqs[LP4_DQS3], sz);
}
int fspm_update_config(struct udevice *dev, struct fspm_upd *upd)
{
struct fsp_m_config *cfg = &upd->config;
struct fspm_arch_upd *arch = &upd->arch;
arch->nvs_buffer_ptr = NULL;
prepare_mrc_cache(upd);
arch->stack_base = (void *)0xfef96000;
arch->boot_loader_tolum_size = 0;
arch->boot_mode = FSP_BOOT_WITH_FULL_CONFIGURATION;
cfg->serial_debug_port_type = 2;
cfg->serial_debug_port_device = 2;
cfg->serial_debug_port_stride_size = 2;
cfg->serial_debug_port_address = 0;
cfg->package = 1;
/* Don't enforce a memory size limit */
cfg->memory_size_limit = 0;
cfg->low_memory_max_value = 2048; /* 2 GB */
/* No restrictions on memory above 4GiB */
cfg->high_memory_max_value = 0;
/* Always default to attempt to use saved training data */
cfg->disable_fast_boot = 0;
const u8 *swizzle_data;
swizzle_data = dev_read_u8_array_ptr(dev, "lpddr4-swizzle",
LP4_NUM_BYTE_LANES *
DQ_BITS_PER_DQS *
LP4_NUM_PHYS_CHANNELS);
if (!swizzle_data)
return log_msg_ret("Cannot read swizzel data", -EINVAL);
setup_sdram(cfg, (struct lpddr4_swizzle_cfg *)swizzle_data);
cfg->pre_mem_gpio_table_ptr = 0;
cfg->profile = 0xb;
cfg->msg_level_mask = 0;
/* other */
cfg->skip_cse_rbp = 1;
cfg->periodic_retraining_disable = 0;
cfg->enable_s3_heci2 = 0;
return 0;
}
/*
* The FSP-M binary appears to break the SPI controller. It can be fixed by
* writing the BAR again, so do that here
*/
int fspm_done(struct udevice *dev)
{
struct udevice *spi;
int ret;
/* Don't probe the device, since that reads the BAR */
ret = uclass_find_first_device(UCLASS_SPI, &spi);
if (ret)
return log_msg_ret("SPI", ret);
if (!spi)
return log_msg_ret("no SPI", -ENODEV);
dm_pci_write_config32(spi, PCI_BASE_ADDRESS_0,
IOMAP_SPI_BASE | PCI_BASE_ADDRESS_SPACE_MEMORY);
return 0;
}
arch/x86/cpu/apollolake/fsp_s.c 0 → 100644
浏览文件 @ c0912f9b
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 Google LLC
* Written by Simon Glass <sjg@chromium.org>
*/
#include <common.h>
#include <acpi_s3.h>
#include <binman.h>
#include <dm.h>
#include <irq.h>
#include <asm/intel_pinctrl.h>
#include <asm/io.h>
#include <asm/intel_regs.h>
#include <asm/msr.h>
#include <asm/msr-index.h>
#include <asm/pci.h>
#include <asm/arch/cpu.h>
#include <asm/arch/systemagent.h>
#include <asm/arch/fsp/fsp_configs.h>
#include <asm/arch/fsp/fsp_s_upd.h>
#define PCH_P2SB_E0 0xe0
#define HIDE_BIT BIT(0)
#define INTEL_GSPI_MAX 3
#define INTEL_I2C_DEV_MAX 8
#define MAX_USB2_PORTS 8
enum {
CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */
CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */
};
enum i2c_speed {
I2C_SPEED_STANDARD = 100000,
I2C_SPEED_FAST = 400000,
I2C_SPEED_FAST_PLUS = 1000000,
I2C_SPEED_HIGH = 3400000,
I2C_SPEED_FAST_ULTRA = 5000000,
};
/*
* Timing values are in units of clock period, with the clock speed
* provided by the SOC
*
* TODO(sjg@chromium.org): Connect this up to the I2C driver
*/
struct dw_i2c_speed_config {
enum i2c_speed speed;
/* SCL high and low period count */
u16 scl_lcnt;
u16 scl_hcnt;
/*
* SDA hold time should be 300ns in standard and fast modes
* and long enough for deterministic logic level change in
* fast-plus and high speed modes.
*
* [15:0] SDA TX Hold Time
* [23:16] SDA RX Hold Time
*/
u32 sda_hold;
};
/* Serial IRQ control. SERIRQ_QUIET is the default (0) */
enum serirq_mode {
SERIRQ_QUIET,
SERIRQ_CONTINUOUS,
SERIRQ_OFF,
};
/*
* This I2C controller has support for 3 independent speed configs but can
* support both FAST_PLUS and HIGH speeds through the same set of speed
* config registers. These are treated separately so the speed config values
* can be provided via ACPI to the OS.
*/
#define DW_I2C_SPEED_CONFIG_COUNT 4
struct dw_i2c_bus_config {
/* Bus should be enabled in TPL with temporary base */
int early_init;
/* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */
enum i2c_speed speed;
/*
* If rise_time_ns is non-zero the calculations for lcnt and hcnt
* registers take into account the times of the bus. However, if
* there is a match in speed_config those register values take
* precedence
*/
int rise_time_ns;
int fall_time_ns;
int data_hold_time_ns;
/* Specific bus speed configuration */
struct dw_i2c_speed_config speed_config[DW_I2C_SPEED_CONFIG_COUNT];
};
struct gspi_cfg {
/* Bus speed in MHz */
u32 speed_mhz;
/* Bus should be enabled prior to ramstage with temporary base */
u8 early_init;
};
/*
* This structure will hold data required by common blocks.
* These are soc specific configurations which will be filled by soc.
* We'll fill this structure once during init and use the data in common block.
*/
struct soc_intel_common_config {
int chipset_lockdown;
struct gspi_cfg gspi[INTEL_GSPI_MAX];
struct dw_i2c_bus_config i2c[INTEL_I2C_DEV_MAX];
};
enum pnp_settings {
PNP_PERF,
PNP_POWER,
PNP_PERF_POWER,
};
struct usb2_eye_per_port {
u8 per_port_tx_pe_half;
u8 per_port_pe_txi_set;
u8 per_port_txi_set;
u8 hs_skew_sel;
u8 usb_tx_emphasis_en;
u8 per_port_rxi_set;
u8 hs_npre_drv_sel;
u8 override_en;
};
struct apl_config {
/* Common structure containing soc config data required by common code*/
struct soc_intel_common_config common_soc_config;
/*
* Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
* four CLKREQ inputs, but six root ports. Root ports without an
* associated CLKREQ signal must be marked with "CLKREQ_DISABLED"
*/
u8 pcie_rp_clkreq_pin[MAX_PCIE_PORTS];
/* Enable/disable hot-plug for root ports (0 = disable, 1 = enable) */
u8 pcie_rp_hotplug_enable[MAX_PCIE_PORTS];
/* De-emphasis enable configuration for each PCIe root port */
u8 pcie_rp_deemphasis_enable[MAX_PCIE_PORTS];
/*
* [14:8] DDR mode Number of dealy elements.Each = 125pSec.
* [6:0] SDR mode Number of dealy elements.Each = 125pSec.
*/
u32 emmc_tx_cmd_cntl;
/*
* [14:8] HS400 mode Number of dealy elements.Each = 125pSec.
* [6:0] SDR104/HS200 mode Number of dealy elements.Each = 125pSec.
*/
u32 emmc_tx_data_cntl1;
/*
* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
* [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
* [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
* [6:0] SDR12/Compatibility mode Number of dealy elements.
* Each = 125pSec.
*/
u32 emmc_tx_data_cntl2;
/*
* [30:24] SDR50 mode Number of dealy elements.Each = 125pSec.
* [22:16] DDR50 mode Number of dealy elements.Each = 125pSec.
* [14:8] SDR25/HS50 mode Number of dealy elements.Each = 125pSec.
* [6:0] SDR12/Compatibility mode Number of dealy elements.
* Each = 125pSec.
*/
u32 emmc_rx_cmd_data_cntl1;
/*
* [14:8] HS400 mode 1 Number of dealy elements.Each = 125pSec.
* [6:0] HS400 mode 2 Number of dealy elements.Each = 125pSec.
*/
u32 emmc_rx_strobe_cntl;
/*
* [13:8] Auto Tuning mode Number of dealy elements.Each = 125pSec.
* [6:0] SDR104/HS200 Number of dealy elements.Each = 125pSec.
*/
u32 emmc_rx_cmd_data_cntl2;
/* Select the eMMC max speed allowed */
u32 emmc_host_max_speed;
/* Specifies on which IRQ the SCI will internally appear */
u32 sci_irq;
/* Configure serial IRQ (SERIRQ) line */
enum serirq_mode serirq_mode;
/* Configure LPSS S0ix Enable */
bool lpss_s0ix_enable;
/* Enable DPTF support */
bool dptf_enable;
/* TCC activation offset value in degrees Celsius */
int tcc_offset;
/*
* Configure Audio clk gate and power gate
* IOSF-SB port ID 92 offset 0x530 [5] and [3]
*/
bool hdaudio_clk_gate_enable;
bool hdaudio_pwr_gate_enable;
bool hdaudio_bios_config_lockdown;
/* SLP S3 minimum assertion width */
int slp_s3_assertion_width_usecs;
/* GPIO pin for PERST_0 */
u32 prt0_gpio;
/* USB2 eye diagram settings per port */
struct usb2_eye_per_port usb2eye[MAX_USB2_PORTS];
/* GPIO SD card detect pin */
unsigned int sdcard_cd_gpio;
/*
* PRMRR size setting with three options
* 0x02000000 - 32MiB
* 0x04000000 - 64MiB
* 0x08000000 - 128MiB
*/
u32 PrmrrSize;
/*
* Enable SGX feature.
* Enabling SGX feature is 2 step process,
* (1) set sgx_enable = 1
* (2) set PrmrrSize to supported size
*/
bool sgx_enable;
/*
* Select PNP Settings.
* (0) Performance,
* (1) Power
* (2) Power & Performance
*/
enum pnp_settings pnp_settings;
/*
* PMIC PCH_PWROK delay configuration - IPC Configuration
* Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address
* (31:24) + Register_Offset (23:16) + OR Value (15:8) + AND Value (7:0)
*/
u32 pmic_pmc_ipc_ctrl;
/*
* Options to disable XHCI Link Compliance Mode. Default is FALSE to not
* disable Compliance Mode. Set TRUE to disable Compliance Mode.
* 0:FALSE(Default), 1:True.
*/
bool disable_compliance_mode;
/*
* Options to change USB3 ModPhy setting for the Integrated Filter (IF)
* value. Default is 0 to not changing default IF value (0x12). Set
* value with the range from 0x01 to 0xff to change IF value.
*/
u32 mod_phy_if_value;
/*
* Options to bump USB3 LDO voltage. Default is FALSE to not increasing
* LDO voltage. Set TRUE to increase LDO voltage with 40mV.
* 0:FALSE (default), 1:True.
*/
bool mod_phy_voltage_bump;
/*
* Options to adjust PMIC Vdd2 voltage. Default is 0 to not adjusting
* the PMIC Vdd2 default voltage 1.20v. Upd for changing Vdd2 Voltage
* configuration: I2C_Slave_Address (31:23) + Register_Offset (23:16)
* + OR Value (15:8) + AND Value (7:0) through BUCK5_VID[3:2]:
* 00=1.10v, 01=1.15v, 10=1.24v, 11=1.20v (default).
*/
u32 pmic_vdd2_voltage;
/* Option to enable VTD feature */
bool enable_vtd;
};
static int get_config(struct udevice *dev, struct apl_config *apl)
{
const u8 *ptr;
ofnode node;
u32 emmc[4];
int ret;
memset(apl, '\0', sizeof(*apl));
node = dev_read_subnode(dev, "fsp-s");
if (!ofnode_valid(node))
return log_msg_ret("fsp-s settings", -ENOENT);
ptr = ofnode_read_u8_array_ptr(node, "pcie-rp-clkreq-pin",
MAX_PCIE_PORTS);
if (!ptr)
return log_msg_ret("pcie-rp-clkreq-pin", -EINVAL);
memcpy(apl->pcie_rp_clkreq_pin, ptr, MAX_PCIE_PORTS);
ret = ofnode_read_u32(node, "prt0-gpio", &apl->prt0_gpio);
if (ret)
return log_msg_ret("prt0-gpio", ret);
ret = ofnode_read_u32(node, "sdcard-cd-gpio", &apl->sdcard_cd_gpio);
if (ret)
return log_msg_ret("sdcard-cd-gpio", ret);
ret = ofnode_read_u32_array(node, "emmc", emmc, ARRAY_SIZE(emmc));
if (ret)
return log_msg_ret("emmc", ret);
apl->emmc_tx_data_cntl1 = emmc[0];
apl->emmc_tx_data_cntl2 = emmc[1];
apl->emmc_rx_cmd_data_cntl1 = emmc[2];
apl->emmc_rx_cmd_data_cntl2 = emmc[3];
apl->dptf_enable = ofnode_read_bool(node, "dptf-enable");
apl->hdaudio_clk_gate_enable = ofnode_read_bool(node,
"hdaudio-clk-gate-enable");
apl->hdaudio_pwr_gate_enable = ofnode_read_bool(node,
"hdaudio-pwr-gate-enable");
apl->hdaudio_bios_config_lockdown = ofnode_read_bool(node,
"hdaudio-bios-config-lockdown");
apl->lpss_s0ix_enable = ofnode_read_bool(node, "lpss-s0ix-enable");
/* Santa */
apl->usb2eye[1].per_port_pe_txi_set = 7;
apl->usb2eye[1].per_port_txi_set = 2;
return 0;
}
static void apl_fsp_silicon_init_params_cb(struct apl_config *apl,
struct fsp_s_config *cfg)
{
u8 port;
for (port = 0; port < MAX_USB2_PORTS; port++) {
if (apl->usb2eye[port].per_port_tx_pe_half)
cfg->port_usb20_per_port_tx_pe_half[port] =
apl->usb2eye[port].per_port_tx_pe_half;
if (apl->usb2eye[port].per_port_pe_txi_set)
cfg->port_usb20_per_port_pe_txi_set[port] =
apl->usb2eye[port].per_port_pe_txi_set;
if (apl->usb2eye[port].per_port_txi_set)
cfg->port_usb20_per_port_txi_set[port] =
apl->usb2eye[port].per_port_txi_set;
if (apl->usb2eye[port].hs_skew_sel)
cfg->port_usb20_hs_skew_sel[port] =
apl->usb2eye[port].hs_skew_sel;
if (apl->usb2eye[port].usb_tx_emphasis_en)
cfg->port_usb20_i_usb_tx_emphasis_en[port] =
apl->usb2eye[port].usb_tx_emphasis_en;
if (apl->usb2eye[port].per_port_rxi_set)
cfg->port_usb20_per_port_rxi_set[port] =
apl->usb2eye[port].per_port_rxi_set;
if (apl->usb2eye[port].hs_npre_drv_sel)
cfg->port_usb20_hs_npre_drv_sel[port] =
apl->usb2eye[port].hs_npre_drv_sel;
}
}
int fsps_update_config(struct udevice *dev, ulong rom_offset,
struct fsps_upd *upd)
{
struct fsp_s_config *cfg = &upd->config;
struct apl_config *apl;
struct binman_entry vbt;
void *buf;
int ret;
ret = binman_entry_find("intel-vbt", &vbt);
if (ret)
return log_msg_ret("Cannot find VBT", ret);
vbt.image_pos += rom_offset;
buf = malloc(vbt.size);
if (!buf)
return log_msg_ret("Alloc VBT", -ENOMEM);
/*
* Load VBT before devicetree-specific config. This only supports
* memory-mapped SPI at present.
*/
bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
memcpy(buf, (void *)vbt.image_pos, vbt.size);
bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
if (*(u32 *)buf != VBT_SIGNATURE)
return log_msg_ret("VBT signature", -EINVAL);
cfg->graphics_config_ptr = (ulong)buf;
apl = malloc(sizeof(*apl));
if (!apl)
return log_msg_ret("config", -ENOMEM);
get_config(dev, apl);
cfg->ish_enable = 0;
cfg->enable_sata = 0;
cfg->pcie_root_port_en[2] = 0;
cfg->pcie_rp_hot_plug[2] = 0;
cfg->pcie_root_port_en[3] = 0;
cfg->pcie_rp_hot_plug[3] = 0;
cfg->pcie_root_port_en[4] = 0;
cfg->pcie_rp_hot_plug[4] = 0;
cfg->pcie_root_port_en[5] = 0;
cfg->pcie_rp_hot_plug[5] = 0;
cfg->pcie_root_port_en[1] = 0;
cfg->pcie_rp_hot_plug[1] = 0;
cfg->usb_otg = 0;
cfg->i2c6_enable = 0;
cfg->i2c7_enable = 0;
cfg->hsuart3_enable = 0;
cfg->spi1_enable = 0;
cfg->spi2_enable = 0;
cfg->sdio_enabled = 0;
memcpy(cfg->pcie_rp_clk_req_number, apl->pcie_rp_clkreq_pin,
sizeof(cfg->pcie_rp_clk_req_number));
memcpy(cfg->pcie_rp_hot_plug, apl->pcie_rp_hotplug_enable,
sizeof(cfg->pcie_rp_hot_plug));
switch (apl->serirq_mode) {
case SERIRQ_QUIET:
cfg->sirq_enable = 1;
cfg->sirq_mode = 0;
break;
case SERIRQ_CONTINUOUS:
cfg->sirq_enable = 1;
cfg->sirq_mode = 1;
break;
case SERIRQ_OFF:
default:
cfg->sirq_enable = 0;
break;
}
if (apl->emmc_tx_cmd_cntl)
cfg->emmc_tx_cmd_cntl = apl->emmc_tx_cmd_cntl;
if (apl->emmc_tx_data_cntl1)
cfg->emmc_tx_data_cntl1 = apl->emmc_tx_data_cntl1;
if (apl->emmc_tx_data_cntl2)
cfg->emmc_tx_data_cntl2 = apl->emmc_tx_data_cntl2;
if (apl->emmc_rx_cmd_data_cntl1)
cfg->emmc_rx_cmd_data_cntl1 = apl->emmc_rx_cmd_data_cntl1;
if (apl->emmc_rx_strobe_cntl)
cfg->emmc_rx_strobe_cntl = apl->emmc_rx_strobe_cntl;
if (apl->emmc_rx_cmd_data_cntl2)
cfg->emmc_rx_cmd_data_cntl2 = apl->emmc_rx_cmd_data_cntl2;
if (apl->emmc_host_max_speed)
cfg->e_mmc_host_max_speed = apl->emmc_host_max_speed;
cfg->lpss_s0ix_enable = apl->lpss_s0ix_enable;
cfg->skip_mp_init = true;
/* Disable setting of EISS bit in FSP */
cfg->spi_eiss = 0;
/* Disable FSP from locking access to the RTC NVRAM */
cfg->rtc_lock = 0;
/* Enable Audio clk gate and power gate */
cfg->hd_audio_clk_gate = apl->hdaudio_clk_gate_enable;
cfg->hd_audio_pwr_gate = apl->hdaudio_pwr_gate_enable;
/* Bios config lockdown Audio clk and power gate */
cfg->bios_cfg_lock_down = apl->hdaudio_bios_config_lockdown;
apl_fsp_silicon_init_params_cb(apl, cfg);
cfg->usb_otg = true;
cfg->vtd_enable = apl->enable_vtd;
return 0;
}
static void p2sb_set_hide_bit(pci_dev_t dev, int hide)
{
pci_x86_clrset_config(dev, PCH_P2SB_E0 + 1, HIDE_BIT,
hide ? HIDE_BIT : 0, PCI_SIZE_8);
}
/* Configure package power limits */
static int set_power_limits(struct udevice *dev)
{
msr_t rapl_msr_reg, limit;
u32 power_unit;
u32 tdp, min_power, max_power;
u32 pl2_val;
u32 override_tdp[2];
int ret;
/* Get units */
rapl_msr_reg = msr_read(MSR_PKG_POWER_SKU_UNIT);
power_unit = 1 << (rapl_msr_reg.lo & 0xf);
/* Get power defaults for this SKU */
rapl_msr_reg = msr_read(MSR_PKG_POWER_SKU);
tdp = rapl_msr_reg.lo & PKG_POWER_LIMIT_MASK;
pl2_val = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK;
min_power = (rapl_msr_reg.lo >> 16) & PKG_POWER_LIMIT_MASK;
max_power = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK;
if (min_power > 0 && tdp < min_power)
tdp = min_power;
if (max_power > 0 && tdp > max_power)
tdp = max_power;
ret = dev_read_u32_array(dev, "tdp-pl-override-mw", override_tdp,
ARRAY_SIZE(override_tdp));
if (ret)
return log_msg_ret("tdp-pl-override-mw", ret);
/* Set PL1 override value */
if (override_tdp[0])
tdp = override_tdp[0] * power_unit / 1000;
/* Set PL2 override value */
if (override_tdp[1])
pl2_val = override_tdp[1] * power_unit / 1000;
/* Set long term power limit to TDP */
limit.lo = tdp & PKG_POWER_LIMIT_MASK;
/* Set PL1 Pkg Power clamp bit */
limit.lo |= PKG_POWER_LIMIT_CLAMP;
limit.lo |= PKG_POWER_LIMIT_EN;
limit.lo |= (MB_POWER_LIMIT1_TIME_DEFAULT &
PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT;
/* Set short term power limit PL2 */
limit.hi = pl2_val & PKG_POWER_LIMIT_MASK;
limit.hi |= PKG_POWER_LIMIT_EN;
/* Program package power limits in RAPL MSR */
msr_write(MSR_PKG_POWER_LIMIT, limit);
log_info("RAPL PL1 %d.%dW\n", tdp / power_unit,
100 * (tdp % power_unit) / power_unit);
log_info("RAPL PL2 %d.%dW\n", pl2_val / power_unit,
100 * (pl2_val % power_unit) / power_unit);
/*
* Sett RAPL MMIO register for Power limits. RAPL driver is using MSR
* instead of MMIO, so disable LIMIT_EN bit for MMIO
*/
writel(limit.lo & ~PKG_POWER_LIMIT_EN, MCHBAR_REG(MCHBAR_RAPL_PPL));
writel(limit.hi & ~PKG_POWER_LIMIT_EN, MCHBAR_REG(MCHBAR_RAPL_PPL + 4));
return 0;
}
int p2sb_unhide(void)
{
pci_dev_t dev = PCI_BDF(0, 0xd, 0);
ulong val;
p2sb_set_hide_bit(dev, 0);
pci_x86_read_config(dev, PCI_VENDOR_ID, &val, PCI_SIZE_16);
if (val != PCI_VENDOR_ID_INTEL)
return log_msg_ret("p2sb unhide", -EIO);
return 0;
}
/* Overwrites the SCI IRQ if another IRQ number is given by device tree */
static void set_sci_irq(void)
{
/* Skip this for now */
}
int arch_fsps_preinit(void)
{
struct udevice *itss;
int ret;
ret = uclass_first_device_err(UCLASS_IRQ, &itss);
if (ret)
return log_msg_ret("no itss", ret);
/*
* Snapshot the current GPIO IRQ polarities. FSP is setting a default
* policy that doesn't honour boards' requirements
*/
irq_snapshot_polarities(itss);
/*
* Clear the GPI interrupt status and enable registers. These
* registers do not get reset to default state when booting from S5.
*/
ret = pinctrl_gpi_clear_int_cfg();
if (ret)
return log_msg_ret("gpi_clear", ret);
return 0;
}
int arch_fsp_init_r(void)
{
#ifdef CONFIG_HAVE_ACPI_RESUME
bool s3wake = gd->arch.prev_sleep_state == ACPI_S3;
#else
bool s3wake = false;
#endif
struct udevice *dev, *itss;
int ret;
/*
* This must be called before any devices are probed. Put any probing
* into arch_fsps_preinit() above.
*
* We don't use CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH here since it will
* force PCI to be probed.
*/
ret = fsp_silicon_init(s3wake, false);
if (ret)
return ret;
ret = uclass_first_device_err(UCLASS_IRQ, &itss);
if (ret)
return log_msg_ret("no itss", ret);
/* Restore GPIO IRQ polarities back to previous settings */
irq_restore_polarities(itss);
/* soc_init() */
ret = p2sb_unhide();
if (ret)
return log_msg_ret("unhide p2sb", ret);
/* Set RAPL MSR for Package power limits*/
ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev);
if (ret)
return log_msg_ret("Cannot get northbridge", ret);
set_power_limits(dev);
/*
* FSP-S routes SCI to IRQ 9. With the help of this function you can
* select another IRQ for SCI.
*/
set_sci_irq();
return 0;
}
arch/x86/cpu/apollolake/hostbridge.c 0 → 100644
浏览文件 @ c0912f9b
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 Google LLC
*/
#include <common.h>
#include <dm.h>
#include <dt-structs.h>
#include <spl.h>
#include <asm/intel_pinctrl.h>
#include <asm/intel_regs.h>
#include <asm/pci.h>
#include <asm/arch/systemagent.h>
/**
* struct apl_hostbridge_platdata - platform data for hostbridge
*
* @dtplat: Platform data for of-platdata
* @early_pads: Early pad data to set up, each (pad, cfg0, cfg1)
* @early_pads_count: Number of pads to process
* @pciex_region_size: BAR length in bytes
* @bdf: Bus/device/function of hostbridge
*/
struct apl_hostbridge_platdata {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_intel_apl_hostbridge dtplat;
#endif
u32 *early_pads;
int early_pads_count;
uint pciex_region_size;
pci_dev_t bdf;
};
enum {
PCIEXBAR = 0x60,
PCIEXBAR_LENGTH_256MB = 0,
PCIEXBAR_LENGTH_128MB,
PCIEXBAR_LENGTH_64MB,
PCIEXBAR_PCIEXBAREN = 1 << 0,
TSEG = 0xb8, /* TSEG base */
};
static int apl_hostbridge_early_init_pinctrl(struct udevice *dev)
{
struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
struct udevice *pinctrl;
int ret;
ret = uclass_first_device_err(UCLASS_PINCTRL, &pinctrl);
if (ret)
return log_msg_ret("no hostbridge pinctrl", ret);
return pinctrl_config_pads(pinctrl, plat->early_pads,
plat->early_pads_count);
}
static int apl_hostbridge_early_init(struct udevice *dev)
{
struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
u32 region_size;
ulong base;
u32 reg;
int ret;
/* Set up the MCHBAR */
pci_x86_read_config(plat->bdf, MCHBAR, &base, PCI_SIZE_32);
base = MCH_BASE_ADDRESS;
pci_x86_write_config(plat->bdf, MCHBAR, base | 1, PCI_SIZE_32);
/*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB
*/
pci_x86_write_config(plat->bdf, PCIEXBAR + 4, 0, PCI_SIZE_32);
switch (plat->pciex_region_size >> 20) {
default:
case 256:
region_size = PCIEXBAR_LENGTH_256MB;
break;
case 128:
region_size = PCIEXBAR_LENGTH_128MB;
break;
case 64:
region_size = PCIEXBAR_LENGTH_64MB;
break;
}
reg = CONFIG_MMCONF_BASE_ADDRESS | (region_size << 1)
| PCIEXBAR_PCIEXBAREN;
pci_x86_write_config(plat->bdf, PCIEXBAR, reg, PCI_SIZE_32);
/*
* TSEG defines the base of SMM range. BIOS determines the base
* of TSEG memory which must be at or below Graphics base of GTT
* Stolen memory, hence its better to clear TSEG register early
* to avoid power on default non-zero value (if any).
*/
pci_x86_write_config(plat->bdf, TSEG, 0, PCI_SIZE_32);
ret = apl_hostbridge_early_init_pinctrl(dev);
if (ret)
return log_msg_ret("pinctrl", ret);
return 0;
}
static int apl_hostbridge_ofdata_to_platdata(struct udevice *dev)
{
struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
struct udevice *pinctrl;
int ret;
/*
* The host bridge holds the early pad data needed to get through TPL.
* This is a small amount of data, enough to fit in TPL, so we keep it
* separate from the full pad data, stored in the fsp-s subnode. That
* subnode is not present in TPL, to save space.
*/
ret = uclass_first_device_err(UCLASS_PINCTRL, &pinctrl);
if (ret)
return log_msg_ret("no hostbridge PINCTRL", ret);
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
int root;
/* Get length of PCI Express Region */
plat->pciex_region_size = dev_read_u32_default(dev, "pciex-region-size",
256 << 20);
root = pci_get_devfn(dev);
if (root < 0)
return log_msg_ret("Cannot get host-bridge PCI address", root);
plat->bdf = root;
ret = pinctrl_read_pads(pinctrl, dev_ofnode(dev), "early-pads",
&plat->early_pads, &plat->early_pads_count);
if (ret)
return log_msg_ret("early-pads", ret);
#else
struct dtd_intel_apl_hostbridge *dtplat = &plat->dtplat;
int size;
plat->pciex_region_size = dtplat->pciex_region_size;
plat->bdf = pci_ofplat_get_devfn(dtplat->reg[0]);
/* Assume that if everything is 0, it is empty */
plat->early_pads = dtplat->early_pads;
size = ARRAY_SIZE(dtplat->early_pads);
plat->early_pads_count = pinctrl_count_pads(pinctrl, plat->early_pads,
size);
#endif
return 0;
}
static int apl_hostbridge_probe(struct udevice *dev)
{
if (spl_phase() == PHASE_TPL)
return apl_hostbridge_early_init(dev);
return 0;
}
static const struct udevice_id apl_hostbridge_ids[] = {
{ .compatible = "intel,apl-hostbridge" },
{ }
};
U_BOOT_DRIVER(apl_hostbridge_drv) = {
.name = "intel_apl_hostbridge",
.id = UCLASS_NORTHBRIDGE,
.of_match = apl_hostbridge_ids,
.ofdata_to_platdata = apl_hostbridge_ofdata_to_platdata,
.probe = apl_hostbridge_probe,
.platdata_auto_alloc_size = sizeof(struct apl_hostbridge_platdata),
};
arch/x86/cpu/apollolake/itss.c 0 → 100644
浏览文件 @ c0912f9b
// SPDX-License-Identifier: GPL-2.0
/*
* Something to do with Interrupts, but I don't know what ITSS stands for
*
* Copyright (C) 2017 Intel Corporation.
* Copyright (C) 2017 Siemens AG
* Copyright 2019 Google LLC
*
* Taken from coreboot itss.c
*/
#include <common.h>
#include <dm.h>
#include <dt-structs.h>
#include <irq.h>
#include <p2sb.h>
#include <spl.h>
#include <asm/arch/itss.h>
struct apl_itss_platdata {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
/* Put this first since driver model will copy the data here */
struct dtd_intel_apl_itss dtplat;
#endif
};
/* struct pmc_route - Routing for PMC to GPIO */
struct pmc_route {
u32 pmc;
u32 gpio;
};
struct apl_itss_priv {
struct pmc_route *route;
uint route_count;
u32 irq_snapshot[NUM_IPC_REGS];
};
static int apl_set_polarity(struct udevice *dev, uint irq, bool active_low)
{
u32 mask;
uint reg;
if (irq > ITSS_MAX_IRQ)
return -EINVAL;
reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * (irq / IRQS_PER_IPC);
mask = 1 << (irq % IRQS_PER_IPC);
pcr_clrsetbits32(dev, reg, mask, active_low ? mask : 0);
return 0;
}
#ifndef CONFIG_TPL_BUILD
static int apl_snapshot_polarities(struct udevice *dev)
{
struct apl_itss_priv *priv = dev_get_priv(dev);
const int start = GPIO_IRQ_START;
const int end = GPIO_IRQ_END;
int reg_start;
int reg_end;
int i;
reg_start = start / IRQS_PER_IPC;
reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC;
for (i = reg_start; i < reg_end; i++) {
uint reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
priv->irq_snapshot[i] = pcr_read32(dev, reg);
}
return 0;
}
static void show_polarities(struct udevice *dev, const char *msg)
{
int i;
log_info("ITSS IRQ Polarities %s:\n", msg);
for (i = 0; i < NUM_IPC_REGS; i++) {
uint reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
log_info("IPC%d: 0x%08x\n", i, pcr_read32(dev, reg));
}
}
static int apl_restore_polarities(struct udevice *dev)
{
struct apl_itss_priv *priv = dev_get_priv(dev);
const int start = GPIO_IRQ_START;
const int end = GPIO_IRQ_END;
int reg_start;
int reg_end;
int i;
show_polarities(dev, "Before");
reg_start = start / IRQS_PER_IPC;
reg_end = (end + IRQS_PER_IPC - 1) / IRQS_PER_IPC;
for (i = reg_start; i < reg_end; i++) {
u32 mask;
u16 reg;
int irq_start;
int irq_end;
irq_start = i * IRQS_PER_IPC;
irq_end = min(irq_start + IRQS_PER_IPC - 1, ITSS_MAX_IRQ);
if (start > irq_end)
continue;
if (end < irq_start)
break;
/* Track bits within the bounds of of the register */
irq_start = max(start, irq_start) % IRQS_PER_IPC;
irq_end = min(end, irq_end) % IRQS_PER_IPC;
/* Create bitmask of the inclusive range of start and end */
mask = (((1U << irq_end) - 1) | (1U << irq_end));
mask &= ~((1U << irq_start) - 1);
reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
pcr_clrsetbits32(dev, reg, mask, mask & priv->irq_snapshot[i]);
}
show_polarities(dev, "After");
return 0;
}
#endif
static int apl_route_pmc_gpio_gpe(struct udevice *dev, uint pmc_gpe_num)
{
struct apl_itss_priv *priv = dev_get_priv(dev);
struct pmc_route *route;
int i;
for (i = 0, route = priv->route; i < priv->route_count; i++, route++) {
if (pmc_gpe_num == route->pmc)
return route->gpio;
}
return -ENOENT;
}
static int apl_itss_ofdata_to_platdata(struct udevice *dev)
{
struct apl_itss_priv *priv = dev_get_priv(dev);
int ret;
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct apl_itss_platdata *plat = dev_get_platdata(dev);
struct dtd_intel_apl_itss *dtplat = &plat->dtplat;
/*
* It would be nice to do this in the bind() method, but with
* of-platdata binding happens in the order that DM finds things in the
* linker list (i.e. alphabetical order by driver name). So the GPIO
* device may well be bound before its parent (p2sb), and this call
* will fail if p2sb is not bound yet.
*
* TODO(sjg@chromium.org): Add a parent pointer to child devices in dtoc
*/
ret = p2sb_set_port_id(dev, dtplat->intel_p2sb_port_id);
if (ret)
return log_msg_ret("Could not set port id", ret);
priv->route = (struct pmc_route *)dtplat->intel_pmc_routes;
priv->route_count = ARRAY_SIZE(dtplat->intel_pmc_routes) /
sizeof(struct pmc_route);
#else
int size;
size = dev_read_size(dev, "intel,pmc-routes");
if (size < 0)
return size;
priv->route = malloc(size);
if (!priv->route)
return -ENOMEM;
ret = dev_read_u32_array(dev, "intel,pmc-routes", (u32 *)priv->route,
size / sizeof(fdt32_t));
if (ret)
return log_msg_ret("Cannot read pmc-routes", ret);
priv->route_count = size / sizeof(struct pmc_route);
#endif
return 0;
}
static const struct irq_ops apl_itss_ops = {
.route_pmc_gpio_gpe = apl_route_pmc_gpio_gpe,
.set_polarity = apl_set_polarity,
#ifndef CONFIG_TPL_BUILD
.snapshot_polarities = apl_snapshot_polarities,
.restore_polarities = apl_restore_polarities,
#endif
};
static const struct udevice_id apl_itss_ids[] = {
{ .compatible = "intel,apl-itss"},
{ }
};
U_BOOT_DRIVER(apl_itss_drv) = {
.name = "intel_apl_itss",
.id = UCLASS_IRQ,
.of_match = apl_itss_ids,
.ops = &apl_itss_ops,
.ofdata_to_platdata = apl_itss_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct apl_itss_platdata),
.priv_auto_alloc_size = sizeof(struct apl_itss_priv),
};
arch/x86/cpu/apollolake/lpc.c 0 → 100644
浏览文件 @ c0912f9b
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 Google LLC
*
* From coreboot Apollo Lake support lpc.c
*/
#include <common.h>
#include <dm.h>
#include <spl.h>
#include <asm/lpc_common.h>
#include <asm/pci.h>
#include <asm/arch/iomap.h>
#include <asm/arch/lpc.h>
#include <linux/log2.h>
void lpc_enable_fixed_io_ranges(uint io_enables)
{
pci_x86_clrset_config(PCH_DEV_LPC, LPC_IO_ENABLES, 0, io_enables,
PCI_SIZE_16);
}
/*
* Find the first unused IO window.
* Returns -1 if not found, 0 for reg 0x84, 1 for reg 0x88 ...
*/
static int find_unused_pmio_window(void)
{
int i;
ulong lgir;
for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {
pci_x86_read_config(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i),
&lgir, PCI_SIZE_32);
if (!(lgir & LPC_LGIR_EN))
return i;
}
return -1;
}
int lpc_open_pmio_window(uint base, uint size)
{
int i, lgir_reg_num;
u32 lgir_reg_offset, lgir, window_size, alignment;
ulong bridged_size, bridge_base;
ulong reg;
log_debug("LPC: Trying to open IO window from %x size %x\n", base,
size);
bridged_size = 0;
bridge_base = base;
while (bridged_size < size) {
/* Each IO range register can only open a 256-byte window */
window_size = min(size, (uint)LPC_LGIR_MAX_WINDOW_SIZE);
/* Window size must be a power of two for the AMASK to work */
alignment = 1UL << (order_base_2(window_size));
window_size = ALIGN(window_size, alignment);
/* Address[15:2] in LGIR[15:12] and Mask[7:2] in LGIR[23:18] */
lgir = (bridge_base & LPC_LGIR_ADDR_MASK) | LPC_LGIR_EN;
lgir |= ((window_size - 1) << 16) & LPC_LGIR_AMASK_MASK;
/* Skip programming if same range already programmed */
for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {
pci_x86_read_config(PCH_DEV_LPC,
LPC_GENERIC_IO_RANGE(i), &reg,
PCI_SIZE_32);
if (lgir == reg)
return -EALREADY;
}
lgir_reg_num = find_unused_pmio_window();
if (lgir_reg_num < 0) {
log_err("LPC: Cannot open IO window: %lx size %lx\n",
bridge_base, size - bridged_size);
log_err("No more IO windows\n");
return -ENOSPC;
}
lgir_reg_offset = LPC_GENERIC_IO_RANGE(lgir_reg_num);
pci_x86_write_config(PCH_DEV_LPC, lgir_reg_offset, lgir,
PCI_SIZE_32);
log_debug("LPC: Opened IO window LGIR%d: base %lx size %x\n",
lgir_reg_num, bridge_base, window_size);
bridged_size += window_size;
bridge_base += window_size;
}
return 0;
}
void lpc_io_setup_comm_a_b(void)
{
/* ComA Range 3F8h-3FFh [2:0] */
u16 com_ranges = LPC_IOD_COMA_RANGE;
u16 com_enable = LPC_IOE_COMA_EN;
/* Setup I/O Decode Range Register for LPC */
pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, com_ranges);
/* Enable ComA and ComB Port */
lpc_enable_fixed_io_ranges(com_enable);
}
static const struct udevice_id apl_lpc_ids[] = {
{ .compatible = "intel,apl-lpc" },
{ }
};
/* All pads are LPC already configured by the hostbridge, so no probing here */
U_BOOT_DRIVER(apl_lpc_drv) = {
.name = "intel_apl_lpc",
.id = UCLASS_LPC,
.of_match = apl_lpc_ids,
};
arch/x86/cpu/apollolake/p2sb.c 0 → 100644
浏览文件 @ c0912f9b
// SPDX-License-Identifier: GPL-2.0
/*
* Primary-to-Sideband Bridge
*
* Copyright 2019 Google LLC
*/
#define LOG_CATEGORY UCLASS_P2SB
#include <common.h>
#include <dm.h>
#include <dt-structs.h>
#include <p2sb.h>
#include <spl.h>
#include <asm/pci.h>
struct p2sb_platdata {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_intel_apl_p2sb dtplat;
#endif
ulong mmio_base;
pci_dev_t bdf;
};
/* PCI config space registers */
#define HPTC_OFFSET 0x60
#define HPTC_ADDR_ENABLE_BIT BIT(7)
/* High Performance Event Timer Configuration */
#define P2SB_HPTC 0x60
#define P2SB_HPTC_ADDRESS_ENABLE BIT(7)
/*
* ADDRESS_SELECT ENCODING_RANGE
* 0 0xfed0 0000 - 0xfed0 03ff
* 1 0xfed0 1000 - 0xfed0 13ff
* 2 0xfed0 2000 - 0xfed0 23ff
* 3 0xfed0 3000 - 0xfed0 33ff
*/
#define P2SB_HPTC_ADDRESS_SELECT_0 (0 << 0)
#define P2SB_HPTC_ADDRESS_SELECT_1 (1 << 0)
#define P2SB_HPTC_ADDRESS_SELECT_2 (2 << 0)
#define P2SB_HPTC_ADDRESS_SELECT_3 (3 << 0)
/*
* apl_p2sb_early_init() - Enable decoding for HPET range
*
* This is needed by FSP-M which uses the High Precision Event Timer.
*
* @dev: P2SB device
* @return 0 if OK, -ve on error
*/
static int apl_p2sb_early_init(struct udevice *dev)
{
struct p2sb_platdata *plat = dev_get_platdata(dev);
pci_dev_t pdev = plat->bdf;
/*
* Enable decoding for HPET memory address range.
* HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode
* the High Performance Timer memory address range
* selected by bits 1:0
*/
pci_x86_write_config(pdev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT,
PCI_SIZE_8);
/* Enable PCR Base address in PCH */
pci_x86_write_config(pdev, PCI_BASE_ADDRESS_0, plat->mmio_base,
PCI_SIZE_32);
pci_x86_write_config(pdev, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
/* Enable P2SB MSE */
pci_x86_write_config(pdev, PCI_COMMAND, PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY, PCI_SIZE_8);
return 0;
}
static int apl_p2sb_spl_init(struct udevice *dev)
{
/* Enable decoding for HPET. Needed for FSP global pointer storage */
dm_pci_write_config(dev, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
P2SB_HPTC_ADDRESS_ENABLE, PCI_SIZE_8);
return 0;
}
int apl_p2sb_ofdata_to_platdata(struct udevice *dev)
{
struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev);
struct p2sb_platdata *plat = dev_get_platdata(dev);
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
int ret;
if (spl_phase() == PHASE_TPL) {
u32 base[2];
/* TPL sets up the initial BAR */
ret = dev_read_u32_array(dev, "early-regs", base,
ARRAY_SIZE(base));
if (ret)
return log_msg_ret("Missing/short early-regs", ret);
plat->mmio_base = base[0];
plat->bdf = pci_get_devfn(dev);
if (plat->bdf < 0)
return log_msg_ret("Cannot get p2sb PCI address",
plat->bdf);
} else {
plat->mmio_base = dev_read_addr_pci(dev);
/* Don't set BDF since it should not be used */
if (!plat->mmio_base || plat->mmio_base == FDT_ADDR_T_NONE)
return -EINVAL;
}
#else
plat->mmio_base = plat->dtplat.early_regs[0];
plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]);
#endif
upriv->mmio_base = plat->mmio_base;
debug("p2sb: mmio_base=%x\n", (uint)plat->mmio_base);
return 0;
}
static int apl_p2sb_probe(struct udevice *dev)
{
if (spl_phase() == PHASE_TPL)
return apl_p2sb_early_init(dev);
else if (spl_phase() == PHASE_SPL)
return apl_p2sb_spl_init(dev);
return 0;
}
static int p2sb_child_post_bind(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
int ret;
u32 pid;
ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid);
if (ret)
return ret;
pplat->pid = pid;
#endif
return 0;
}
static const struct udevice_id apl_p2sb_ids[] = {
{ .compatible = "intel,apl-p2sb" },
{ }
};
U_BOOT_DRIVER(apl_p2sb_drv) = {
.name = "intel_apl_p2sb",
.id = UCLASS_P2SB,
.of_match = apl_p2sb_ids,
.probe = apl_p2sb_probe,
.ofdata_to_platdata = apl_p2sb_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct p2sb_platdata),
.per_child_platdata_auto_alloc_size =
sizeof(struct p2sb_child_platdata),
.child_post_bind = p2sb_child_post_bind,
};
arch/x86/cpu/apollolake/pch.c 0 → 100644
浏览文件 @ c0912f9b
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 Google LLC
*/
#include <common.h>
#include <dm.h>
#include <pch.h>
#include <spl.h>
#include <asm/lpc_common.h>
#define BIOS_CTRL 0xdc
static int apl_set_spi_protect(struct udevice *dev, bool protect)
{
if (spl_phase() == PHASE_SPL)
return lpc_set_spi_protect(dev, BIOS_CTRL, protect);
return 0;
}
static const struct pch_ops apl_pch_ops = {
.set_spi_protect = apl_set_spi_protect,
};
static const struct udevice_id apl_pch_ids[] = {
{ .compatible = "intel,apl-pch" },
{ }
};
U_BOOT_DRIVER(apl_pch) = {
.name = "apl_pch",
.id = UCLASS_PCH,
.of_match = apl_pch_ids,
.ops = &apl_pch_ops,
};
arch/x86/cpu/apollolake/pmc.c 0 → 100644
浏览文件 @ c0912f9b
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 Intel Corporation.
* Copyright 2019 Google LLC
*
* Modified from coreboot pmclib.c, pmc.c and pmutil.c
*/
#define LOG_CATEGORY UCLASS_ACPI_PMC
#include <common.h>
#include <acpi_s3.h>
#include <dt-structs.h>
#include <dm.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/pci.h>
#include <power/acpi_pmc.h>
#define GPIO_GPE_CFG 0x1050
/* Memory mapped IO registers behind PMC_BASE_ADDRESS */
#define PRSTS 0x1000
#define GEN_PMCON1 0x1020
#define COLD_BOOT_STS BIT(27)
#define COLD_RESET_STS BIT(26)
#define WARM_RESET_STS BIT(25)
#define GLOBAL_RESET_STS BIT(24)
#define SRS BIT(20)
#define MS4V BIT(18)
#define RPS BIT(2)
#define GEN_PMCON1_CLR1_BITS (COLD_BOOT_STS | COLD_RESET_STS | \
WARM_RESET_STS | GLOBAL_RESET_STS | \
SRS | MS4V)
#define GEN_PMCON2 0x1024
#define GEN_PMCON3 0x1028
/* Offset of TCO registers from ACPI base I/O address */
#define TCO_REG_OFFSET 0x60
#define TCO1_STS 0x64
#define DMISCI_STS BIT(9)
#define BOOT_STS BIT(18)
#define TCO2_STS 0x66
#define TCO1_CNT 0x68
#define TCO_LOCK BIT(12)
#define TCO2_CNT 0x6a
enum {
ETR = 0x1048,
CF9_LOCK = 1UL << 31,
CF9_GLB_RST = 1 << 20,
};
struct apl_pmc_platdata {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_intel_apl_pmc dtplat;
#endif
pci_dev_t bdf;
};
static int apl_pmc_fill_power_state(struct udevice *dev)
{
struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
upriv->tco1_sts = inw(upriv->acpi_base + TCO1_STS);
upriv->tco2_sts = inw(upriv->acpi_base + TCO2_STS);
upriv->prsts = readl(upriv->pmc_bar0 + PRSTS);
upriv->gen_pmcon1 = readl(upriv->pmc_bar0 + GEN_PMCON1);
upriv->gen_pmcon2 = readl(upriv->pmc_bar0 + GEN_PMCON2);
upriv->gen_pmcon3 = readl(upriv->pmc_bar0 + GEN_PMCON3);
return 0;
}
static int apl_prev_sleep_state(struct udevice *dev, int prev_sleep_state)
{
struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
/* WAK_STS bit will not be set when waking from G3 state */
if (!(upriv->pm1_sts & WAK_STS) &&
(upriv->gen_pmcon1 & COLD_BOOT_STS))
prev_sleep_state = ACPI_S5;
return prev_sleep_state;
}
static int apl_disable_tco(struct udevice *dev)
{
struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
pmc_disable_tco_base(upriv->acpi_base + TCO_REG_OFFSET);
return 0;
}
static int apl_global_reset_set_enable(struct udevice *dev, bool enable)
{
struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
if (enable)
setbits_le32(upriv->pmc_bar0 + ETR, CF9_GLB_RST);
else
clrbits_le32(upriv->pmc_bar0 + ETR, CF9_GLB_RST);
return 0;
}
int apl_pmc_ofdata_to_uc_platdata(struct udevice *dev)
{
struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
struct apl_pmc_platdata *plat = dev_get_platdata(dev);
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
u32 base[6];
int size;
int ret;
ret = dev_read_u32_array(dev, "early-regs", base, ARRAY_SIZE(base));
if (ret)
return log_msg_ret("Missing/short early-regs", ret);
upriv->pmc_bar0 = (void *)base[0];
upriv->pmc_bar2 = (void *)base[2];
upriv->acpi_base = base[4];
/* Since PCI is not enabled, we must get the BDF manually */
plat->bdf = pci_get_devfn(dev);
if (plat->bdf < 0)
return log_msg_ret("Cannot get PMC PCI address", plat->bdf);
/* Get the dwX values for pmc gpe settings */
size = dev_read_size(dev, "gpe0-dw");
if (size < 0)
return log_msg_ret("Cannot read gpe0-dm", size);
upriv->gpe0_count = size / sizeof(u32);
ret = dev_read_u32_array(dev, "gpe0-dw", upriv->gpe0_dw,
upriv->gpe0_count);
if (ret)
return log_msg_ret("Bad gpe0-dw", ret);
return pmc_ofdata_to_uc_platdata(dev);
#else
struct dtd_intel_apl_pmc *dtplat = &plat->dtplat;
plat->bdf = pci_ofplat_get_devfn(dtplat->reg[0]);
upriv->pmc_bar0 = (void *)dtplat->early_regs[0];
upriv->pmc_bar2 = (void *)dtplat->early_regs[2];
upriv->acpi_base = dtplat->early_regs[4];
upriv->gpe0_dwx_mask = dtplat->gpe0_dwx_mask;
upriv->gpe0_dwx_shift_base = dtplat->gpe0_dwx_shift_base;
upriv->gpe0_sts_reg = dtplat->gpe0_sts;
upriv->gpe0_sts_reg += upriv->acpi_base;
upriv->gpe0_en_reg = dtplat->gpe0_en;
upriv->gpe0_en_reg += upriv->acpi_base;
upriv->gpe0_count = min((int)ARRAY_SIZE(dtplat->gpe0_dw), GPE0_REG_MAX);
memcpy(upriv->gpe0_dw, dtplat->gpe0_dw, sizeof(dtplat->gpe0_dw));
#endif
upriv->gpe_cfg = (u32 *)(upriv->pmc_bar0 + GPIO_GPE_CFG);
return 0;
}
static int enable_pmcbar(struct udevice *dev)
{
struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
struct apl_pmc_platdata *priv = dev_get_platdata(dev);
pci_dev_t pmc = priv->bdf;
/*
* Set PMC base addresses and enable decoding. BARs 1 and 3 are 64-bit
* BARs.
*/
pci_x86_write_config(pmc, PCI_BASE_ADDRESS_0, (ulong)upriv->pmc_bar0,
PCI_SIZE_32);
pci_x86_write_config(pmc, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
pci_x86_write_config(pmc, PCI_BASE_ADDRESS_2, (ulong)upriv->pmc_bar2,
PCI_SIZE_32);
pci_x86_write_config(pmc, PCI_BASE_ADDRESS_3, 0, PCI_SIZE_32);
pci_x86_write_config(pmc, PCI_BASE_ADDRESS_4, upriv->acpi_base,
PCI_SIZE_16);
pci_x86_write_config(pmc, PCI_COMMAND, PCI_COMMAND_IO |
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
PCI_SIZE_16);
return 0;
}
static int apl_pmc_probe(struct udevice *dev)
{
if (spl_phase() == PHASE_TPL)
return enable_pmcbar(dev);
return 0;
}
static struct acpi_pmc_ops apl_pmc_ops = {
.init = apl_pmc_fill_power_state,
.prev_sleep_state = apl_prev_sleep_state,
.disable_tco = apl_disable_tco,
.global_reset_set_enable = apl_global_reset_set_enable,
};
static const struct udevice_id apl_pmc_ids[] = {
{ .compatible = "intel,apl-pmc" },
{ }
};
U_BOOT_DRIVER(apl_pmc) = {
.name = "intel_apl_pmc",
.id = UCLASS_ACPI_PMC,
.of_match = apl_pmc_ids,
.ofdata_to_platdata = apl_pmc_ofdata_to_uc_platdata,
.probe = apl_pmc_probe,
.ops = &apl_pmc_ops,
.platdata_auto_alloc_size = sizeof(struct apl_pmc_platdata),
};
arch/x86/cpu/apollolake/punit.c 0 → 100644
浏览文件 @ c0912f9b
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 Google LLC
*/
#include <common.h>
#include <dm.h>
#include <spl.h>
#include <asm/cpu.h>
#include <asm/cpu_common.h>
#include <asm/intel_regs.h>
#include <asm/io.h>
#include <asm/pci.h>
#include <asm/arch/systemagent.h>
/*
* Punit Initialisation code. This all isn't documented, but
* this is the recipe.
*/
static int punit_init(struct udevice *dev)
{
struct udevice *cpu;
u32 reg;
ulong start;
int ret;
/* Thermal throttle activation offset */
ret = uclass_first_device_err(UCLASS_CPU, &cpu);
if (ret)
return log_msg_ret("Cannot find CPU", ret);
cpu_configure_thermal_target(cpu);
/*
* Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR).
* Enable all cores here.
*/
writel(0, MCHBAR_REG(CORE_DISABLE_MASK));
/* P-Unit bring up */
reg = readl(MCHBAR_REG(BIOS_RESET_CPL));
if (reg == 0xffffffff) {
/* P-unit not found */
debug("Punit MMIO not available\n");
return -ENOENT;
}
/* Set Punit interrupt pin IPIN offset 3D */
dm_pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x2);
/* Set PUINT IRQ to 24 and INTPIN LOCK */
writel(PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER |
PUINT_THERMAL_DEVICE_IRQ_LOCK,
MCHBAR_REG(PUNIT_THERMAL_DEVICE_IRQ));
/* Stage0 BIOS Reset Complete (RST_CPL) */
enable_bios_reset_cpl();
/*
* Poll for bit 8 to check if PCODE has completed its action in response
* to BIOS Reset complete. We wait here till 1 ms for the bit to get
* set.
*/
start = get_timer(0);
while (!(readl(MCHBAR_REG(BIOS_RESET_CPL)) & PCODE_INIT_DONE)) {
if (get_timer(start) > 1) {
debug("PCODE Init Done timeout\n");
return -ETIMEDOUT;
}
udelay(100);
}
debug("PUNIT init complete\n");
return 0;
}
static int apl_punit_probe(struct udevice *dev)
{
if (spl_phase() == PHASE_SPL)
return punit_init(dev);
return 0;
}
static const struct udevice_id apl_syscon_ids[] = {
{ .compatible = "intel,apl-punit", .data = X86_SYSCON_PUNIT },
{ }
};
U_BOOT_DRIVER(syscon_intel_punit) = {
.name = "intel_punit_syscon",
.id = UCLASS_SYSCON,
.of_match = apl_syscon_ids,
.probe = apl_punit_probe,
};
arch/x86/cpu/apollolake/spl.c 0 → 100644
浏览文件 @ c0912f9b
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 Google LLC
*/
#include <common.h>
#include <binman_sym.h>
#include <dm.h>
#include <spi.h>
#include <spl.h>
#include <spi_flash.h>
#include <asm/fast_spi.h>
#include <asm/spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/iomap.h>
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
/* This reads the next phase from mapped SPI flash */
static int rom_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
ulong spl_pos = spl_get_image_pos();
ulong spl_size = spl_get_image_size();
struct udevice *dev;
ulong map_base;
size_t map_size;
uint offset;
int ret;
spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
spl_image->entry_point = spl_phase() == PHASE_TPL ?
CONFIG_SPL_TEXT_BASE : CONFIG_SYS_TEXT_BASE;
spl_image->load_addr = spl_image->entry_point;
spl_image->os = IH_OS_U_BOOT;
spl_image->name = "U-Boot";
debug("Reading from mapped SPI %lx, size %lx", spl_pos, spl_size);
if (CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)) {
ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev);
if (ret)
return log_msg_ret("spi_flash", ret);
if (!dev)
return log_msg_ret("spi_flash dev", -ENODEV);
ret = dm_spi_get_mmap(dev, &map_base, &map_size, &offset);
if (ret)
return log_msg_ret("mmap", ret);
} else {
ret = fast_spi_get_bios_mmap(PCH_DEV_SPI, &map_base, &map_size,
&offset);
if (ret)
return ret;
}
spl_pos += map_base & ~0xff000000;
debug(", base %lx, pos %lx\n", map_base, spl_pos);
bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
memcpy((void *)spl_image->load_addr, (void *)spl_pos, spl_size);
cpu_flush_l1d_to_l2();
bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
return 0;
}
SPL_LOAD_IMAGE_METHOD("Mapped SPI", 2, BOOT_DEVICE_SPI_MMAP, rom_load_image);
#if CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)
static int apl_flash_std_read(struct udevice *dev, u32 offset, size_t len,
void *buf)
{
struct spi_flash *flash = dev_get_uclass_priv(dev);
struct mtd_info *mtd = &flash->mtd;
size_t retlen;
return log_ret(mtd->_read(mtd, offset, len, &retlen, buf));
}
static int apl_flash_probe(struct udevice *dev)
{
return spi_flash_std_probe(dev);
}
/*
* Manually set the parent of the SPI flash to SPI, since dtoc doesn't. We also
* need to allocate the parent_platdata since by the time this function is
* called device_bind() has already gone past that step.
*/
static int apl_flash_bind(struct udevice *dev)
{
if (CONFIG_IS_ENABLED(OF_PLATDATA)) {
struct dm_spi_slave_platdata *plat;
struct udevice *spi;
int ret;
ret = uclass_first_device_err(UCLASS_SPI, &spi);
if (ret)
return ret;
dev->parent = spi;
plat = calloc(sizeof(*plat), 1);
if (!plat)
return -ENOMEM;
dev->parent_platdata = plat;
}
return 0;
}
static const struct dm_spi_flash_ops apl_flash_ops = {
.read = apl_flash_std_read,
};
static const struct udevice_id apl_flash_ids[] = {
{ .compatible = "jedec,spi-nor" },
{ }
};
U_BOOT_DRIVER(winbond_w25q128fw) = {
.name = "winbond_w25q128fw",
.id = UCLASS_SPI_FLASH,
.of_match = apl_flash_ids,
.bind = apl_flash_bind,
.probe = apl_flash_probe,
.priv_auto_alloc_size = sizeof(struct spi_flash),
.ops = &apl_flash_ops,
};
/* This uses a SPI flash device to read the next phase */
static int spl_fast_spi_load_image(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
ulong spl_pos = spl_get_image_pos();
ulong spl_size = spl_get_image_size();
struct udevice *dev;
int ret;
ret = uclass_first_device_err(UCLASS_SPI_FLASH, &dev);
if (ret)
return ret;
spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
spl_image->entry_point = spl_phase() == PHASE_TPL ?
CONFIG_SPL_TEXT_BASE : CONFIG_SYS_TEXT_BASE;
spl_image->load_addr = spl_image->entry_point;
spl_image->os = IH_OS_U_BOOT;
spl_image->name = "U-Boot";
spl_pos &= ~0xff000000;
debug("Reading from flash %lx, size %lx\n", spl_pos, spl_size);
ret = spi_flash_read_dm(dev, spl_pos, spl_size,
(void *)spl_image->load_addr);
cpu_flush_l1d_to_l2();
if (ret)
return ret;
return 0;
}
SPL_LOAD_IMAGE_METHOD("Fast SPI", 1, BOOT_DEVICE_FAST_SPI,
spl_fast_spi_load_image);
void board_boot_order(u32 *spl_boot_list)
{
bool use_spi_flash = IS_ENABLED(CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH);
if (use_spi_flash) {
spl_boot_list[0] = BOOT_DEVICE_FAST_SPI;
spl_boot_list[1] = BOOT_DEVICE_SPI_MMAP;
} else {
spl_boot_list[0] = BOOT_DEVICE_SPI_MMAP;
spl_boot_list[1] = BOOT_DEVICE_FAST_SPI;
}
}
#else
void board_boot_order(u32 *spl_boot_list)
{
spl_boot_list[0] = BOOT_DEVICE_SPI_MMAP;
}
#endif
arch/x86/cpu/apollolake/systemagent.c 0 → 100644
浏览文件 @ c0912f9b
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 Intel Corporation.
* Take from coreboot project file of the same name
*/
#include <common.h>
#include <asm/intel_regs.h>
#include <asm/io.h>
#include <asm/arch/systemagent.h>
void enable_bios_reset_cpl(void)
{
/*
* Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU
* that BIOS has initialised memory and power management
*
* The FSP-S does not do this. If we leave this as zero then I believe
* the power-aware interrupts don't work in Linux, and CPU 0 always gets
* the interrupt.
*/
setbits_8(MCHBAR_REG(BIOS_RESET_CPL), 3);
}
arch/x86/cpu/apollolake/uart.c 0 → 100644
浏览文件 @ c0912f9b
// SPDX-License-Identifier: GPL-2.0
/*
* Special driver to handle of-platdata
*
* Copyright 2019 Google LLC
*
* Some code from coreboot lpss.c
*/
#include <common.h>
#include <dm.h>
#include <dt-structs.h>
#include <ns16550.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/pci.h>
#include <asm/lpss.h>
/* Low-power Subsystem (LPSS) clock register */
enum {
LPSS_CLOCK_CTL_REG = 0x200,
LPSS_CNT_CLOCK_EN = 1,
LPSS_CNT_CLK_UPDATE = 1U << 31,
LPSS_CLOCK_DIV_N_SHIFT = 16,
LPSS_CLOCK_DIV_N_MASK = 0x7fff << LPSS_CLOCK_DIV_N_SHIFT,
LPSS_CLOCK_DIV_M_SHIFT = 1,
LPSS_CLOCK_DIV_M_MASK = 0x7fff << LPSS_CLOCK_DIV_M_SHIFT,
/* These set the UART input clock speed */
LPSS_UART_CLK_M_VAL = 0x25a,
LPSS_UART_CLK_N_VAL = 0x7fff,
};
static void lpss_clk_update(void *regs, u32 clk_m_val, u32 clk_n_val)
{
u32 clk_sel;
clk_sel = clk_n_val << LPSS_CLOCK_DIV_N_SHIFT |
clk_m_val << LPSS_CLOCK_DIV_M_SHIFT;
clk_sel |= LPSS_CNT_CLK_UPDATE | LPSS_CNT_CLOCK_EN;
writel(clk_sel, regs + LPSS_CLOCK_CTL_REG);
}
static void uart_lpss_init(void *regs)
{
/* Take UART out of reset */
lpss_reset_release(regs);
/* Set M and N divisor inputs and enable clock */
lpss_clk_update(regs, LPSS_UART_CLK_M_VAL, LPSS_UART_CLK_N_VAL);
}
void apl_uart_init(pci_dev_t bdf, ulong base)
{
/* Set UART base address */
pci_x86_write_config(bdf, PCI_BASE_ADDRESS_0, base, PCI_SIZE_32);
/* Enable memory access and bus master */
pci_x86_write_config(bdf, PCI_COMMAND, PCI_COMMAND_MEMORY |
PCI_COMMAND_MASTER, PCI_SIZE_32);
uart_lpss_init((void *)base);
}
/*
* This driver uses its own compatible string but almost everything else from
* the standard ns16550 driver. This allows us to provide an of-platdata
* implementation, since the platdata produced by of-platdata does not match
* struct ns16550_platdata.
*
* When running with of-platdata (generally TPL), the platdata is converted to
* something that ns16550 expects. When running withoutof-platdata (SPL, U-Boot
* proper), we use ns16550's ofdata_to_platdata routine.
*/
static int apl_ns16550_probe(struct udevice *dev)
{
struct ns16550_platdata *plat = dev_get_platdata(dev);
if (!CONFIG_IS_ENABLED(PCI))
apl_uart_init(plat->bdf, plat->base);
return ns16550_serial_probe(dev);
}
static int apl_ns16550_ofdata_to_platdata(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_intel_apl_ns16550 *dtplat = dev_get_platdata(dev);
struct ns16550_platdata *plat;
/*
* Convert our platdata to the ns16550's platdata, so we can just use
* that driver
*/
plat = malloc(sizeof(*plat));
if (!plat)
return -ENOMEM;
plat->base = dtplat->early_regs[0];
plat->reg_width = 1;
plat->reg_shift = dtplat->reg_shift;
plat->reg_offset = 0;
plat->clock = dtplat->clock_frequency;
plat->fcr = UART_FCR_DEFVAL;
plat->bdf = pci_ofplat_get_devfn(dtplat->reg[0]);
dev->platdata = plat;
#else
int ret;
ret = ns16550_serial_ofdata_to_platdata(dev);
if (ret)
return ret;
#endif /* OF_PLATDATA */
return 0;
}
static const struct udevice_id apl_ns16550_serial_ids[] = {
{ .compatible = "intel,apl-ns16550" },
{ },
};
U_BOOT_DRIVER(apl_ns16550) = {
.name = "intel_apl_ns16550",
.id = UCLASS_SERIAL,
.of_match = apl_ns16550_serial_ids,
.platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
.priv_auto_alloc_size = sizeof(struct NS16550),
.ops = &ns16550_serial_ops,
.ofdata_to_platdata = apl_ns16550_ofdata_to_platdata,
.probe = apl_ns16550_probe,
};
arch/x86/cpu/broadwell/sdram.c
浏览文件 @ c0912f9b
......@@ -83,7 +83,7 @@ static int prepare_mrc_cache(struct pei_data *pei_data)
struct mrc_region entry;
int ret;
ret = mrccache_get_region(NULL, &entry);
ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry);
if (ret)
return ret;
mrc_cache = mrccache_find_current(&entry);
......@@ -169,12 +169,14 @@ int dram_init(void)
pei_data->data_to_save);
/* S3 resume: don't save scrambler seed or MRC data */
if (pei_data->boot_mode != SLEEP_STATE_S3) {
struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL];
/*
* This will be copied to SDRAM in reserve_arch(), then written
* to SPI flash in mrccache_save()
*/
gd->arch.mrc_output = (char *)pei_data->data_to_save;
gd->arch.mrc_output_len = pei_data->data_to_save_size;
mrc->buf = (char *)pei_data->data_to_save;
mrc->len = pei_data->data_to_save_size;
}
gd->arch.pei_meminfo = pei_data->meminfo;
......
arch/x86/cpu/coreboot/Kconfig
浏览文件 @ c0912f9b
......@@ -24,5 +24,6 @@ config SYS_COREBOOT
imply CMD_CBFS
imply FS_CBFS
imply CBMEM_CONSOLE
imply X86_TSC_READ_BASE
endif
arch/x86/cpu/cpu.c
浏览文件 @ c0912f9b
......@@ -46,6 +46,7 @@
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_TPL_BUILD
static const char *const x86_vendor_name[] = {
[X86_VENDOR_INTEL] = "Intel",
[X86_VENDOR_CYRIX] = "Cyrix",
......@@ -58,6 +59,7 @@ static const char *const x86_vendor_name[] = {
[X86_VENDOR_NSC] = "NSC",
[X86_VENDOR_SIS] = "SiS",
};
#endif
int __weak x86_cleanup_before_linux(void)
{
......@@ -114,6 +116,7 @@ int icache_status(void)
return 1;
}
#ifndef CONFIG_TPL_BUILD
const char *cpu_vendor_name(int vendor)
{
const char *name;
......@@ -124,6 +127,7 @@ const char *cpu_vendor_name(int vendor)
return name;
}
#endif
char *cpu_get_name(char *name)
{
......
arch/x86/cpu/i386/Makefile
浏览文件 @ c0912f9b
......@@ -5,5 +5,7 @@
obj-y += call64.o
obj-y += cpu.o
ifndef CONFIG_TPL_BUILD
obj-y += interrupt.o
endif
obj-y += setjmp.o
arch/x86/cpu/i386/cpu.c
浏览文件 @ c0912f9b
......@@ -21,6 +21,7 @@
#include <common.h>
#include <cpu_func.h>
#include <malloc.h>
#include <spl.h>
#include <asm/control_regs.h>
#include <asm/cpu.h>
#include <asm/mp.h>
......@@ -58,6 +59,8 @@ struct cpuinfo_x86 {
uint8_t x86_mask;
};
/* gcc 7.3 does not wwant to drop x86_vendors, so use #ifdef */
#ifndef CONFIG_TPL_BUILD
/*
* List of cpu vendor strings along with their normalized
* id values.
......@@ -78,6 +81,7 @@ static const struct {
{ X86_VENDOR_NSC, "Geode by NSC", },
{ X86_VENDOR_SIS, "SiS SiS SiS ", },
};
#endif
static void load_ds(u32 segment)
{
......@@ -199,6 +203,7 @@ static inline int test_cyrix_52div(void)
return (unsigned char) (test >> 8) == 0x02;
}
#ifndef CONFIG_TPL_BUILD
/*
* Detect a NexGen CPU running without BIOS hypercode new enough
* to have CPUID. (Thanks to Herbert Oppmann)
......@@ -219,6 +224,7 @@ static int deep_magic_nexgen_probe(void)
: "=a" (ret) : : "cx", "dx");
return ret;
}
#endif
static bool has_cpuid(void)
{
......@@ -230,6 +236,7 @@ static bool has_mtrr(void)
return cpuid_edx(0x00000001) & (1 << 12) ? true : false;
}
#ifndef CONFIG_TPL_BUILD
static int build_vendor_name(char *vendor_name)
{
struct cpuid_result result;
......@@ -242,14 +249,40 @@ static int build_vendor_name(char *vendor_name)
return result.eax;
}
#endif
static void identify_cpu(struct cpu_device_id *cpu)
{
cpu->device = 0; /* fix gcc 4.4.4 warning */
/*
* Do a quick and dirty check to save space - Intel and AMD only and
* just the vendor. This is enough for most TPL code.
*/
if (spl_phase() == PHASE_TPL) {
struct cpuid_result result;
result = cpuid(0x00000000);
switch (result.ecx >> 24) {
case 'l': /* GenuineIntel */
cpu->vendor = X86_VENDOR_INTEL;
break;
case 'D': /* AuthenticAMD */
cpu->vendor = X86_VENDOR_AMD;
break;
default:
cpu->vendor = X86_VENDOR_ANY;
break;
}
return;
}
/* gcc 7.3 does not want to drop x86_vendors, so use #ifdef */
#ifndef CONFIG_TPL_BUILD
char vendor_name[16];
int i;
vendor_name[0] = '\0'; /* Unset */
cpu->device = 0; /* fix gcc 4.4.4 warning */
/* Find the id and vendor_name */
if (!has_cpuid()) {
......@@ -265,9 +298,8 @@ static void identify_cpu(struct cpu_device_id *cpu)
/* Detect NexGen with old hypercode */
else if (deep_magic_nexgen_probe())
memcpy(vendor_name, "NexGenDriven", 13);
}
if (has_cpuid()) {
int cpuid_level;
} else {
int cpuid_level;
cpuid_level = build_vendor_name(vendor_name);
vendor_name[12] = '\0';
......@@ -287,6 +319,7 @@ static void identify_cpu(struct cpu_device_id *cpu)
break;
}
}
#endif
}
static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
......
arch/x86/cpu/intel_common/Makefile
浏览文件 @ c0912f9b
......@@ -8,8 +8,18 @@ obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += me_status.o
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += report_platform.o
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += mrc.o
endif
ifdef CONFIG_INTEL_CAR_CQOS
obj-$(CONFIG_TPL_BUILD) += car2.o
ifndef CONFIG_SPL_BUILD
obj-y += car2_uninit.o
endif
endif
obj-y += cpu.o
obj-y += fast_spi.o
obj-y += lpc.o
obj-y += lpss.o
ifndef CONFIG_TARGET_EFI_APP
obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += microcode.o
ifndef CONFIG_$(SPL_)X86_64
......
arch/x86/cpu/intel_common/car2.S 0 → 100644
浏览文件 @ c0912f9b
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This file was modified from the coreboot version.
*
* Copyright (C) 2015-2016 Intel Corp.
*/
#include <config.h>
#include <asm/msr-index.h>
#include <asm/mtrr.h>
#include <asm/post.h>
#include <asm/processor.h>
#include <asm/processor-flags.h>
#define KiB 1024
#define IS_POWER_OF_2(x) (!((x) & ((x) - 1)))
.global car_init
car_init:
post_code(POST_CAR_START)
/*
* Use the MTRR default type MSR as a proxy for detecting INIT#.
* Reset the system if any known bits are set in that MSR. That is
* an indication of the CPU not being properly reset.
*/
check_for_clean_reset:
mov $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
and $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax
cmp $0, %eax
jz no_reset
/* perform warm reset */
movw $IO_PORT_RESET, %dx
movb $(SYS_RST | RST_CPU), %al
outb %al, %dx
no_reset:
post_code(POST_CAR_SIPI)
/* Clear/disable fixed MTRRs */
mov $fixed_mtrr_list_size, %ebx
xor %eax, %eax
xor %edx, %edx
clear_fixed_mtrr:
add $-2, %ebx
movzwl fixed_mtrr_list(%ebx), %ecx
wrmsr
jnz clear_fixed_mtrr
post_code(POST_CAR_MTRR)
/* Figure put how many MTRRs we have, and clear them out */
mov $MTRR_CAP_MSR, %ecx
rdmsr
movzb %al, %ebx /* Number of variable MTRRs */
mov $MTRR_PHYS_BASE_MSR(0), %ecx
xor %eax, %eax
xor %edx, %edx
clear_var_mtrr:
wrmsr
inc %ecx
wrmsr
inc %ecx
dec %ebx
jnz clear_var_mtrr
post_code(POST_CAR_UNCACHEABLE)
/* Configure default memory type to uncacheable (UC) */
mov $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
/* Clear enable bits and set default type to UC */
and $~(MTRR_DEF_TYPE_MASK | MTRR_DEF_TYPE_EN | \
MTRR_DEF_TYPE_FIX_EN), %eax
wrmsr
/*
* Configure MTRR_PHYS_MASK_HIGH for proper addressing above 4GB
* based on the physical address size supported for this processor
* This is based on read from CPUID EAX = 080000008h, EAX bits [7:0]
*
* Examples:
* MTRR_PHYS_MASK_HIGH = 00000000Fh For 36 bit addressing
* MTRR_PHYS_MASK_HIGH = 0000000FFh For 40 bit addressing
*/
movl $0x80000008, %eax /* Address sizes leaf */
cpuid
sub $32, %al
movzx %al, %eax
xorl %esi, %esi
bts %eax, %esi
dec %esi /* esi <- MTRR_PHYS_MASK_HIGH */
post_code(POST_CAR_BASE_ADDRESS)
#if IS_POWER_OF_2(CONFIG_DCACHE_RAM_SIZE)
/* Configure CAR region as write-back (WB) */
mov $MTRR_PHYS_BASE_MSR(0), %ecx
mov $CONFIG_DCACHE_RAM_BASE, %eax
or $MTRR_TYPE_WRBACK, %eax
xor %edx,%edx
wrmsr
/* Configure the MTRR mask for the size region */
mov $MTRR_PHYS_MASK(0), %ecx
mov $CONFIG_DCACHE_RAM_SIZE, %eax /* size mask */
dec %eax
not %eax
or $MTRR_PHYS_MASK_VALID, %eax
movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */
wrmsr
#elif (CONFIG_DCACHE_RAM_SIZE == 768 * KiB) /* 768 KiB */
/* Configure CAR region as write-back (WB) */
mov $MTRR_PHYS_BASE_MSR(0), %ecx
mov $CONFIG_DCACHE_RAM_BASE, %eax
or $MTRR_TYPE_WRBACK, %eax
xor %edx,%edx
wrmsr
mov $MTRR_PHYS_MASK_MSR(0), %ecx
mov $(512 * KiB), %eax /* size mask */
dec %eax
not %eax
or $MTRR_PHYS_MASK_VALID, %eax
movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */
wrmsr
mov $MTRR_PHYS_BASE_MSR(1), %ecx
mov $(CONFIG_DCACHE_RAM_BASE + 512 * KiB), %eax
or $MTRR_TYPE_WRBACK, %eax
xor %edx,%edx
wrmsr
mov $MTRR_PHYS_MASK_MSR(1), %ecx
mov $(256 * KiB), %eax /* size mask */
dec %eax
not %eax
or $MTRR_PHYS_MASK_VALID, %eax
movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */
wrmsr
#else
#error "DCACHE_RAM_SIZE is not a power of 2 and setup code is missing"
#endif
post_code(POST_CAR_FILL)
/* Enable variable MTRRs */
mov $MTRR_DEF_TYPE_MSR, %ecx
rdmsr
or $MTRR_DEF_TYPE_EN, %eax
wrmsr
/* Enable caching */
mov %cr0, %eax
and $~(X86_CR0_CD | X86_CR0_NW), %eax
invd
mov %eax, %cr0
#if IS_ENABLED(CONFIG_INTEL_CAR_NEM)
jmp car_nem
#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS)
jmp car_cqos
#elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED)
jmp car_nem_enhanced
#else
#error "No CAR mechanism selected:
#endif
jmp car_init_ret
fixed_mtrr_list:
.word MTRR_FIX_64K_00000_MSR
.word MTRR_FIX_16K_80000_MSR
.word MTRR_FIX_16K_A0000_MSR
.word MTRR_FIX_4K_C0000_MSR
.word MTRR_FIX_4K_C8000_MSR
.word MTRR_FIX_4K_D0000_MSR
.word MTRR_FIX_4K_D8000_MSR
.word MTRR_FIX_4K_E0000_MSR
.word MTRR_FIX_4K_E8000_MSR
.word MTRR_FIX_4K_F0000_MSR
.word MTRR_FIX_4K_F8000_MSR
fixed_mtrr_list_size = . - fixed_mtrr_list
#if IS_ENABLED(CONFIG_INTEL_CAR_NEM)
.global car_nem
car_nem:
/* Disable cache eviction (setup stage) */
mov $MSR_EVICT_CTL, %ecx
rdmsr
or $0x1, %eax
wrmsr
post_code(0x26)
/* Clear the cache memory region. This will also fill up the cache */
movl $CONFIG_DCACHE_RAM_BASE, %edi
movl $CONFIG_DCACHE_RAM_SIZE, %ecx
shr $0x02, %ecx
xor %eax, %eax
cld
rep stosl
post_code(0x27)
/* Disable cache eviction (run stage) */
mov $MSR_EVICT_CTL, %ecx
rdmsr
or $0x2, %eax
wrmsr
post_code(0x28)
jmp car_init_ret
#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS)
.global car_cqos
car_cqos:
/*
* Create CBM_LEN_MASK based on CBM_LEN
* Get CPUID.(EAX=10H, ECX=2H):EAX.CBM_LEN[bits 4:0]
*/
mov $0x10, %eax
mov $0x2, %ecx
cpuid
and $0x1f, %eax
add $1, %al
mov $1, %ebx
mov %al, %cl
shl %cl, %ebx
sub $1, %ebx
/* Store the CBM_LEN_MASK in mm3 for later use */
movd %ebx, %mm3
/*
* Disable both L1 and L2 prefetcher. For yet-to-understood reason,
* prefetchers slow down filling cache with rep stos in CQOS mode.
*/
mov $MSR_PREFETCH_CTL, %ecx
rdmsr
or $(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax
wrmsr
#if (CONFIG_DCACHE_RAM_SIZE == CONFIG_L2_CACHE_SIZE)
/*
* If CAR size is set to full L2 size, mask is calculated as all-zeros.
* This is not supported by the CPU/uCode.
*/
#error "CQOS CAR may not use whole L2 cache area"
#endif
/* Calculate how many bits to be used for CAR */
xor %edx, %edx
mov $CONFIG_DCACHE_RAM_SIZE, %eax /* dividend */
mov $CONFIG_CACHE_QOS_SIZE_PER_BIT, %ecx /* divisor */
div %ecx /* result is in eax */
mov %eax, %ecx /* save to ecx */
mov $1, %ebx
shl %cl, %ebx
sub $1, %ebx /* resulting mask is is in ebx */
/* Set this mask for initial cache fill */
mov $MSR_L2_QOS_MASK(0), %ecx
rdmsr
mov %ebx, %eax
wrmsr
/* Set CLOS selector to 0 */
mov $MSR_IA32_PQR_ASSOC, %ecx
rdmsr
and $~MSR_IA32_PQR_ASSOC_MASK, %edx /* select mask 0 */
wrmsr
/* We will need to block CAR region from evicts */
mov $MSR_L2_QOS_MASK(1), %ecx
rdmsr
/* Invert bits that are to be used for cache */
mov %ebx, %eax
xor $~0, %eax /* invert 32 bits */
/*
* Use CBM_LEN_MASK stored in mm3 to set bits based on Capacity Bit
* Mask Length.
*/
movd %mm3, %ebx
and %ebx, %eax
wrmsr
post_code(0x26)
/* Clear the cache memory region. This will also fill up the cache */
movl $CONFIG_DCACHE_RAM_BASE, %edi
movl $CONFIG_DCACHE_RAM_SIZE, %ecx
shr $0x02, %ecx
xor %eax, %eax
cld
rep stosl
post_code(0x27)
/* Cache is populated. Use mask 1 that will block evicts */
mov $MSR_IA32_PQR_ASSOC, %ecx
rdmsr
and $~MSR_IA32_PQR_ASSOC_MASK, %edx /* clear index bits first */
or $1, %edx /* select mask 1 */
wrmsr
/* Enable prefetchers */
mov $MSR_PREFETCH_CTL, %ecx
rdmsr
and $~(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax
wrmsr
post_code(0x28)
jmp car_init_ret
#elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED)
.global car_nem_enhanced
car_nem_enhanced:
/* Disable cache eviction (setup stage) */
mov $MSR_EVICT_CTL, %ecx
rdmsr
or $0x1, %eax
wrmsr
post_code(0x26)
/* Create n-way set associativity of cache */
xorl %edi, %edi
find_llc_subleaf:
movl %edi, %ecx
movl $0x04, %eax
cpuid
inc %edi
and $0xe0, %al /* EAX[7:5] = Cache Level */
cmp $0x60, %al /* Check to see if it is LLC */
jnz find_llc_subleaf
/*
* Set MSR 0xC91 IA32_L3_MASK_! = 0xE/0xFE/0xFFE/0xFFFE
* for 4/8/16 way of LLC
*/
shr $22, %ebx
inc %ebx
/* Calculate n-way associativity of LLC */
mov %bl, %cl
/*
* Maximizing RO cacheability while locking in the CAR to a
* single way since that particular way won't be victim candidate
* for evictions.
* This has been done after programing LLC_WAY_MASK_1 MSR
* with desired LLC way as mentioned below.
*
* Hence create Code and Data Size as per request
* Code Size (RO) : Up to 16M
* Data Size (RW) : Up to 256K
*/
movl $0x01, %eax
/*
* LLC Ways -> LLC_WAY_MASK_1:
* 4: 0x000E
* 8: 0x00FE
* 12: 0x0FFE
* 16: 0xFFFE
*
* These MSRs contain one bit per each way of LLC
* - If this bit is '0' - the way is protected from eviction
* - If this bit is '1' - the way is not protected from eviction
*/
shl %cl, %eax
subl $0x02, %eax
movl $MSR_IA32_L3_MASK_1, %ecx
xorl %edx, %edx
wrmsr
/*
* Set MSR 0xC92 IA32_L3_MASK_2 = 0x1
*
* For SKL SOC, data size remains 256K consistently.
* Hence, creating 1-way associative cache for Data
*/
mov $MSR_IA32_L3_MASK_2, %ecx
mov $0x01, %eax
xorl %edx, %edx
wrmsr
/*
* Set MSR_IA32_PQR_ASSOC = 0x02
*
* Possible values:
* 0: Default value, no way mask should be applied
* 1: Apply way mask 1 to LLC
* 2: Apply way mask 2 to LLC
* 3: Shouldn't be use in NEM Mode
*/
movl $MSR_IA32_PQR_ASSOC, %ecx
movl $0x02, %eax
xorl %edx, %edx
wrmsr
movl $CONFIG_DCACHE_RAM_BASE, %edi
movl $CONFIG_DCACHE_RAM_SIZE, %ecx
shr $0x02, %ecx
xor %eax, %eax
cld
rep stosl
/*
* Set MSR_IA32_PQR_ASSOC = 0x01
* At this stage we apply LLC_WAY_MASK_1 to the cache.
* i.e. way 0 is protected from eviction.
*/
movl $MSR_IA32_PQR_ASSOC, %ecx
movl $0x01, %eax
xorl %edx, %edx
wrmsr
post_code(0x27)
/*
* Enable No-Eviction Mode Run State by setting
* NO_EVICT_MODE MSR 2E0h bit [1] = '1'.
*/
movl $MSR_EVICT_CTL, %ecx
rdmsr
orl $0x02, %eax
wrmsr
post_code(0x28)
jmp car_init_ret
#endif
#if CONFIG_IS_ENABLED(X86_16BIT_INIT)
_dt_ucode_base_size:
/* These next two fields are filled in by binman */
.globl ucode_base
ucode_base: /* Declared in microcode.h */
.long 0 /* microcode base */
.globl ucode_size
ucode_size: /* Declared in microcode.h */
.long 0 /* microcode size */
.long CONFIG_SYS_MONITOR_BASE /* code region base */
.long CONFIG_SYS_MONITOR_LEN /* code region size */
#endif
arch/x86/cpu/intel_common/car2_uninit.S 0 → 100644
浏览文件 @ c0912f9b
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright 2017 Intel Corp.
* Copyright 2019 Google LLC
* Taken from coreboot file exit_car.S
*/
#include <config.h>
#include <asm/msr-index.h>
#include <asm/mtrr.h>
.text
.global car_uninit
car_uninit:
/*
* Retrieve return address from stack as it will get trashed below if
* execution is utilizing the cache-as-ram stack.
*/
pop %ebx
/* Disable MTRRs */
mov $(MTRR_DEF_TYPE_MSR), %ecx
rdmsr
and $(~(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)), %eax
wrmsr
#ifdef CONFIG_INTEL_CAR_NEM
.global car_nem_teardown
car_nem_teardown:
/* invalidate cache contents */
invd
/* Knock down bit 1 then bit 0 of NEM control not combining steps */
mov $(MSR_EVICT_CTL), %ecx
rdmsr
and $(~(1 << 1)), %eax
wrmsr
and $(~(1 << 0)), %eax
wrmsr
#elif IS_ENABLED(CONFIG_INTEL_CAR_CQOS)
.global car_cqos_teardown
car_cqos_teardown:
/* Go back to all-evicting mode, set both masks to all-1s */
mov $MSR_L2_QOS_MASK(0), %ecx
rdmsr
mov $~0, %al
wrmsr
mov $MSR_L2_QOS_MASK(1), %ecx
rdmsr
mov $~0, %al
wrmsr
/* Reset CLOS selector to 0 */
mov $MSR_IA32_PQR_ASSOC, %ecx
rdmsr
and $~MSR_IA32_PQR_ASSOC_MASK, %edx
wrmsr
#elif IS_ENABLED(CONFIG_INTEL_CAR_NEM_ENHANCED)
.global car_nem_enhanced_teardown
car_nem_enhanced_teardown:
/* invalidate cache contents */
invd
/* Knock down bit 1 then bit 0 of NEM control not combining steps */
mov $(MSR_EVICT_CTL), %ecx
rdmsr
and $(~(1 << 1)), %eax
wrmsr
and $(~(1 << 0)), %eax
wrmsr
/* Reset CLOS selector to 0 */
mov $IA32_PQR_ASSOC, %ecx
rdmsr
and $~IA32_PQR_ASSOC_MASK, %edx
wrmsr
#endif
/* Return to caller */
jmp *%ebx
arch/x86/cpu/intel_common/fast_spi.c 0 → 100644
浏览文件 @ c0912f9b
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 Google LLC
*/
#include <common.h>
#include <asm/io.h>
#include <asm/cpu_common.h>
#include <asm/fast_spi.h>
#include <asm/pci.h>
/*
* Returns bios_start and fills in size of the BIOS region.
*/
static ulong fast_spi_get_bios_region(struct fast_spi_regs *regs,
uint *bios_size)
{
ulong bios_start, bios_end;
/*
* BIOS_BFPREG provides info about BIOS-Flash Primary Region Base and
* Limit. Base and Limit fields are in units of 4K.
*/
u32 val = readl(&regs->bfp);
bios_start = (val & SPIBAR_BFPREG_PRB_MASK) << 12;
bios_end = (((val & SPIBAR_BFPREG_PRL_MASK) >>
SPIBAR_BFPREG_PRL_SHIFT) + 1) << 12;
*bios_size = bios_end - bios_start;
return bios_start;
}
int fast_spi_get_bios_mmap(pci_dev_t pdev, ulong *map_basep, uint *map_sizep,
uint *offsetp)
{
struct fast_spi_regs *regs;
ulong bar, base, mmio_base;
/* Special case to find mapping without probing the device */
pci_x86_read_config(pdev, PCI_BASE_ADDRESS_0, &bar, PCI_SIZE_32);
mmio_base = bar & PCI_BASE_ADDRESS_MEM_MASK;
regs = (struct fast_spi_regs *)mmio_base;
base = fast_spi_get_bios_region(regs, map_sizep);
*map_basep = (u32)-*map_sizep - base;
*offsetp = base;
return 0;
}
int fast_spi_early_init(pci_dev_t pdev, ulong mmio_base)
{
/* Program Temporary BAR for SPI */
pci_x86_write_config(pdev, PCI_BASE_ADDRESS_0,
mmio_base | PCI_BASE_ADDRESS_SPACE_MEMORY,
PCI_SIZE_32);
/* Enable Bus Master and MMIO Space */
pci_x86_clrset_config(pdev, PCI_COMMAND, 0, PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY, PCI_SIZE_8);
/*
* Disable the BIOS write protect so write commands are allowed.
* Enable Prefetching and caching.
*/
pci_x86_clrset_config(pdev, SPIBAR_BIOS_CONTROL,
SPIBAR_BIOS_CONTROL_EISS |
SPIBAR_BIOS_CONTROL_CACHE_DISABLE,
SPIBAR_BIOS_CONTROL_WPD |
SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE, PCI_SIZE_8);
return 0;
}
arch/x86/cpu/intel_common/lpss.c 0 → 100644
浏览文件 @ c0912f9b
// SPDX-License-Identifier: GPL-2.0
/*
* Special driver to handle of-platdata
*
* Copyright 2019 Google LLC
*
* Some code from coreboot lpss.c
*/
#include <common.h>
#include <dm.h>
#include <pci.h>
#include <asm/io.h>
#include <asm/lpss.h>
enum {
LPSS_RESET_CTL_REG = 0x204,
/*
* Bit 1:0 controls LPSS controller reset.
*
* 00 ->LPSS Host Controller is in reset (Reset Asserted)
* 01/10 ->Reserved
* 11 ->LPSS Host Controller is NOT at reset (Reset Released)
*/
LPSS_CNT_RST_RELEASE = 3,
/* Power management control and status register */
PME_CTRL_STATUS = 0x84,
/* Bit 1:0 Powerstate, controls D0 and D3 state */
POWER_STATE_MASK = 3,
};
/* Take controller out of reset */
void lpss_reset_release(void *regs)
{
writel(LPSS_CNT_RST_RELEASE, regs + LPSS_RESET_CTL_REG);
}
void lpss_set_power_state(struct udevice *dev, enum lpss_pwr_state state)
{
dm_pci_clrset_config8(dev, PME_CTRL_STATUS, POWER_STATE_MASK, state);
}
arch/x86/cpu/irq.c
浏览文件 @ c0912f9b
......@@ -350,14 +350,6 @@ int irq_router_probe(struct udevice *dev)
return 0;
}
ulong write_pirq_routing_table(ulong addr)
{
if (!gd->arch.pirq_routing_table)
return addr;
return copy_pirq_routing_table(addr, gd->arch.pirq_routing_table);
}
static const struct udevice_id irq_router_ids[] = {
{ .compatible = "intel,irq-router" },
{ }
......@@ -370,8 +362,3 @@ U_BOOT_DRIVER(irq_router_drv) = {
.probe = irq_router_probe,
.priv_auto_alloc_size = sizeof(struct irq_router),
};
UCLASS_DRIVER(irq) = {
.id = UCLASS_IRQ,
.name = "irq",
};
arch/x86/cpu/ivybridge/sdram.c
浏览文件 @ c0912f9b
......@@ -116,7 +116,7 @@ static int prepare_mrc_cache(struct pei_data *pei_data)
ret = read_seed_from_cmos(pei_data);
if (ret)
return ret;
ret = mrccache_get_region(NULL, &entry);
ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry);
if (ret)
return ret;
mrc_cache = mrccache_find_current(&entry);
......@@ -538,12 +538,14 @@ int dram_init(void)
/* S3 resume: don't save scrambler seed or MRC data */
if (pei_data->boot_mode != PEI_BOOT_RESUME) {
struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL];
/*
* This will be copied to SDRAM in reserve_arch(), then written
* to SPI flash in mrccache_save()
*/
gd->arch.mrc_output = (char *)pei_data->mrc_output;
gd->arch.mrc_output_len = pei_data->mrc_output_len;
mrc->buf = (char *)pei_data->mrc_output;
mrc->len = pei_data->mrc_output_len;
ret = write_seeds_to_cmos(pei_data);
if (ret)
debug("Failed to write seeds to CMOS: %d\n", ret);
......
arch/x86/cpu/mp_init.c
浏览文件 @ c0912f9b
......@@ -418,69 +418,6 @@ static int init_bsp(struct udevice **devp)
return 0;
}
#ifdef CONFIG_QFW
static int qemu_cpu_fixup(void)
{
int ret;
int cpu_num;
int cpu_online;
struct udevice *dev, *pdev;
struct cpu_platdata *plat;
char *cpu;
/* first we need to find '/cpus' */
for (device_find_first_child(dm_root(), &pdev);
pdev;
device_find_next_child(&pdev)) {
if (!strcmp(pdev->name, "cpus"))
break;
}
if (!pdev) {
printf("unable to find cpus device\n");
return -ENODEV;
}
/* calculate cpus that are already bound */
cpu_num = 0;
for (uclass_find_first_device(UCLASS_CPU, &dev);
dev;
uclass_find_next_device(&dev)) {
cpu_num++;
}
/* get actual cpu number */
cpu_online = qemu_fwcfg_online_cpus();
if (cpu_online < 0) {
printf("unable to get online cpu number: %d\n", cpu_online);
return cpu_online;
}
/* bind addtional cpus */
dev = NULL;
for (; cpu_num < cpu_online; cpu_num++) {
/*
* allocate device name here as device_bind_driver() does
* not copy device name, 8 bytes are enough for
* sizeof("cpu@") + 3 digits cpu number + '\0'
*/
cpu = malloc(8);
if (!cpu) {
printf("unable to allocate device name\n");
return -ENOMEM;
}
sprintf(cpu, "cpu@%d", cpu_num);
ret = device_bind_driver(pdev, "cpu_qemu", cpu, &dev);
if (ret) {
printf("binding cpu@%d failed: %d\n", cpu_num, ret);
return ret;
}
plat = dev_get_parent_platdata(dev);
plat->cpu_id = cpu_num;
}
return 0;
}
#endif
int mp_init(struct mp_params *p)
{
int num_aps;
......@@ -494,11 +431,11 @@ int mp_init(struct mp_params *p)
if (ret)
return ret;
#ifdef CONFIG_QFW
ret = qemu_cpu_fixup();
if (ret)
return ret;
#endif
if (IS_ENABLED(CONFIG_QFW)) {
ret = qemu_cpu_fixup();
if (ret)
return ret;
}
ret = init_bsp(&cpu);
if (ret) {
......
arch/x86/cpu/qfw_cpu.c 0 → 100644
浏览文件 @ c0912f9b
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015 Google, Inc
*/
#include <common.h>
#include <cpu.h>
#include <dm.h>
#include <qfw.h>
#include <dm/lists.h>
#include <dm/uclass-internal.h>
#include <dm/root.h>
int qemu_cpu_fixup(void)
{
int ret;
int cpu_num;
int cpu_online;
struct udevice *dev, *pdev;
struct cpu_platdata *plat;
char *cpu;
/* first we need to find '/cpus' */
for (device_find_first_child(dm_root(), &pdev);
pdev;
device_find_next_child(&pdev)) {
if (!strcmp(pdev->name, "cpus"))
break;
}
if (!pdev) {
printf("unable to find cpus device\n");
return -ENODEV;
}
/* calculate cpus that are already bound */
cpu_num = 0;
for (uclass_find_first_device(UCLASS_CPU, &dev);
dev;
uclass_find_next_device(&dev)) {
cpu_num++;
}
/* get actual cpu number */
cpu_online = qemu_fwcfg_online_cpus();
if (cpu_online < 0) {
printf("unable to get online cpu number: %d\n", cpu_online);
return cpu_online;
}
/* bind addtional cpus */
dev = NULL;
for (; cpu_num < cpu_online; cpu_num++) {
/*
* allocate device name here as device_bind_driver() does
* not copy device name, 8 bytes are enough for
* sizeof("cpu@") + 3 digits cpu number + '\0'
*/
cpu = malloc(8);
if (!cpu) {
printf("unable to allocate device name\n");
return -ENOMEM;
}
sprintf(cpu, "cpu@%d", cpu_num);
ret = device_bind_driver(pdev, "cpu_qemu", cpu, &dev);
if (ret) {
printf("binding cpu@%d failed: %d\n", cpu_num, ret);
return ret;
}
plat = dev_get_parent_platdata(dev);
plat->cpu_id = cpu_num;
}
return 0;
}
arch/x86/cpu/quark/dram.c
浏览文件 @ c0912f9b
......@@ -24,7 +24,7 @@ static __maybe_unused int prepare_mrc_cache(struct mrc_params *mrc_params)
struct mrc_region entry;
int ret;
ret = mrccache_get_region(NULL, &entry);
ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry);
if (ret)
return ret;
......@@ -154,9 +154,11 @@ int dram_init(void)
#ifdef CONFIG_ENABLE_MRC_CACHE
cache = malloc(sizeof(struct mrc_timings));
if (cache) {
struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL];
memcpy(cache, &mrc_params.timings, sizeof(struct mrc_timings));
gd->arch.mrc_output = cache;
gd->arch.mrc_output_len = sizeof(struct mrc_timings);
mrc->buf = cache;
mrc->len = sizeof(struct mrc_timings);
}
#endif
......
arch/x86/cpu/slimbootloader/Kconfig
浏览文件 @ c0912f9b
......@@ -17,3 +17,4 @@ config SYS_SLIMBOOTLOADER
imply USB_EHCI_HCD
imply USB_XHCI_HCD
imply E1000
imply X86_TSC_READ_BASE
arch/x86/cpu/u-boot-spl.lds
浏览文件 @ c0912f9b
......@@ -17,7 +17,10 @@ SECTIONS
. = IMAGE_TEXT_BASE; /* Location of bootcode in flash */
__text_start = .;
.text : { *(.text*); }
.text : {
__image_copy_start = .;
*(.text*);
}
. = ALIGN(4);
......
arch/x86/dts/Makefile
浏览文件 @ c0912f9b
......@@ -2,6 +2,7 @@
dtb-y += bayleybay.dtb \
cherryhill.dtb \
chromebook_coral.dtb \
chromebook_link.dtb \
chromebox_panther.dtb \
chromebook_samus.dtb \
......
arch/x86/dts/chromebook_coral.dts 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/dts/u-boot.dtsi
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/include/asm/arch-apollolake/cpu.h 0 → 100644
浏览文件 @ c0912f9b
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright 2019 Google LLC
*/
#ifndef _ASM_ARCH_CPU_H
#define _ASM_ARCH_CPU_H
/* Common Timer Copy (CTC) frequency - 19.2MHz */
#define CTC_FREQ 19200000
#define MAX_PCIE_PORTS 6
#define CLKREQ_DISABLED 0xf
#ifndef __ASSEMBLY__
/* Flush L1D to L2 */
void cpu_flush_l1d_to_l2(void);
#endif
#endif /* _ASM_ARCH_CPU_H */
arch/x86/include/asm/arch-apollolake/fsp/fsp_configs.h 0 → 100644
浏览文件 @ c0912f9b
/* SPDX-License-Identifier: Intel */
/*
* Copyright 2019 Google LLC
*/
#ifndef __FSP_CONFIGS_H__
#define __FSP_CONFIGS_H__
#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */
#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */
#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */
#define VBT_SIGNATURE 0x54425624
#endif
arch/x86/include/asm/arch-apollolake/fsp/fsp_m_upd.h 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/include/asm/arch-apollolake/fsp/fsp_s_upd.h 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/include/asm/arch-apollolake/fsp/fsp_vpd.h 0 → 100644
浏览文件 @ c0912f9b
/* SPDX-License-Identifier: Intel */
/*
* Copyright 2019 Google LLC
*/
#ifndef __FSP_VPD_H
#define __FSP_VPD_H
/* Nothing to declare here for FSP2 */
#endif
arch/x86/include/asm/arch-apollolake/gpio.h 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/include/asm/arch-apollolake/iomap.h 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/include/asm/arch-apollolake/itss.h 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/include/asm/arch-apollolake/lpc.h 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/include/asm/arch-apollolake/pch.h 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/include/asm/arch-apollolake/pm.h 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/include/asm/arch-apollolake/systemagent.h 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/include/asm/arch-apollolake/uart.h 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/include/asm/fast_spi.h 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/include/asm/fsp/fsp_api.h 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/include/asm/fsp1/fsp_api.h
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/include/asm/fsp2/fsp_api.h 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/include/asm/fsp2/fsp_internal.h 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/include/asm/global_data.h
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/include/asm/intel_pinctrl.h 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/include/asm/intel_pinctrl_defs.h 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/include/asm/lpss.h 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/include/asm/mrccache.h
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/include/asm/msr-index.h
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/include/asm/processor.h
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/include/asm/spl.h
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/lib/Makefile
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/lib/fsp/Makefile
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/lib/fsp/fsp_common.c
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/lib/fsp/fsp_dram.c
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/lib/fsp/fsp_support.c
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/lib/fsp1/Makefile
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/lib/fsp1/fsp_common.c
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/lib/fsp1/fsp_dram.c
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/lib/fsp2/Makefile 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/lib/fsp2/fsp_common.c 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/lib/fsp2/fsp_dram.c 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/lib/fsp2/fsp_init.c 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/lib/fsp2/fsp_meminit.c 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/lib/fsp2/fsp_silicon_init.c 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/lib/fsp2/fsp_support.c 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/lib/mrccache.c
浏览文件 @ c0912f9b
此差异已折叠。
arch/x86/lib/pirq_routing.c
浏览文件 @ c0912f9b
此差异已折叠。
board/gateworks/gw_ventana/Kconfig
浏览文件 @ c0912f9b
此差异已折叠。
board/google/Kconfig
浏览文件 @ c0912f9b
此差异已折叠。
board/google/chromebook_coral/Kconfig 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
board/google/chromebook_coral/MAINTAINERS 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
board/google/chromebook_coral/Makefile 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
board/google/chromebook_coral/coral.c 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
cmd/Kconfig
浏览文件 @ c0912f9b
此差异已折叠。
cmd/Makefile
浏览文件 @ c0912f9b
此差异已折叠。
cmd/pmc.c 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
cmd/x86/fsp.c
浏览文件 @ c0912f9b
此差异已折叠。
common/board_r.c
浏览文件 @ c0912f9b
此差异已折叠。
common/spl/spl.c
浏览文件 @ c0912f9b
此差异已折叠。
configs/chromebook_coral_defconfig 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
configs/omap35_logic_defconfig
浏览文件 @ c0912f9b
此差异已折叠。
configs/qemu-x86_64_defconfig
浏览文件 @ c0912f9b
此差异已折叠。
configs/sandbox64_defconfig
浏览文件 @ c0912f9b
此差异已折叠。
configs/sandbox_defconfig
浏览文件 @ c0912f9b
此差异已折叠。
configs/sandbox_flattree_defconfig
浏览文件 @ c0912f9b
此差异已折叠。
configs/sandbox_spl_defconfig
浏览文件 @ c0912f9b
此差异已折叠。
configs/tools-only_defconfig
浏览文件 @ c0912f9b
此差异已折叠。
doc/board/google/chromebook_coral.rst 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
doc/board/google/index.rst
浏览文件 @ c0912f9b
此差异已折叠。
doc/device-tree-bindings/gpio/intel,apl-gpio.txt 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
doc/device-tree-bindings/pci/x86-pci.txt 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
doc/device-tree-bindings/pinctrl/intel,apl-pinctrl.txt 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
doc/driver-model/of-plat.rst
浏览文件 @ c0912f9b
此差异已折叠。
drivers/Makefile
浏览文件 @ c0912f9b
此差异已折叠。
drivers/core/util.c
浏览文件 @ c0912f9b
此差异已折叠。
drivers/gpio/Kconfig
浏览文件 @ c0912f9b
此差异已折叠。
drivers/gpio/Makefile
浏览文件 @ c0912f9b
此差异已折叠。
drivers/gpio/at91_gpio.c
浏览文件 @ c0912f9b
此差异已折叠。
drivers/gpio/atmel_pio4.c
浏览文件 @ c0912f9b
此差异已折叠。
drivers/gpio/da8xx_gpio.c
浏览文件 @ c0912f9b
此差异已折叠。
drivers/gpio/da8xx_gpio.h
浏览文件 @ c0912f9b
此差异已折叠。
drivers/gpio/intel_gpio.c 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
drivers/gpio/mxc_gpio.c
浏览文件 @ c0912f9b
此差异已折叠。
drivers/gpio/mxs_gpio.c
浏览文件 @ c0912f9b
此差异已折叠。
drivers/gpio/omap_gpio.c
浏览文件 @ c0912f9b
此差异已折叠。
drivers/gpio/sunxi_gpio.c
浏览文件 @ c0912f9b
此差异已折叠。
drivers/i2c/Makefile
浏览文件 @ c0912f9b
此差异已折叠。
drivers/i2c/designware_i2c.c
浏览文件 @ c0912f9b
此差异已折叠。
drivers/i2c/designware_i2c.h
浏览文件 @ c0912f9b
此差异已折叠。
drivers/i2c/designware_i2c_pci.c 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
drivers/i2c/i2c-uclass.c
浏览文件 @ c0912f9b
此差异已折叠。
drivers/i2c/muxes/pca954x.c
浏览文件 @ c0912f9b
此差异已折叠。
drivers/misc/Kconfig
浏览文件 @ c0912f9b
此差异已折叠。
drivers/misc/Makefile
浏览文件 @ c0912f9b
此差异已折叠。
drivers/misc/irq-uclass.c 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
drivers/misc/irq_sandbox.c 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
drivers/misc/p2sb-uclass.c 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
drivers/misc/p2sb_emul.c 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
drivers/misc/p2sb_sandbox.c 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
drivers/misc/sandbox_adder.c 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
drivers/mmc/fsl_esdhc_imx.c
浏览文件 @ c0912f9b
此差异已折叠。
drivers/mmc/omap_hsmmc.c
浏览文件 @ c0912f9b
此差异已折叠。
drivers/mtd/spi/sf_probe.c
浏览文件 @ c0912f9b
此差异已折叠。
drivers/net/designware.c
浏览文件 @ c0912f9b
此差异已折叠。
drivers/net/designware.h
浏览文件 @ c0912f9b
此差异已折叠。
drivers/net/fec_mxc.c
浏览文件 @ c0912f9b
此差异已折叠。
drivers/net/fec_mxc.h
浏览文件 @ c0912f9b
此差异已折叠。
drivers/net/mvneta.c
浏览文件 @ c0912f9b
此差异已折叠。
drivers/net/mvpp2.c
浏览文件 @ c0912f9b
此差异已折叠。
drivers/net/sun8i_emac.c
浏览文件 @ c0912f9b
此差异已折叠。
drivers/pch/Kconfig
浏览文件 @ c0912f9b
此差异已折叠。
drivers/pch/Makefile
浏览文件 @ c0912f9b
此差异已折叠。
drivers/pci/pci-aardvark.c
浏览文件 @ c0912f9b
此差异已折叠。
drivers/pci/pci-uclass.c
浏览文件 @ c0912f9b
此差异已折叠。
drivers/pci/pcie_dw_mvebu.c
浏览文件 @ c0912f9b
此差异已折叠。
drivers/pinctrl/Kconfig
浏览文件 @ c0912f9b
此差异已折叠。
drivers/pinctrl/Makefile
浏览文件 @ c0912f9b
此差异已折叠。
drivers/pinctrl/intel/Kconfig 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
drivers/pinctrl/intel/Makefile 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
drivers/pinctrl/intel/pinctrl.c 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
drivers/pinctrl/intel/pinctrl_apl.c 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
drivers/power/Kconfig
浏览文件 @ c0912f9b
此差异已折叠。
drivers/power/acpi_pmc/Kconfig 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
drivers/power/acpi_pmc/Makefile 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
drivers/power/acpi_pmc/acpi-pmc-uclass.c 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
drivers/power/acpi_pmc/pmc_emul.c 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
drivers/power/acpi_pmc/sandbox.c 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
drivers/spi/Kconfig
浏览文件 @ c0912f9b
此差异已折叠。
drivers/spi/atmel_spi.c
浏览文件 @ c0912f9b
此差异已折叠。
drivers/spi/designware_spi.c
浏览文件 @ c0912f9b
此差异已折叠。
drivers/spi/ich.c
浏览文件 @ c0912f9b
此差异已折叠。
drivers/spi/ich.h
浏览文件 @ c0912f9b
此差异已折叠。
drivers/spi/spi-uclass.c
浏览文件 @ c0912f9b
此差异已折叠。
drivers/timer/Kconfig
浏览文件 @ c0912f9b
此差异已折叠。
drivers/timer/tsc_timer.c
浏览文件 @ c0912f9b
此差异已折叠。
drivers/tpm/tpm2_tis_spi.c
浏览文件 @ c0912f9b
此差异已折叠。
include/binman.h 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
include/bootstage.h
浏览文件 @ c0912f9b
此差异已折叠。
include/config_uncmd_spl.h
浏览文件 @ c0912f9b
此差异已折叠。
include/configs/at91-sama5_common.h
浏览文件 @ c0912f9b
此差异已折叠。
include/configs/chromebook_coral.h 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
include/configs/gw_ventana.h
浏览文件 @ c0912f9b
此差异已折叠。
include/configs/mx6ul_14x14_evk.h
浏览文件 @ c0912f9b
此差异已折叠。
include/dm/ofnode.h
浏览文件 @ c0912f9b
此差异已折叠。
include/dm/pci.h 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
include/dm/uclass-id.h
浏览文件 @ c0912f9b
此差异已折叠。
include/init.h
浏览文件 @ c0912f9b
此差异已折叠。
include/irq.h 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
include/p2sb.h 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
include/pci.h
浏览文件 @ c0912f9b
此差异已折叠。
include/power/acpi_pmc.h 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
include/qfw.h
浏览文件 @ c0912f9b
此差异已折叠。
include/spi.h
浏览文件 @ c0912f9b
此差异已折叠。
include/spi_flash.h
浏览文件 @ c0912f9b
此差异已折叠。
include/spl.h
浏览文件 @ c0912f9b
此差异已折叠。
lib/Kconfig
浏览文件 @ c0912f9b
此差异已折叠。
lib/Makefile
浏览文件 @ c0912f9b
此差异已折叠。
lib/binman.c 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
lib/efi/Kconfig
浏览文件 @ c0912f9b
此差异已折叠。
lib/net_utils.c
浏览文件 @ c0912f9b
此差异已折叠。
net/Makefile
浏览文件 @ c0912f9b
此差异已折叠。
net/checksum.c 已删除 100644 → 0
浏览文件 @ 533c9f57
此差异已折叠。
scripts/Makefile.lib
浏览文件 @ c0912f9b
此差异已折叠。
scripts/Makefile.uncmd_spl
浏览文件 @ c0912f9b
此差异已折叠。
test/dm/Makefile
浏览文件 @ c0912f9b
此差异已折叠。
test/dm/irq.c 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
test/dm/p2sb.c 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
test/dm/pmc.c 0 → 100644
浏览文件 @ c0912f9b
此差异已折叠。
Markdown is supported
0% 或 .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑！
想要评论请 注册 或