- 18 12月, 2015 16 次提交
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由 Michal Simek 提交于
Enable DM for the whole architecture. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
LL_TEMAC is available at big endian MB and it is not properly tested that's why the patch removes it. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Clean board specific file. Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Michal Simek 提交于
Create space below u-boot binary for early malloc. It means memory layout is stack grows down, space for early malloc, u-boot code. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
All ethernet operation needs to be updated for architectures which requires MANUAL_RELOC. Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Michal Simek 提交于
Clear driver dependecies via Kconfig. Remove PHYLIB dependency from the driver. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Michal Simek 提交于
Use core to call net_process_received_packet() instead of call inside the driver. Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Michal Simek 提交于
recv function should return 0 instead of frame_len not to proceed the same packet again in core. Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Michal Simek 提交于
Undefined phy address is -1 not 0. Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Nathan Rossi 提交于
Update the ZYBO device tree and enable config options that relate to the added devices in the device tree. Signed-off-by: NNathan Rossi <nathan@nathanrossi.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michal Simek <monstr@monstr.eu> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Nathan Rossi 提交于
When the Zynq Boot ROM code loads the payload from QSPI it uses the LQSPI feature of the QSPI device, however it does not clean up its configuration before handing over to the payload which leaves the device confgured to by-pass the standard non-linear operating mode. This ensures the Linear QSPI mode is disabled before re-enabling the device. Signed-off-by: NNathan Rossi <nathan@nathanrossi.com> Cc: Jagan Teki <jteki@openedev.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Nathan Rossi 提交于
Clean up the param checking, removing some code paths that will never happen. Signed-off-by: NNathan Rossi <nathan@nathanrossi.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Tom Rini <trini@konsulko.com> Reported-by: Coverity (CID 133251) Reviewed-by: NTom Rini <trini@konsulko.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Nathan Rossi 提交于
Add ps7_init_gpl.c/h for the ZYBO board. This instance of the ps7_init is generated by the Vivado 2015.3 tools using the system configuration provided by Digilent located on their website. Update the kconfig so that the defconfig is not overrided to use the custom init ps7_init_gpl target by default. Signed-off-by: NNathan Rossi <nathan@nathanrossi.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michal Simek <monstr@monstr.eu> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Enable u-boot,dm-pre-reloc for sdhci for zc706, zed and zybo. And create aliases for it. Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 17 12月, 2015 9 次提交
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由 Shaohui Xie 提交于
We don't disable unused FM1-DTSEC1 MAC node in FMAN v2 since it is used by MDIO. For FMAN v3, MDIO uses dedicated controller, so we can disable unused FM1-DTSEC1 MAC node to avoid being probed in Linux. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> [York Sun: revised commit message] Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Mingkai Hu 提交于
Change RCW for SD boot and NAND boot. Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Mingkai Hu 提交于
Change RCW for SD boot and NAND boot. Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Mingkai Hu 提交于
Consecutive write transactions from core to PCI express outbound path hangs after 25 to 30 transactions depending on core freq. This erratum enable the mbist clock through COP register setting. Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Mingkai Hu 提交于
Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Mingkai Hu 提交于
Remove verbose message for FMan port. Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com> [York Sun: Added commit message] Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Stuart Yoder 提交于
The MC version numbers provide no meaningful information about binary interface compatibility, so remove the check which refuses to start the MC unless a specific version is found. Version checking is supposed to be done at the individual object level, and individual drivers are responsible for their own version checking. Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com> Acked-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 16 12月, 2015 2 次提交
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由 Alexey Brodkin 提交于
This fixes commit 1a37889b: ----------------------->8-------------------- eeprom: Pull out the RW loop Unify the code for doing read/write into single function, since the code for both the read and write is almost identical. This again trims down the code duplication. ----------------------->8-------------------- where the same one routine is utilized for both EEPROM writing and reading. The only difference was supposed to be a "read" flag which in both cases was set with 1 somehow. That lead to a missing delay in case of writing which lead to write failure (in my case no data was written). Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com> Acked-by: NMarek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Cc: Heiko Schocher <hs@denx.de>
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由 York Sun 提交于
This reverts commit e8f954a7, which causes compiling errors on 32-bit hosts. Acked-by: NAneesh Bansal <aneesh.bansal@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com>
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- 15 12月, 2015 13 次提交
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由 Tang Yuantian 提交于
Freescale ARM-based Layerscape contains a SATA controller which comply with the serial ATA 3.0 specification and the AHCI 1.3 specification. This patch adds SATA feature on ls2080aqds, ls2080ardb and ls1043aqds boards. Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Aneesh Bansal 提交于
For Setting and clearing the bits in SEC Block registers sec_clrbits32() and sec_setbits32() are used which work as per endianness of CAAM block. So these must be used with SEC register address as argument. If the value is read in a local variable, then the functions will not behave correctly where endianness of CAAM and core is different. Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com> CC: Alex Porosanu <alexandru.porosanu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Aneesh Bansal 提交于
LS1043ARDB Secure Boot Target from NOR has been added. - Configs defined to enable esbc_validate. - ESBC Address in header is made 64 bit. - SMMU is re-configured in Bypass mode. Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Aneesh Bansal 提交于
uintptr_t which is a typdef for unsigned long is needed for creating pointers (32 or 64 bit depending on Core) from 32 bit variables storing the address. If a 32 bit variable (u32) is typecasted to a pointer (void *), compiler gives a warning in case size of pointer on the core is 64 bit. The typdef has been moved from include/compiler.h to include/linux/types.h Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Aneesh Bansal 提交于
For LS1043, SEC read/writes are made snoopable by setting the corresponding bits in SCFG to avoid coherency issues. Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Aneesh Bansal 提交于
usec2ticks() function has been defined for ARMv8 which will be used by SEC Driver. Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 Alexander Stein 提交于
When reading a large blob. e.g. a linux kernel (several MiBs) a watchdog timeout might occur meanwhile. So pet the watchdog while operating on the flash. Signed-off-by: NAlexander Stein <alexander.stein@systec-electronic.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
MC and debug server are not board-specific. Move reserving memory to SoC file, using the new board_reserve_ram_top function. Reduce debug server memory by 2MB to make room for secure memory. In the system with MC and debug server, the top of u-boot memory is not the end of memory. PRAM is not used for this reservation. Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
As the name may be confusing, the CONFIG_SYS_MEM_TOP_HIDE reserves some memory from the end of ram, tracked by gd->ram_size. It is not always the top of u-boot visible memory. Rewrite the macro with a weak function to provide flexibility for complex calcuation. Legacy use of this macro is still supported. Signed-off-by: NYork Sun <yorksun@freescale.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 York Sun 提交于
DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 York Sun 提交于
Secure memory is at the end of memory, separated and reserved from OS, tracked by gd->secure_ram. Secure memory can host MMU tables, security monitor, etc. This is different from PRAM used to reserve private memory. PRAM offers memory at the top of u-boot memory, not necessarily the real end of memory for systems with very large DDR. Using the end of memory simplifies MMU setup and avoid memory fragmentation. "bdinfo" command shows gd->secure_ram value if this memory is marked as secured. Signed-off-by: NYork Sun <yorksun@freescale.com>
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由 Yao Yuan 提交于
As the errata A008336 and A008514 do not apply to all LS series SoCs (such as LS1021A, LS1043A) we move them to an soc specific file Signed-off-by: NYuan Yao <yao.yuan@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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