- 20 8月, 2013 1 次提交
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由 Matthias Fuchs 提交于
This patch removes support for the APM 405CR CPU. This CPU is EOL and no board uses this chip. Signed-off-by: NMatthias Fuchs <matthias.fuchs@esd.eu>
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- 24 7月, 2013 1 次提交
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: NTom Rini <trini@ti.com>
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- 12 5月, 2011 1 次提交
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由 Steven A. Falco 提交于
APM errata CHIP_21 for the 405EX/EXr (from the rev 1.09 document dated 4/27/11) states that rev D processors may wake up with the wrong feature set. This patch implements the APM-proposed workaround. To enable this patch for your board, add the appropriate define for your CPU to your board header file. See kilauea.h for more information. The following variants are supported: #define CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EXr_NO_SECURITY #define CONFIG_SYS_4xx_CHIP_21_405EXr_SECURITY Please note that if you select the wrong define, your board will not boot, and JTAG will be required to recover. Tested on custom boards using: CONFIG_SYS_4xx_CHIP_21_405EX_NO_SECURITY <sfalco@harris.com> CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY <eibach@gdsys.de> Signed-off-by: NSteve Falco <sfalco@harris.com> Acked-by: NDirk Eibach <eibach@gdsys.de> Signed-off-by: NStefan Roese <sr@denx.de>
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- 20 10月, 2010 1 次提交
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由 Stefan Roese 提交于
Remove uneccessary functions to access the TCR/TSR registers as well. Signed-off-by: NStefan Roese <sr@denx.de>
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- 04 10月, 2010 1 次提交
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由 Tirumala Marri 提交于
APM821XX is a new line of SoCs which are derivatives of PPC44X family of processors. This patch adds support of CPU, cache, tlb, 32k ocm, bootstraps, PLB and AHB bus. Signed-off-by: NTirumala R Marri <tmarri@apm.com> Signed-off-by: NStefan Roese <sr@denx.de>
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- 23 9月, 2010 4 次提交
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由 Stefan Roese 提交于
This cleanup is done by creating header files for all SoC versions and moving the SoC specific defines into these special headers. This way the common header ppc405.h and ppc440.h can be cleaned up finally. As a part from this cleanup, the GPIO definitions for PPC405EP are corrected. The high and low parts of the registers (for example CONFIG_SYS_GPIO0_OSRL vs. CONFIG_SYS_GPIO0_OSRH) have been defined in the wrong order. This patch now fixes this issue by switching these xxxH and xxxL values. This brings the GPIO 405EP port in sync with all other PPC4xx ports. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
This patch starts a bit PPC4xx header cleanup. First patch mostly touches PPC440 files. A later patch will touch the PPC405 files as well. This cleanup is done by creating header files for all SoC versions and moving the SoC specific defines into these special headers. This way the common header ppc405.h and ppc440.h can be cleaned up finally. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
This patch moves some ppc4xx related headers from the common include directory (include/) to the powerpc specific one (arch/powerpc/include/asm/). This way to common include directory is not so cluttered with files. Signed-off-by: NStefan Roese <sr@denx.de>
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- 03 9月, 2010 1 次提交
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由 Stefan Roese 提交于
This patch fixes a bug in reconfigure_pll(), where the detection of the current bootstrap option is wrong. The ICS bits where incorrectly shifted. This bug was found on the lwmon5 board, which uses bootstrap option H (I2C bootstrap EEPROM). Additionally a bit of code was moved into the if statement, since its only used after later on. No need to run this code all the time. Also, a few empty lines are added to make the code better readable. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Rupjyoti Sarmah <rsarmah@amcc.com> Cc: Victor Gallardo <vgallardo@appliedmicro.com>
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- 01 7月, 2010 1 次提交
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由 Stefan Roese 提交于
This patch enables booting with option E on the PPC460EX/EXr/GT. When booting with Option E, the PLL is in bypass, CPR0_PLLC[ENG]=0. The Software Boot Configuration Procedure is needed to engage the PLL and perform a chip reset. Signed-off-by: NStefan Roese <sr@denx.de>
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- 22 4月, 2010 1 次提交
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由 Stefan Roese 提交于
As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NWolfgang Denk <wd@denx.de> Acked-by: NDetlev Zundel <dzu@denx.de> Acked-by: NKim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
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- 13 4月, 2010 1 次提交
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由 Peter Tyser 提交于
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
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- 24 3月, 2010 1 次提交
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由 Rupjyoti Sarmah 提交于
440EPx fixed bootstrap options A, B, D, and E sets PLL FWDVA to a value = 1. This results in the PLLOUTB being greater than the CPU clock frequency resulting unstable 440EPx operation resulting in various software hang conditions. This patch reprograms the FWDVA satisfying the requirement of setting FWDVB to a value greater than 1 while using one of the four deafult bootstrap options. Signed-off-by: NRupjyoti Sarmah <rsarmah@amcc.com> Acked-by : Victor Gallardo <vgallardo@appliedmicro.com> Signed-off-by: NStefan Roese <sr@denx.de>
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- 23 10月, 2009 1 次提交
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由 Stefan Roese 提交于
PPC440EP(x)/PPC440GR(x): In asynchronous PCI mode, the synchronous PCI clock must meet certain requirements. The following equation describes the relationship that must be maintained between the asynchronous PCI clock and synchronous PCI clock. Select an appropriate PCI:PLB ratio to maintain the relationship: AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz This patch now adds a function to check and reconfigure the sync PCI clock to meet this requirement. This is in preparation for some AMCC boards (Sequoia/Rainier and Yosemite/Yellowstone) using this function to not violate the PCI clocking rules. Signed-off-by: NStefan Roese <sr@denx.de>
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- 07 10月, 2009 1 次提交
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由 Niklaus Giger 提交于
Modify all existing *.c files to use the new register names as seen in the AMCC manuals. Signed-off-by: NNiklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: NStefan Roese <sr@denx.de>
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- 03 10月, 2009 1 次提交
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由 Stefan Roese 提交于
This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: NStefan Roese <sr@denx.de>
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- 11 9月, 2009 1 次提交
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由 Stefan Roese 提交于
This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: NStefan Roese <sr@denx.de>
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- 24 7月, 2009 1 次提交
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由 Matthias Fuchs 提交于
Signed-off-by: NMatthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: NStefan Roese <sr@denx.de>
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- 10 7月, 2009 1 次提交
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由 Matthias Fuchs 提交于
This patch moves some basic PCI initialisation from the 4xx cpu_init_f() to cpu/ppc4xx/4xx_pci.c. The original cpu_init_f() function enabled the 405EP's internal arbiter in all situations. Also the HCE bit in cpc0_pci is always set. The first is not really wanted for PCI adapter designs and the latter is a general bug for PCI adapter U-Boots. Because it enables PCI configuration by the system CPU even when the PCI configuration has not been setup by the 405EP. The one and only correct place is in pci_405gp_init() (see "Set HCE bit" comment). So for compatibility reasons the arbiter is still enabled in any case, but from weak pci_pre_init() so that it can be replaced by board specific code. Signed-off-by: NMatthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: NStefan Roese <sr@denx.de>
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- 21 3月, 2009 2 次提交
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由 Stefan Roese 提交于
Remove this code. It's not needed. The 4xx EMAC driver stores the MAC addresses into the SoC registers instead. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Mike Frysinger 提交于
The environment is the canonical storage location of the mac address, so we're killing off the global data location and moving everything to querying the env directly. The cpus that get converted here: at91rm9200 mpc512x mpc5xxx mpc8260 mpc8xx ppc4xx Signed-off-by: NMike Frysinger <vapier@gentoo.org> CC: Ben Warren <biggerbadderben@gmail.com> CC: John Rigby <jrigby@freescale.com> CC: Stefan Roese <sr@denx.de>
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- 19 10月, 2008 1 次提交
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Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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- 21 8月, 2008 2 次提交
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由 Stefan Roese 提交于
This patch fixes some minor issues introduced with the patch: ppc4xx: Optimize PLB4 Arbiter... from Prodyut Hazarika: - Rework memory-queue and PLB arbiter optimization code, that the local variable is not needed anymore. This removes one #ifdef. - Use consistant spacing in ppc4xx.h header (XXX + 0x01 instead of XXX+ 0x01). This was not introduced by Prodyut, just a copy-paste problem. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Prodyut Hazarika 提交于
PPC405EX and PPC460EX/GT/SX - Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX processors - Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared across processors (405 and 440/460) - Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX processors - Add register bit definitions for Memory Queue Configuration registers Signed-off-by: NProdyut Hazarika <phazarika@amcc.com> Signed-off-by: NStefan Roese <sr@denx.de>
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- 11 7月, 2008 1 次提交
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由 Stefan Roese 提交于
This patch reworks the 440GX interrupt handling so that the common 4xx code can be used. The 440GX is an exception to all other 4xx variants by having the cascading interrupt vectors not on UIC0 but on a special UIC named UICB0 (UIC Base 0). With this patch now, U-Boot references the 440GX UICB0 when UIC0 is selected. And the common 4xx interrupt handling is simpler without any 440GX special cases. Also some additional cleanup to cpu/ppc4xx/interrupt.c is done. Signed-off-by: NStefan Roese <sr@denx.de>
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- 30 6月, 2008 1 次提交
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由 Stefan Roese 提交于
This patch implements a fix provided by AMCC so that the lockup upon simultanious traffic on AHB USB OTG, USB 2.0 and SATA doesn't occur anymore: Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA. This errata is not officially available yet. I'll update the comment to add the errata number later. Signed-off-by: NStefan Roese <sr@denx.de>
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- 04 6月, 2008 1 次提交
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由 Grant Erickson 提交于
This patch (Part 1 of 2): * Rolls up a suite of changes to enable correct primordial stack and global data handling when the data cache is used for such a purpose for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS). * Related to the first, unifies DDR2 SDRAM and ECC initialization by eliminating redundant ECC initialization implementations and moving redundant SDRAM initialization out of board code into shared 4xx code. * Enables MCSR visibility on the 405EX(r). * Enables the use of the data cache for initial RAM on both AMCC's Kilauea and Makalu and removes a redundant CFG_POST_MEMORY flag from each board's CONFIG_POST value. - Removed, per Stefan Roese's request, defunct memory.c file for Makalu and rolled sdram_init from it into makalu.c. With respect to the 4xx DDR initialization and ECC unification, there is certainly more work that can and should be done (file renaming, etc.). However, that can be handled at a later date on a second or third pass. As it stands, this patch moves things forward in an incremental yet positive way for those platforms that utilize this code and the features associated with it. Signed-off-by: NGrant Erickson <gerickson@nuovations.com> Signed-off-by: NStefan Roese <sr@denx.de>
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- 27 3月, 2008 2 次提交
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由 Markus Brunner 提交于
This bug was introduced with commit aee747f1 which enabled CFG_4xx_GPIO_TABLE for PPC405 and unintentionally disabled the setting of the emac noise filter bits for PPC405EP when CFG_4xx_GPIO_TABLE is set. Signed-off-by: NMarkus Brunner <super.firetwister@gmail.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Mike Nuss 提交于
On PPC440EPx without a bootstrap I2C EEPROM, the PLL can be reconfigured after startup to change the speed of the clocks. This patch adds the option CFG_PLL_RECONFIG. If this option is set to 667, the CPU initialization code will reconfigure the PLL to run the system with a CPU frequency of 667MHz and PLB frequency of 166MHz, without the need for an external EEPROM. Signed-off-by: NMike Nuss <mike@terascala.com> Acked-by: NStefan Roese <sr@denx.de>
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- 15 3月, 2008 1 次提交
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由 Stefan Roese 提交于
This patch adds basic support for the AMCC 460EX/460GT PPC's. Signed-off-by: NStefan Roese <sr@denx.de>
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- 28 12月, 2007 2 次提交
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由 Stefan Roese 提交于
In an attmemt to clean up the 4xx start.S file, I removed the enabling of the internal 405EP PCI arbiter. This is needed for multiple other 405EP platforms, like most of the esd 405EP. Now the internal PCI arbiter is enabled again per default as it has been before. Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NMatthias Fuchs <matthias.fuchs@esd-electronics.com>
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de> Acked-by: NMatthias Fuchs <matthias.fuchs@esd-electronics.com>
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- 15 11月, 2007 1 次提交
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由 Stefan Roese 提交于
- Rename CFG_440_GPIO_TABLE to CFG_4xx_GPIO_TABLE - Cleanup of the 4xx GPIO functions - Move some GPIO defines from the cpu headers ppc405.h/ppc440.h into gpio.h Signed-off-by: NStefan Roese <sr@denx.de>
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- 01 11月, 2007 1 次提交
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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- 23 6月, 2007 2 次提交
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由 Wolfgang Denk 提交于
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由 Igor Lisitsin 提交于
Added memory, CPU, UART, I2C and SPR POST tests for PPC440. Signed-off-by: NIgor Lisitsin <igor@emcraft.com> --
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- 24 3月, 2007 1 次提交
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由 Stefan Roese 提交于
This patch adds some 4xx GPIO functions. It also moves some of the common code and defines into a common 4xx GPIO header file. Signed-off-by: NStefan Roese <sr@denx.de>
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- 21 3月, 2007 1 次提交
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由 Stefan Roese 提交于
This patch adds support for the new AMCC 405EZ PPC. It is in preparation for the AMCC Acadia board support. Please note that this Acadia/405EZ support is still in a beta stage. Still lot's of cleanup needed but we need a preliminary release now. Signed-off-by: NStefan Roese <sr@denx.de>
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- 20 2月, 2007 1 次提交
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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