It seems that bytes 13-14 of the SID / bytes 1-2 from word 3 of the SID
are always 0 on H3 making it a poor candidate to use as source for the
serialnr / mac-address, and the other non constant words (1 and 2) also
have quite a few bits which are the same for some boards,

This commits switches to using the crc32 of words 1 - 3 to get a
more unique value for the mac-address / serialnr.

Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Corentin LABBE <clabbe.montjoie@gmail.com>
Cc: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

On 2 of my H3 boards bytes 13-15 of the SID are all 0 leading to
the NIC specific bytes of the mac all being 0, which leads to the
boards not getting an ipv6 address from the dhcp server.

This commits adds a check to ensure this does not happen.

Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Corentin LABBE <clabbe.montjoie@gmail.com>
Cc: Amit Singh Tomar <amittomer25@gmail.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

MACPWR was used to bring the Ethernet PHY out of reset. The designware
driver now supports the phy reset gpio binding, so this is no longer
needed. In fact in requesting the same GPIO, it makes the designware
driver fail to probe.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

sunxi uses a 2 cell phandle for gpio bindings. Also there are no
seperate nodes for each pin bank.

Add a custom .xlate function to map gpio phandles to the correct
pin bank device. This fixes gpio_request_by_name usage.

Fixes: 7aa97485 ("dm: sunxi: Modify the GPIO driver to support driver
		      model")
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

This patch is style-related only, to reformat all the start.S code,
actually not following a coherent style inside single files and
between different cpu start.S files.

Linux format has been respected, as
  - max line width at 80 columns
  - one 8 cols tab between asm instructions and operands
  - inline comments, where any, fixed at col 41
Signed-off-by: NAngelo Dureghello <angelo@sysam.it>

AM571x IDK and AM572x IDK EVMs have spansion s25fl256s QSPI flash on the
board connected to TI QSPI IP over CS0. Therefore enable QSPI support.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>

AM571x and AM572x IDK have a spansion s25fl256s QSPI flash on the board
connected to TI QSPI over CS0. Hence, add QSPI and flash slave
DT nodes.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>

AM437x SK and AM437x IDK EVMs have 64MB flash, therefore enable
CONFIG_SPI_FLASH_BAR to access flash regions above 16MB.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>

According to AM572x DM SPRS953A, QSPI max bus speed is 76.8MHz.
Therefore update the spi-max-frequency value of QSPI node for DRA74 and
DRA72 evm. This increase flash read speed by ~2MB/s.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>
Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>

Now that QSPI driver can support 76.8MHz, update the
CONFIG_SF_DEFAULT_SPEED to the same value.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>
Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>

According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, update
the driver to use the same.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>
Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>

According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence
update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz
clock, so that driver can use the same.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>

Add AT25DF321 flash support.
Fix AT25DF321A device name.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>

As per commit b545a98f ("spi: ti_qspi: Add delay
for successful bulk erase) says its added to meet bulk erase timing
constraints. But bulk erase is a cmd to flash and delay in read path
does not make sense. Morever, testing on DRA74/DRA72 evm has shown that
this delay is no longer required.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>
Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>

clk_div is uninitialized at the beginning of ti_spi_set_speed(), move
debug() print after clk_div calculation to avoid compiler warning and to
have proper value of clk_div printed during debugging.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>
Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>

Populating QSPI_RD_SNGL bit(0x1) in priv->cmd means that value
QSPI_INVAL (0x4) is not written to CMD field of QSPI_SPI_CMD_REG in
ti_qspi_cs_deactivate(). Therefore CS is never deactivated between
successive READ ID which results in sf probe to fail.
Fix this by not populating priv->cmd with QSPI_RD_SNGL and OR it wih
priv->cmd as required (similar to the convention followed in the
driver).
Signed-off-by: NVignesh R <vigneshr@ti.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>
Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>

This commit adds support in the spi-nor driver for the
N25Q016A, a 16Mbit SPI NOR flash from Micron.
Signed-off-by: NMoritz Fischer <moritz.fischer@ettus.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>

Pass the board/freescale/*mx*/ path as files maintained by Stefano
Babic.

While this is not ideal and does not cover all the i.MX board cases,
it gives at least a better hint for the /scripts/get_maintainer.pl
tool.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>

Add an entry for the mx7dsabresd_secure_defconfig target.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>

Use CONFIG_TIMER_CLK_FREQ to let the non-secure init code initialize
the generic timer on all CPU's. This allows to make use of the timer
freuquency register also on other CPU than the start CPU which is
important for KVM.
Signed-off-by: NStefan Agner <stefan.agner@toradex.com>

Remove unused define constant.
Signed-off-by: NDiego Dorta <diego.dorta@nxp.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>

cgtqmx6eval uses the imx_ddr_size() function to calculate the DDR size in
runtime, so there is no need to define PHYS_SDRAM_SIZE.

Remove the unneeded definition.

Cc: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Acked-by: NOtavio Salvador <otavio@ossystems.com.br>

novena uses the imx_ddr_size() function to calculate the DDR size in
runtime, so there is no need to define PHYS_SDRAM_SIZE.

Remove the unneeded definition.

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Acked-by: NMarek Vasut <marex@denx.de>

imx_ddr_size() can be used to calculate the DDR size in runtime.

By using this function we no longer need to define PHYS_SDRAM_SIZE.

Cc: Martin Donnelly <martin.donnelly@ge.com>
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>

imx_ddr_size() can be used to calculate the DDR size in runtime.

By using this function we no longer need to define PHYS_SDRAM_SIZE.

Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Acked-by: NHeiko Schocher <hs@denx.de>

imx_ddr_size() can be used to calculate the DDR size in runtime.

By using this function we no longer need to define PHYS_SDRAM_SIZE.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>

Currently it's recommended to move some configuration options to the
defconfig file.

Move some USB related options to the defconfig file.
Signed-off-by: NBreno Lima <breno.lima@nxp.com>

This commit adds support for the Toradex Computer on Modules
Colibri iMX7S/iMX7D. The two modules/SoC's are very similar hence
can be easily supported by one board. The board code detects RAM
size at runtime which is one of the differences between the two
boards. The board also uses the UART's in DTE mode, hence making
use of the new DTE support via serial DM.
Signed-off-by: NStefan Agner <stefan.agner@toradex.com>

It's not necessary to implement the is_mx6q function, there is a macro in
sys_proto.h already implemented.
Signed-off-by: NBreno Lima <breno.lima@nxp.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>

It's not necessary to implement the is_mx6q function, there is a macro in
sys_proto.h already implemented.
Signed-off-by: NBreno Lima <breno.lima@nxp.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>

It's not necessary to use the is_cpu_type function, there is a macro in
sys_proto.h already implemented.
Signed-off-by: NBreno Lima <breno.lima@nxp.com>
Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com>

Added removal of the fsl,ext-reset-output property in the wdog node for board
revisions that pre-date the addition of the external watchdog reset signal.

This property is a recent addition to mainline linux kernel in order to
specify that the IMX watchdog external reset should be used instead of the
internal chip-level reset.
Signed-off-by: NTim Harvey <tharvey@gateworks.com>

Re-factor the board-specific dt fixups so that they are easier to follow
and extend in the future:
 - use defines for DT paths
 - use switch/case per board
 - order models numerically

There is no functional change in the code
Signed-off-by: NTim Harvey <tharvey@gateworks.com>

The hwconfig env var allows user to control hardware specific configuration
of board specific features but not all Ventana boards have the same features.

We will use the magic default value of "_UNKNOWN_" to signify that the
bootloader should create this based on detected board model.
Signed-off-by: NTim Harvey <tharvey@gateworks.com>

The GW5520 has 10 DIO's instead of the typical 4 found on the Ventana
product family.
Signed-off-by: NTim Harvey <tharvey@gateworks.com>

Replace the static list of board-specific digital I/O's with a dynamic list.
Signed-off-by: NTim Harvey <tharvey@gateworks.com>

Not all Ventana boards have an RS232 transceiver, make it board specific.
Signed-off-by: NTim Harvey <tharvey@gateworks.com>

3b1f6811 caused a regression that removes
board info dispaly for Gateworks Ventana boards because it made the invalid
assumption that CONFIG_DISPLAY_BOARDINFO_LATE was the same thing as
CONFIG_DISPLAY_BOARDINFO.

Ventana needs to call show_board_info in late init because we need to have
the i2c eeprom based model info. Re-define CONFIG_DISPLAY_BOARDINFO_LATE
to allow that to happen.

Cc: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: NTim Harvey <tharvey@gateworks.com>

The IMX6 PCIe host controller does not have a proper reset and as such there
are several issues that can arise if PCI is enabled in the bootloader follwed
by Linux trying to re-configure LTSSM and/or toggling PERST# to the devices.

For now, the best approach seems to default to disabling PCI by defaulting
pciedisable=1. This can be overridden by the user if they need PCI in the
bootloader, for example:
 - GW552x needing ethernet access in bootloader
 - GW16082 expansion board needing a device-tree fixup for irq mapping
Signed-off-by: NTim Harvey <tharvey@gateworks.com>