With CONFIG_SYS_INIT_SP_BSS_OFFSET enabled, the initial (pre-relocation)
stack is placed some distance after bss_start. The control DTB is appended
to the U-Boot binary at bss_start. If the DTB is too large, or the SP BSS
offset too small, then the initial stack could corrupt the DTB. Enhance
the Makefile to check whether this is likely to occur.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Request that all environment variables containing hard-coded address be
calculated at boot time instead.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

In the presence of potentially fragemented memory, we cannot hard-code
addresses into environment variables such as kernel_addr_r. Instead, we
must calculate those addresses at run-time based on available memory
locations. Implement the code to perform such runtime calculation, based
on requirements described in environment variables, to allow the user
full control over the allocation.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Tegra186 currently restricts its DRAM usage to entries in the /memory node
in the DTB passed to it. However, the MMU configuration always maps the
entire first 2GB of RAM. This could allow the CPU to speculatively access
RAM that isn't part of the in-use banks. This patch switches to runtime
construction of the table that's used to construct the MMU translation
tables, and thus prevents access to RAM that's not part of a valid bank.

Note: This patch is intended to prevent access to RAM regions which U-Boot
does not need to access, with the primary purpose of avoiding theoretical
speculative access to physical regions for which the HW will throw errors
(e.g. carve-outs that the CPU has no permission to access at a bus level,
bad ECC pages, etc.). In particular, this patch is not deliberately
related to the speculation-related security issues that were recently
announced. The apparent similarity is a coincidence.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

On this platform, there may be up to 1024 unusable chunks of memory.
Increase CONFIG_NR_DRAM_BANKS so that U-Boot can remember all the banks
required to represent such fragmented memory.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

In the future, the list of DRAM regions passed to U-Boot in the DTB may
be quite long and fragmented. Due to this, U-Boot must search through the
regions to find the best region to relocate into, rather than relying on
the current assumption that the top of bank 0 is a reasonable relocation
target. This change implements such searching.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

arch_lmb_reserve() currently assumes that the stack pointer is within DRAM
bank 0. This is not necessarily true. Enhance the code to search through
DRAM banks until the bank that does contain SP is found, and then reserve
the tail of that bank.

Fixes: 2d1916e4 ("ARM: add flat device tree support")
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Apply a few small fixes for the DTB /memory node parsing from NVIDIA's
downstream U-Boot:

- Allow arbitrary number of DRAM banks.
- Correctly calculate the number of DRAM banks.
- Clip PCIe memory in the same way as U-Boot CPU memory use.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Enable CONFIG_LINUX_KERNEL_IMAGE_HEADER for all 64-bit Tegra boards.
cboot (the boot SW that runs before U-Boot) will eventually use this
information.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Allow placing a Linux kernel image header at the start of the U-Boot
binary. This is useful since the image header reports the amount of memory
(BSS and similar) that U-Boot needs to use, but that isn't part of the
binary size. This can be used by the code that loads U-Boot into memory to
determine where to load U-Boot, based on other users of memory.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Enable CONFIG_SYS_INIT_SP_BSS_OFFSET for all 64-bit Tegra boards. Place
the stack/... 512KiB from the end of the U-Boot binary. This should be
plenty to accommodate the current DTBs (max 64 KiB), early malloc region
(6KiB), stack usage, and plenty of slack, while still not placing it too
far away from the U-Boot binary.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

U-Boot typically uses a hard-coded value for the stack pointer before
relocation. Implement option SYS_INIT_SP_BSS_OFFSET to instead calculate
the initial SP at run-time. This is useful to avoid hard-coding addresses
into U-Boot, so that can be loaded and executed at arbitrary addresses and
thus avoid using arbitrary addresses at runtime. This option's value is
the offset added to &_bss_start in order to calculate the stack pointer.
This offset should be large enough so that the early malloc region, global
data (gd), and early stack usage do not overlap any appended DTB.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

No 64-bit Tegra uses SPL. Remove various unused definitions from config
headers.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

64-bit Tegra don't use SPL, and soon won't define CONFIG_SPL_TEXT_BASE
when building. Fix the binman .dts file so that it doesn't use undefined
values.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Current USDHC driver will reset VSELECT to 0 (3.3v) during mmc init,
then set to 1 for 1.8v eMMC I/O. When booting from eMMC, since ROM has
already set VSELECT to 1.8v before running the u-boot. This reset in
USDHC driver causes a short 2.2v pulse on CMD pin.

Fix this issue by not reset VSELECT to 0 when 1.8v flag is set.
Signed-off-by: NYe Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

In order to discard this code when unused in SPL we need to guard the
command with a check for CONFIG_SPL_BUILD and we rearrange the code
slightly to make this cleaner.

Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NTom Rini <trini@konsulko.com>

Enable travis-ci support with a link having built.
Signed-off-by: NChih-Mao Chen <cmchen@andestech.com>
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Signed-off-by: NGreentime Hu <green.hu@gmail.com>

Add documents to describe NX25 and AE250.
Also update other documents for RISC-V.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Signed-off-by: NGreentime Hu <green.hu@gmail.com>

Support common commands bdinfo and image format,
also modify common generic flow for RISC-V.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Signed-off-by: NGreentime Hu <green.hu@gmail.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Run hello_world successfully.

U-Boot 2018.01-rc2-00033-gb265b91-dirty (Dec 22 2017 - 13:54:21 +0800)

DRAM:  1 GiB
MMC:   mmc@f0e00000: 0
SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
In:    serial@f0300000
Out:   serial@f0300000
Err:   serial@f0300000
Net:
Warning: mac@e0100000 (eth0) using random MAC address - 0a:47:9b:f8:b4:f2
eth0: mac@e0100000
RISC-V # mmc rescan
RISC-V # fatls mmc 0:1
318907   u-boot-ae250-64.bin
1252   hello_world_ae250_32.bin
328787   u-boot-ae250-32.bin

3 file(s), 0 dir(s)

RISC-V # fatload mmc 0:1 0x600000 hello_world_ae250_32.bin
reading hello_world_ae250_32.bin
1252 bytes read in 23 ms (52.7 KiB/s)
RISC-V # go 0x600000
Example expects ABI version 9
Actual U-Boot ABI version 9
Hello World
argc = 1
argv[0] = "0x600000"
argv[1] = "$B@"
Hit any key to exit ...

RISC-V #
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Signed-off-by: NGreentime Hu <green.hu@gmail.com>

Add prelink-riscv to arrange .rela.dyn and .rela.got
in compile time. So that u-boot can be directly
executed without fixup.
Signed-off-by: NChih-Mao Chen <cmchen@andestech.com>
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Signed-off-by: NGreentime Hu <green.hu@gmail.com>

Add nx25-ae250 default configuration for RISC-V
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Signed-off-by: NGreentime Hu <green.hu@gmail.com>

Add nx25-ae250 board configuartion options for RISC-V
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Signed-off-by: NGreentime Hu <green.hu@gmail.com>

Add nx25-ae250 board to do platform initializations.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Signed-off-by: NGreentime Hu <green.hu@gmail.com>

Add Kconfig and makefile for RISC-V
Also modify MAINTAINERS for it.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Signed-off-by: NGreentime Hu <green.hu@gmail.com>
Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>

Add header files for RISC-V.
Cache, ptregs, data type and other definitions are included.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Signed-off-by: NGreentime Hu <green.hu@gmail.com>

AE250 is the Soc using NX25 cpu core base on RISC-V arch.
Details please see the doc/README.ae250.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Signed-off-by: NGreentime Hu <green.hu@gmail.com>

Add makefile, interrupts.c and boot.c,... functions
to support RISC-V arch.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Signed-off-by: NGreentime Hu <green.hu@gmail.com>
Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>

Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch

Verifications:
1. startup and relocation ok.
2. boot from rom or ram both ok.
2. timer driver ok.
3. uart driver ok
4. mmc driver ok
5. spi driver ok.
6. 32/64 bit both ok.

Detail verification message please see doc/README.ae250.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Signed-off-by: NGreentime Hu <green.hu@gmail.com>
Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>

hc_wp_grp_size is needed only if hardware partitionning is used.
On ARM removing it saves about 30 bytes of code space.
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>

This information is only used by the "mmc info" command.
On ARM removing this information from SPL saves about 140 of code space.
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>

Also remove erase_grp_size and write_bl_len from struct mmc as they are
not used anymore. On ARM, removing them saves about 100 bytes of code
space in SPL.
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>

The content of ssr is useful only for erase operations.
on ARM, removing sd_read_ssr() saves around 300 bytes.
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>

This allows using CONFIG_IS_ENABLED(MMC_WRITE) to compile out code
needed only if write support is required.
The option is added for u-boot and for SPL
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>

Using a table versus a switch() structure saves a bit of space
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>

Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>

struct mmc_data contains the block size to use for the data transfer.
Use this information instead of using the default value or the block length
information stored in struct mmc.
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>

This is not required as fastboot can't be started from SPL.
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>