- 16 10月, 2012 40 次提交
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由 Benoît Thébaudeau 提交于
The MFN bit-field of the PLL registers represents a signed value. See the reference manual. Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
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由 Benoît Thébaudeau 提交于
The i.MX5 eSDHC clocks were considered as coming from the IPG clock although they have dedicated clock paths. Also, on i.MX5/6, each SDHC instance has a dedicated clock, so gd->sdhc_clk must be set accordingly. This is good for the case only a single SDHC instance is used (initialization made with fsl_esdhc_mmc_init()). A future patch will fix the multi-instance use case (initialization made directly with fsl_esdhc_initialize()). Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Eric Bénard <eric@eukrea.com> Cc: Otavio Salvador <otavio@ossystems.com.br>
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由 Benoît Thébaudeau 提交于
There are only 2 I²C instances on i.MX51, but 3 on i.MX53. Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
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由 Benoît Thébaudeau 提交于
The FEC clock does not come from PLL1, but from the IPG clock. The previous code was even inconsistent with itself, returning the IPG clock as expected for imx_get_fecclk(), but the PLL1 clock for mxc_get_clock(MXC_FEC_CLK). Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
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由 Benoît Thébaudeau 提交于
The code handling the dividers was duplicated for each possible input clock, and this function can benefit from the newly introduced get_standard_pll_sel_clk() function instead of duplicating this mux handling code. Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
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由 Benoît Thébaudeau 提交于
This function returned 66500000 instead of the correct lp_apm clock frequency if the CCM.CSCMR1.uart_clk_sel mux is set to 3. This patch fixes this issue by introducing the get_standard_pll_sel_clk() function that will be used by future patches to handle identical muxes used by many other clocks. Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
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由 Benoît Thébaudeau 提交于
This fixes the "IPG PERCLK" frequency printed by the clocks command. The issue was that get_ipg_per_clk() used periph_clk instead of lp_apm in the case CCM.CBCMR.perclk_lp_apm_sel is set. It also fixes I²C support. Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
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由 Benoît Thébaudeau 提交于
In the case periph_clk comes from periph_apm_clk, the latter is selected by the CCM.CBCMR.periph_apm_sel mux, which can source the lp_apm clock from its input ♯2. get_periph_clk() returned 0 instead of the lp_apm clock frequency in this case. Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
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由 Benoît Thébaudeau 提交于
If CCM.CCSR.lp_apm is set, the lp_apm clock is not necessarily 32768 Hz x 1024. In that case: - on i.MX51, this clock comes from the output of the FPM, - on i.MX53, this clock comes from the output of PLL4. This patch fixes the code accordingly. Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
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由 Benoît Thébaudeau 提交于
This fixes config_pll_clk(), which used 0x20 instead of 0x200 for PLL4_CLOCK. Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
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由 Benoît Thébaudeau 提交于
The i.MX51 has a single USB PHY clock, while the i.MX53 has two. These 3 clocks have different clock gate control bit-fields. The existing code was correct only for i.MX53, so this patch fixes the i.MX51 use case. Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Jana Rapava <fermata7@gmail.com> Cc: Wolfgang Grandegger <wg@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il>
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由 Benoît Thébaudeau 提交于
The clock gate values are 2-bit bit-fields. Hence, setting or clearing only one of these bits like what was done is wrong and can lead to unpredictable behavior depending on the original value of these bit-fields. Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
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由 Benoît Thébaudeau 提交于
Use clock gate definitions having names showing clearly the gated clock instead of names giving only a register field index. Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
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由 Benoît Thébaudeau 提交于
Clean up the i.MX5 clock driver: - Use readl() and writel() instead of their __raw_ counterparts. - Use the clr/setbits_le32() family of macros rather than expanding code. - Use accessor macros for bit-fields instead of _MASK and _OFFSET. Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de>
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由 Benoît Thébaudeau 提交于
Define default SoC input clock frequencies for i.MX5/6 in order to get rid of duplicated definitions. Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Jason Liu <r64343@freescale.com> Cc: Matt Sealey <matt@genesi-usa.com> Cc: Fabio Estevam <fabio.estevam@freescale.com>
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由 Matthias Weisser 提交于
i2c didn't work on imx25 due to missing MXC_IPG_PERCLK. Now using MXC_I2C_CLK on all imx systems using i2c. Signed-off-by: NMatthias Weisser <weisserm@arcor.de> Acked-by: NStefano Babic <sbabic@denx.de>
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由 Eric Benard 提交于
tested on a MCIMX257CJM4A which now reports : CPU: Freescale i.MX25 rev1.2 at 399 MHz Signed-off-by: NEric Bénard <eric@eukrea.com> Acked-by: NOtavio Salvador <otavio@ossystems.com.br>
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由 Fabio Estevam 提交于
mx6qsabreauto is a board based on mx6q SoC with the following features: - 2GB of DDR3 - 2 USB ports - 1 HDMI output port - SPI NOR - 2 LVDS LCD ports - Gigabit Ethernet - Camera - eMMC and SD card slot - Multichannel Audio - CAN - SATA - NAND - PCIE - Video Input Add very basic support for it. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
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由 Fabio Estevam 提交于
Add a common mx6 config file that can be shared between some mx6 boards. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
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由 Eric Nelson 提交于
Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com>
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由 Eric Nelson 提交于
Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com> Acked-by: NStefano Babic <sbabic@denx.de>
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由 Eric Nelson 提交于
Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com> Acked-by: NStefano Babic <sbabic@denx.de>
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由 Eric Nelson 提交于
Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com>
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由 Eric Nelson 提交于
Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com>
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由 Eric Nelson 提交于
Register CCM_CHSCCDR (offset 0x34 in CCM) is named CCM_CHSCCDR in reference manual, but was named chscdr in struct mxc_ccm_reg. Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com>
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由 Eric Nelson 提交于
Add meaningful constants for each clock channels and use them for enabling and disabling i.MX6 clocks. Includes an update to enable/disable the IPU1 clock in drivers/video/ipu_common to remove IMX5x register access when used on i.MX6 as discussed in V1: http://patchwork.ozlabs.org/patch/185129/Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com>
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由 Fabio Estevam 提交于
USDHC3 has 8 pins wired in mx6qsabresd. Configure the extra pins. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
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由 Fabio Estevam 提交于
mx6qsabresd has a AR8031 Gigabit PHY. Add support for it. Also increase CONFIG_SYS_MALLOC_LEN so that FEC buffer allocation does not fail. Tested on 1Gbp and 100Mbps networks. Suggested-by: NKim Phillips <kim.phillips@freescale.com> Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Acked-by: NKim Phillips <kim.phillips@freescale.com>
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由 Fabio Estevam 提交于
mx6qsabresd is a board based on mx6q SoC with the following features: - 1GB of DDR3 - 1 USB OTG port - 1 HDMI output port - SPI NOR - LVDS panel - Gigabit Ethernet - Camera Connector - eMMC and SD card slot - Audio Add very basic support for it. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
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由 Fabio Estevam 提交于
Factor out common DDR3 initialization code, allowing easier maintainance of such scripts. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
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由 Lukasz Dalek 提交于
Add function which return CPU model and revision which can be used for cpu detection. Signed-off-by: NLukasz Dalek <luk0104@gmail.com>
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由 Lucas Stach 提交于
Boards may require a different pinmux setup for NAND than the default one. Add a way to call into board specific code to set this up. Signed-off-by: NLucas Stach <dev@lynxeye.de> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Lucas Stach 提交于
The prototypes used in board files were all scattered out, which lead to code duplication between SPL and normal U-Boot and some prototypes not actually being used. Consolidate this in a common board header. Signed-off-by: NLucas Stach <dev@lynxeye.de> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Lucas Stach 提交于
Secondary config for the Flash attachment. Signed-off-by: NLucas Stach <dev@lynxeye.de> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Lucas Stach 提交于
Rename board provided gpio_config_uart() to gpio_early_init_uart() as it does the same thing as the equally called function provided by the uart-switch code. This allows to simply call this function in early board init whether or not we are building with CONFIG_UART_SWITCH defined. Also provide a weak symbol for this function, to avoid the need to provide this function for boards that don't need any fixup. This patch supersedes the earlier posted "tegra: convert gpio_config_uart to weak symbol". Build tested with MAKEALL -s tegra20 Signed-off-by: NLucas Stach <dev@lynxeye.de> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Lucas Stach 提交于
Common practice on Tegra 2 boards is to use the pllp_out4 FO to generate the ULPI reference clock. For this to work we have to override the default hardware generated output divider. This function adds a clean way to do so. Signed-off-by: NLucas Stach <dev@lynxeye.de> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Lucas Stach 提交于
Most Tegra boards output the ULPI reference clock on pad DEV2. Complete the periph_id enum so that we are able to enable this clock output circuit. Signed-off-by: NLucas Stach <dev@lynxeye.de> Acked-by: NStephen Warren <swarren@wwwdotorg.org> Acked-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Stephen Warren 提交于
This is extremely likely to be used from the boot.scr that Tegra's default bootcmd locates and executes. Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Tom Warren 提交于
The move is pretty straight-forward. ap20.h and tegra20.h were renamed to ap.h and tegra.h. Some files remain in arch-tegra20 but 'include' a file in 'arch-tegra' with #defines & structs that will be common between T20 and T30 HW. HW-specific #defines, etc. stay in the 'arch-tegra20' 'root' file. All boards build OK w/MAKEALL -s tegra20. Checkpatch.pl runs clean. Seaboard works OK. Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Tom Warren 提交于
Move files that are going to be common between T20 and T30 into 'tegra-common' subdirs in AVP (arm720t), CPU (armv7), and shared (arch/arm/cpu/.) areas. Any files that are left behind in '/tegra20' will be copied to '/tegra30' subdirs and modified for that SoC. The 'common' files should need only minor changes. Include files (arch/arm/include/asm/arch-tegra/tegra20) will be done in a follow-on patch. Builds fine w/MAKEALL -s tegra20. Checkpatch.pl is clean. Signed-off-by: NTom Warren <twarren@nvidia.com>
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