1. 24 10月, 2016 2 次提交
  2. 12 10月, 2016 1 次提交
  3. 27 9月, 2016 2 次提交
  4. 20 9月, 2016 1 次提交
  5. 17 9月, 2016 1 次提交
  6. 10 9月, 2016 2 次提交
  7. 09 9月, 2016 1 次提交
  8. 07 9月, 2016 1 次提交
  9. 08 8月, 2016 1 次提交
  10. 10 6月, 2016 1 次提交
  11. 02 6月, 2016 1 次提交
  12. 17 5月, 2016 1 次提交
  13. 26 4月, 2016 3 次提交
  14. 20 4月, 2016 3 次提交
  15. 10 4月, 2016 1 次提交
  16. 26 3月, 2016 1 次提交
  17. 15 3月, 2016 2 次提交
    • S
      Kconfig: Move CONFIG_FIT and related options to Kconfig · 73223f0e
      Simon Glass 提交于
      There are already two FIT options in Kconfig but the CONFIG options are
      still in the header files. We need to do a proper move to fix this.
      
      Move these options to Kconfig and tidy up board configuration:
      
         CONFIG_FIT
         CONFIG_OF_BOARD_SETUP
         CONFIG_OF_SYSTEM_SETUP
         CONFIG_FIT_SIGNATURE
         CONFIG_FIT_BEST_MATCH
         CONFIG_FIT_VERBOSE
         CONFIG_OF_STDOUT_VIA_ALIAS
         CONFIG_RSA
      
      Unfortunately the first one is a little complicated. We need to make sure
      this option is not enabled in SPL by this change. Also this option is
      enabled automatically in the host builds by defining CONFIG_FIT in the
      image.h file. To solve this, add a new IMAGE_USE_FIT #define which can
      be used in files that are built on the host but must also build for U-Boot
      and SPL.
      
      Note: Masahiro's moveconfig.py script is amazing.
      Signed-off-by: NSimon Glass <sjg@chromium.org>
      [trini: Add microblaze change, various configs/ re-applies]
      Signed-off-by: NTom Rini <trini@konsulko.com>
      73223f0e
    • S
      Correct defconfig ordering · 4edb9458
      Simon Glass 提交于
      Various boards have the wrong Kconfig ordering now. To avoid a misleading
      
      diff in the next patch, reorder the configuration correctly.
      Signed-off-by: NSimon Glass <sjg@chromium.org>
      4edb9458
  18. 13 1月, 2016 1 次提交
  19. 20 12月, 2015 1 次提交
    • M
      arm: socfpga: sockit: Probe DWC2 UDC from OF instead of hard-coded data · 225217da
      Marek Vasut 提交于
      This patch adds the necessary OF alias for the UDC node, which let's
      the code locate the DWC2 UDC base address in OF instead of hard-coding
      it into the U-Boot binary. The code is adjusted to use the address from
      OF instead of the hard-coded one. Finally, the hard-coded address is
      removed and USB DM support is enabled.
      Signed-off-by: NMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Lukasz Majewski <l.majewski@majess.pl>
      Cc: Lukasz Majewski <l.majewski@samsung.com>
      225217da
  20. 07 12月, 2015 1 次提交
    • M
      arm: socfpga: Enable CONFIG_DM_MMC · 540fcbca
      Marek Vasut 提交于
      Enable driver model MMC support on SoCFPGA.
      Signed-off-by: NMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <clsee@altera.com>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
      Cc: Simon Glass <sjg@chromium.org>
      Cc: Tom Rini <trini@konsulko.com>
      540fcbca
  21. 25 11月, 2015 2 次提交
  22. 22 11月, 2015 1 次提交
  23. 19 11月, 2015 1 次提交
  24. 28 9月, 2015 1 次提交
  25. 04 9月, 2015 1 次提交
  26. 23 8月, 2015 2 次提交
    • M
      arm: socfpga: Enable DWAPB GPIO driver · 1bd57ff5
      Marek Vasut 提交于
      Enable the DWAPB GPIO driver for SoCFPGA Cyclone V and Arria V.
      Signed-off-by: NMarek Vasut <marex@denx.de>
      Cc: Simon Glass <sjg@chromium.org>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      1bd57ff5
    • M
      arm: socfpga: Unbind CPU type from board type · cd9b7317
      Marek Vasut 提交于
      The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5
      selected both a board and a CPU. This is not correct as these macros
      are supposed to select only board.
      
      All would be good, if QTS-generated header files didn't check for
      these macros exactly to determine if the platform is Cyclone V or
      Arria V. Thus, for the sake of compatibility with not well fleshed
      out header file generator, this patch makes these two macros into
      a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK
      and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the
      previous stub config option.
      
      The result is that compatibility with QTS is preserved and the new
      CONFIG_TARGET_* select actual target boards.
      Signed-off-by: NMarek Vasut <marex@denx.de>
      cd9b7317
  27. 22 8月, 2015 1 次提交
  28. 19 8月, 2015 1 次提交
  29. 08 8月, 2015 2 次提交
    • M
      arm: socfpga: config: Move SPL GD and malloc to RAM · 7599b53d
      Marek Vasut 提交于
      Now that the SPL structure is organised such that it matches the
      U-Boot's SPL design, it is possible to use the option of relocating
      GD to RAM. And since we have GD in RAM, move malloc area to RAM as
      well. We point the malloc base pointer 1 MiB past U-Boot's load
      address. We use simple malloc for SPL because it is 3kiB smaller
      in terms of code size than regular malloc which was used thus far.
      Signed-off-by: NMarek Vasut <marex@denx.de>
      7599b53d
    • M
      arm: socfpga: misc: Probe ethernet GMAC from OF · e14d3f79
      Marek Vasut 提交于
      The GMAC can now be probed from OF, so enable DM ethernet and remove the
      old ad-hoc designware_initialize() invocation.
      Signed-off-by: NMarek Vasut <marex@denx.de>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Joe Hershberger <joe.hershberger@ni.com>
      e14d3f79