The PIO on the R40 SoC is mostly compatible with the A20.
Only a few pin functions for mmc2 were added to the PC
pingroup, to support 8 bit eMMCs.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

These values were taken from the Banana Pi M2 Ultra fex file
found in the released vendor BSP. This is the only publicly
available R40 device at the time of this writing.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

According to the BSP released by Banana Pi, the R40 (sun8iw11p1) has
an extra "PLL lock control" register in the CCU, which controls whether
the individual PLL lock status bits in each PLL's control register work
or not.

This patch enables it for all the PLLs.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The PIO is generally compatible with the A20, except that it routes the
full 8 bits and eMMC reset pins for mmc2.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The watchdog found on the R40 SoC is the older variant found on the A20.
Add the proper "#if defines" to make it work.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The R40 SoC uses the AXP221s in I2C mode to supply power.

Some regulator's common usages have changed, and also the recommended
voltage for existing usages have changed. Update the defaults to match.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The R40 is the successor to the A20. It is a hybrid of the A20, A33
and the H3.

The R40's PIO controller is compatible with the A20,
Reuse the A20 UART and I2C muxing code by adding the R40's macro.

The display pipeline is the newer DE 2.0 variant.
Block enabling video on R40 for now.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Currently we have some lines in board/sunxi/Kconfig that are very long.
These line either provide default values for a set of SoCs, or limit
some option to a subset of sunxi SoCs.

Fortunately Kconfig makes it easy to split them. The Kconfig language
document states

    If multiple dependencies are defined, they are connected with '&&'.

This means we can split existing dependencies at "&&" symbols. This
applies to both the "depends on" lines and "if" expressions.

This patch splits them up to one symbol per line. This will make it
easier to add, remove, or modify one item at a time.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Convert the CONS_INDEX configuration to Kconfig.
Update sunxi's defconfigs to remove SYS_EXTRA_OPTIONS variable not
needed anymore.
Default value is 1 except for sun5i (equals 2) and sun8i (equals 5).
Signed-off-by: NMylène Josserand <mylene.josserand@free-electrons.com>
[Maxime: Added a depends on ARCH_SUNXI to avoid build breakages]
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Convert the CONFIG_MACPWR to Kconfig and update all the sunxi defconfigs
that used it in SYS_EXTRA_OPTIONS.
Signed-off-by: NMylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Convert the CONFIG_SATAPWR into kconfig.
Thanks to that, many SYS_EXTRA_OPTIONS can be removed from some
defconfigs.
Signed-off-by: NMylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Convert CONFIG_RGMII to Kconfig. Thanks to that, it is possible to
update defconfig files of SYS_EXTRA_OPTIONS accordingly and
remove it when it is possible.
Signed-off-by: NMylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Convert the SUNXI_EMAC config to Kconfig. Remove it from SYS_EXTRA_OPTIONS
from many sunxi defconfig and renamed it into SUN4I_EMAC to not confuse it
with SUN8I_EMAC.
Signed-off-by: NMylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The USB_EHCI configuration is already set in this defconfig
using kconfig's config. This configuration in SYS_EXTRA_OPTIONS
must be removed and so the SYS_EXTRA_OPTIONS.
Signed-off-by: NMylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

This configuration is not necessary in a defconfig file so
it is removed from the SYS_EXTRA_OPTIONS.
Signed-off-by: NMylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Remove the AXP209_POWER option from SYS_EXTRA_OPTIONS.
As this configuration already exists on Kconfig, we just need
to remove it from defconfig.
Signed-off-by: NMylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Move the SUNXI_GMAC config option to Kconfig, remove it
from SYS_EXTRA_OPTIONS and rename it into SUN7I_GMAC.
Signed-off-by: NMylène Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Add myself as maintainer of the NanoPi NEO Air board.
Signed-off-by: NJelle van der Waa <jelle@vdwaa.nl>
Reviewed-by: NJagan Teki <jagan@openedev.com>

Signed-off-by: NTom Rini <trini@konsulko.com>

The RK3399-Q7 ("Puma") SoM exposes UART0 as the Qseven UART (i.e. the
serial line available via standardised pins on the edge connector and
available on a RS232 connector).

To support boards (such as the RK3399-Q7) that require UART0 as a
debug console, we match CONFIG_DEBUG_UART_BASE and add the appropriate
iomux setup to the rk3399 SPL code.

As we are already touching this code, we also move the board-specific
UART setup (i.e. iomux setup) into board_debug_uart_init(). This will
be called from the debug UART init when CONFIG_DEBUG_UART_BOARD_INIT
is set.

As the RK3399 needs to use its board_debug_uart_init() function, we
have Kconfig enable it by default for RK3399 builds.

With everything set up to define CONFIG_BAUDRATE via defconfig and
with to have the SPL debug UART either on UART0 or UART2, the configs
for the RK3399 EVB are then update (the change for the RK3399-Q7 is
left for later to not cause issues on applying the change).
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

For using mipi display, we need to enable lcd3v3
which supplied by rk808,so enable rk808 first.
Signed-off-by: NEric Gao <eric.gao@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

To enable mipi display, we need to enable pmic
rk808 first for lcd3v3 power,which use i2c0 to
communicate with soc. So enable i2c0.
Signed-off-by: NEric Gao <eric.gao@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

when enable PMIC rk808,the system will halt at very
 early stage,log is shown as bellow.

INFO:    plat_rockchip_pmu_init(1211): pd status 3e
INFO:    BL31: Initializing runtime services
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0x200000
INFO:    SPSR = 0x3c9
time 44561b, 0 (<<----Just stop here)

It's caused by the absence of "{ }" in syscon_rk3399.c
,which will lead to memory overflow like below.According
 to Sysmap file ,we can find the function buck_get_value
of rk808 is just follow the compatible struct,the pointer
"of_match" point to "buck_get_value",but it is not a
struct and don't have member of compatible, In this case,
system crash. So,on the face, it looks like that rk808 is
guilty.but he is really innocent.

while (of_match->compatible) { <<----------
    if (!strcmp(of_match->compatible, compat)) {
    *of_idp = of_match;
    return 0;
    }
    of_match++;
}
Signed-off-by: NEric Gao <eric.gao@rock-chips.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
Tested-by: NKever Yang <kever.yang@rock-chips.com>

The RK3399-Q7 SoM is a Qseven-compatible (70mm x 70mm, MXM-230
connector) system-on-module from Theobroma Systems, featuring the
Rockchip RK3399.

It provides the following feature set:
 * up to 4GB DDR3
 * on-module SPI-NOR flash
 * on-module eMMC (with 8-bit interace)
 * SD card (on a baseboad) via edge connector
 * Gigabit Ethernet w/ on-module Micrel KSZ9031 GbE PHY
 * HDMI/eDP/MIPI displays
 * 2x MIPI-CSI
 * USB
   - 1x USB 3.0 dual-role (direct connection)
   - 2x USB 3.0 host + 1x USB 2.0 (on-module USB 3.0 hub)
 * on-module STM32 Cortex-M0 companion controller, implementing:
   - low-power RTC functionality (ISL1208 emulation)
   - fan controller (AMC6821 emulation)
   - USB<->CAN bridge controller

Note that we use a multi-payload FIT image for booting and have
Cortex-M0 payload in a separate subimage: we thus rely on the FIT
image loader to put it into the SRAM region that ATF expects it in.
Signed-off-by: NKlaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Fixed build warning on puma-rk3399:
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The RK3399-Q7 (Puma) DTS should (of course) be dual-licensed.
This updates the licensing info in the rk3399-puma.dts.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The warm-reset of rk3188 socs keeps the remap setting as it was, so if
it was enabled, the cpu would start from address 0x0 of the sram instead
of address 0x0 of the bootrom, thus making the reset hang.

Therefore make sure the remap is disabled before attempting a warm reset.

Cold reset is not affected by this at all.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NSimon Glass <sjg@chromium.org>

The lower address is reserved for ATF, do not use it.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Most Rockchip socs have the ability to either map the bootrom or a sram
area to the starting address of the cpu by flipping a bit in the GRF.

Newer socs leave this untouched and mapped to the bootrom but the legacy
loaders on rk3188 and before enabled the remap functionality and the
current smp implementation in the Linux kernel also requires it to be
enabled, to bring up secondary cpus.

So to keep smp working in the kernel, mimic the behaviour of the legacy
bootloaders and enable the remap functionality.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NSimon Glass <sjg@chromium.org>

Somehow 43b5c78d ("rockchip: cosmetic: Sort RK3288 boards") moved
the rock board in between some rk3288 board, probably as a result of
rebasing.

So move it back to its original position above all rk3288 boards.

Fixes: 43b5c78d ("rockchip: cosmetic: Sort RK3288 boards")
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Acked-by: NSimon Glass <sjg@chromium.org>

Now that most rockchip SoC based board have usb host support, enable
USB boot targets by default.
Signed-off-by: NEddie Cai <eddie.cai.linux@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Fixed build errors when CONFIG_CMD_USB not defined:
Signed-off-by: NSimon Glass <sjg@chromium.org>

tinker board support ethernet and usb host, so enable USB, PXE and DHCP support.
Signed-off-by: NEddie Cai <eddie.cai.linux@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: NSimon Glass <sjg@chromium.org>

The RK3399 hangs during DMA of the Designware MMC controller, when
performing DMA-based transactions in SPL due to the DDR security settings
left behind by the BootROM (i.e. accesses to the first MB of DRAM are
restricted... however, the DMA is likely to target this first MB, as it
transfers from/to the stack).

System security is not affected, as the final security configuration is
performed by the ATF, which is executed after the SPL stage.

With this fix in place, we can now drop 'fifo-mode' in the DTS for the
RK3399-Q7 (Puma).
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>

Due to the introduction of the pinctrl and clk driver, and using
device tree files, remove the unneeded hardcoded pin configuration
and clock enabling code from the board file.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>

Update the configuration files to support the device tree and driver
model, so do SPL. The device clock and pins configuration are handled
by the clock and the pinctrl drivers respectively.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Fix build error with sama5d3_xplained_mmc:
Signed-off-by: NSimon Glass <sjg@chromium.org>

Enable the early debug UART to debug problems when an ICE or other
debug mechanism is not available.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>

Due to the introduction of the pinctrl and clk driver, and using
device tree files, remove the unneeded hardcoded pin configuration
and clock enabling code from the board file.
Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com>
Remove CONFIG_PHY_MICREL as per previous patch:
Signed-off-by: NSimon Glass <sjg@chromium.org>