- 18 3月, 2009 1 次提交
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由 arun c 提交于
According to coldfire manual data timeout > address time out also use correct macro to program XARB_CFG Signed-off-by: NArun C <arunedarath@mistralsolutions.com>
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- 16 3月, 2009 5 次提交
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由 Wolfgang Denk 提交于
Update CHANEGLOG, fix minor coding style issue. Signed-off-by: NWolfgang Denk <wd@denx.de>
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- 15 3月, 2009 2 次提交
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由 Jerry Van Baren 提交于
The routine assumed 4 bank SDRAMs, enhance to configure for 4 or 8 bank SDRAMs. Signed-off-by: NGerald Van Baren <vanbaren@cideas.com> Acked-by: NDave Liu <daveliu@freescale.com> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Norbert van Bolhuis 提交于
This patch makes sure the correct mask is applied when setting the encryption and I2C bus 0 clock in SCCR. Failing to do so may lead to ENCCM being 0 in which case I2C bus 0 won't function. Signed-off-by: NNorbert van Bolhuis <nvbolhuis@aimvalley.nl> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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- 14 3月, 2009 1 次提交
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由 Dirk Behme 提交于
Read and store OMAP3 die ID in U-Boot environment. Signed-off-by: NDirk Behme <dirk.behme@googlemail.com>
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- 13 3月, 2009 2 次提交
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由 Jon Smirl 提交于
Set a non-zero speed in the MII register so that MII commands will work. Signed-off-by: NJon Smirl <jonsmirl@gmail.com>
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由 Yusuke.Goda 提交于
Signed-off-by: NYusuke Goda <goda.yusuke@renesas.com> Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>
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- 12 3月, 2009 8 次提交
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由 Yoshihiro Shimoda 提交于
The rtl8139 driver use pci_mem_to_phys. So it need PCI system memory registration. Signed-off-by: NYoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Nobuhiro Iwamatsu 提交于
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Yoshihiro Shimoda 提交于
We can built 'make sh7785lcr_32bit_config'. And add new command "pmb" for this mode. This command changes PMB for using 512MB system memory. Signed-off-by: NYoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Yoshihiro Shimoda 提交于
Some register value was hardcoded for System memory size 128MB and memory offset 0x08000000. This patch fixed the problem. Signed-off-by: NYoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Yoshihiro Shimoda 提交于
It is necessary for some pci device driver. Signed-off-by: NYoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Yoshihiro Shimoda 提交于
Signed-off-by: NYoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Yoshihiro Shimoda 提交于
Signed-off-by: NYoshihiro Shimoda <shimoda.yoshihiro@renesas.com> Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>
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由 Nobuhiro Iwamatsu 提交于
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>
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- 11 3月, 2009 2 次提交
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- 10 3月, 2009 5 次提交
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由 Paul Gortmaker 提交于
Commit af1c2b84 added a generic phy support, with an ID of zero and a 32 bit mask; meaning that it will match on any PHY ID. The problem is that there is a test that checked if a matching PHY was found, and if not, it printed the non-matching ID. But since there will always be a match (on the generic PHY, worst case), this test will never trip. In the case of a misconfigured PHY address, or of a PHY that isn't explicitly supported outside of the generic support, you will never see the ID of 0xffffffff, or the ID of the real (but unsupported) chip. It will silently fall through onto the generic support. This change makes that test useful again, and ensures that the selection of generic PHY support doesn't happen without some sort of notice. It also makes it explicitly clear that the generic PHY must be last in the PHY table. Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com> Acked-by: NAndy Fleming <afleming@freescale.com>
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由 Wolfgang Denk 提交于
Fix typo in makefile which broke out of tree builds. Also use expolicit "rm" instead of "ln -sf" which is known to be unreliable. Signed-off-by: NWolfgang Denk <wd@denx.de> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 ksi@koi8.net 提交于
This adds tsec12ioovcr to include/asm-ppc/immap_85xx.h (was reserved.) Signed-off-by: NSergey Kubushyn <ksi@koi8.net>
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由 Andy Fleming 提交于
These were left in accidentally, and are not really useful unless the code is as broken as it was when it was being developed. Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Ed Swarthout 提交于
Commit e1be0d25, "32bit BUg fix for DDR2 on 8572" prevented other sdram_cfg bits (such as ecc and self_refresh_in_sleep) from being set. Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com>
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- 09 3月, 2009 3 次提交
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Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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由 Wolfgang Denk 提交于
Fix typo in makefile which broke out of tree builds. Also use expolicit "rm" instead of "ln -sf" which is known to be unreliable. Signed-off-by: NWolfgang Denk <wd@denx.de>
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git://git.denx.de/u-boot-mpc83xx由 Wolfgang Denk 提交于
Conflicts: lib_ppc/board.c Signed-off-by: NWolfgang Denk <wd@denx.de>
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- 06 3月, 2009 10 次提交
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由 Heiko Schocher 提交于
add CONFIG_BOOTCOUNT_LIMIT feature for 8360 CPU. The bootcounter uses 8 bytes from the muram, because no other memory was found on this CPU for the bootcount feature. So we must correct the muram size in DTS before booting Linux. This feature is actual only implemented for MPC8360, because not all 83xx CPU have qe, and therefore no muram, which this feature uses. Signed-off-by: NHeiko Schocher <hs@denx.de> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Heiko Schocher 提交于
old code implemented the QE_ENET10 errata only for Silicon Revision 2.0. New code reads now the Silicon Revision register and sets dependend on the Silicon Revision the values as advised in the QE_ENET10 errata. Signed-off-by: NHeiko Schocher <hs@denx.de> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Heiko Schocher 提交于
- HRCW update HRCWH_BOOTSEQ_DISABLE not HRCWH_BOOTSEQ_NORMAL HRCWH_LALE_EARLY added - DDR-SDRAM settings modified. This solves sporadically problems with this memory. - CS1 now 128 MB window size - CS3 now 512 MB window size - PRAM activated - MTDPARTS_DEFAULT defined - CONFIG_HOSTNAME added - MONITOR_LEN now 384 KB Signed-off-by: NHeiko Schocher <hs@denx.de> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Heiko Schocher 提交于
it is possible that some board variants have different DDR II RAM sizes. So we autodetect the size of the assembled RAM. Signed-off-by: NHeiko Schocher <hs@denx.de> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Heiko Schocher 提交于
This patch adds I2C mux support for the fsl_i2c driver. This allows you to add "new" i2c busses, which are reached over i2c muxes. For more infos, please look in the README and search for CONFIG_I2C_MUX. Signed-off-by: NHeiko Schocher <hs@denx.de> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Heiko Schocher 提交于
This patch adds I2C support for the Keymile kmeter1 board. It uses the First I2C Controller from the CPU, for accessing 4 temperature sensors, an eeprom with IVM data and the booteeprom over a pca9547 mux. Signed-off-by: NHeiko Schocher <hs@denx.de> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Heiko Schocher 提交于
In case where a board not uses CONFIG_POST, it is not necessary to init the DTTs when running from flash. Signed-off-by: NHeiko Schocher <hs@denx.de> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Dave Liu 提交于
1. RD_TO_PRE missed to add the AL, and need min 2 clocks for tRTP according to DDR2 JEDEC spec. 2. WRTORD - tWTR need min 2 clocks according to DDR2 JEDEC spec. 3. add the support of DDR2-533,667,800 DIMMs 4. cpo 5. make the AL to min to gain better performance. The Micron MT9HTF6472CHY-667D1 DIMMs test passed on MPC837xEMDS platform at 266MHz/333MHz/400MHz data rate. items 1, 2 and 5: Acked-by: NJoakim Tjernlund <Joakim.Tjernlund@transmode.se> Reported-by: NJoakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: NDave Liu <daveliu@freescale.com> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Valeriy Glushkov 提交于
The previous version rebooted forever with DDR bigger than 256MB. Access the DS1339 RTC chip is on I2C1 bus. Allow DHCP. Signed-off-by: NValeriy Glushkov <gvv@lstec.com> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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由 Anton Vorontsov 提交于
The SerDes initialization should be finished before negating the reset signal according to the reference manual. This isn't an issue on real hardware, but we'd better stick to the specifications anyway. Suggested-by: NLiu Dave <DaveLiu@freescale.com> Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
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- 02 3月, 2009 1 次提交
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由 Heiko Schocher 提交于
it is not necessary to init the DTTs so early, so move this init to board_init_r (). Signed-off-by: NHeiko Schocher <hs@denx.de>
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