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014c595f
编写于
3月 09, 2009
作者:
W
Wolfgang Denk
浏览文件
操作
浏览文件
下载
差异文件
Merge branch 'master' of
git://git.denx.de/u-boot-mpc83xx
Conflicts: lib_ppc/board.c Signed-off-by:
N
Wolfgang Denk
<
wd@denx.de
>
上级
9c2d63ec
f70fd13e
变更
10
隐藏空白更改
内联
并排
Showing
10 changed file
with
259 addition
and
70 deletion
+259
-70
board/freescale/mpc837xemds/pci.c
board/freescale/mpc837xemds/pci.c
+7
-7
board/keymile/common/common.c
board/keymile/common/common.c
+1
-1
board/keymile/kmeter1/kmeter1.c
board/keymile/kmeter1/kmeter1.c
+63
-18
cpu/mpc83xx/cpu.c
cpu/mpc83xx/cpu.c
+34
-0
cpu/mpc83xx/fdt.c
cpu/mpc83xx/fdt.c
+18
-0
cpu/mpc83xx/spd_sdram.c
cpu/mpc83xx/spd_sdram.c
+23
-3
drivers/i2c/fsl_i2c.c
drivers/i2c/fsl_i2c.c
+21
-1
include/configs/MPC8349ITX.h
include/configs/MPC8349ITX.h
+5
-0
include/configs/keymile-common.h
include/configs/keymile-common.h
+0
-7
include/configs/kmeter1.h
include/configs/kmeter1.h
+87
-33
未找到文件。
board/freescale/mpc837xemds/pci.c
浏览文件 @
014c595f
...
...
@@ -115,6 +115,13 @@ skip_pci:
if
(
PARTID_NO_E
(
spridr
)
==
SPR_8379
)
return
;
if
(
pex2
)
fsl_setup_serdes
(
CONFIG_FSL_SERDES2
,
FSL_SERDES_PROTO_PEX_X2
,
FSL_SERDES_CLK_100
,
FSL_SERDES_VDD_1V
);
else
fsl_setup_serdes
(
CONFIG_FSL_SERDES2
,
FSL_SERDES_PROTO_PEX
,
FSL_SERDES_CLK_100
,
FSL_SERDES_VDD_1V
);
/* Configure the clock for PCIE controller */
clrsetbits_be32
(
&
clk
->
sccr
,
SCCR_PCIEXP1CM
|
SCCR_PCIEXP2CM
,
SCCR_PCIEXP1CM_1
|
SCCR_PCIEXP2CM_1
);
...
...
@@ -132,13 +139,6 @@ skip_pci:
out_be32
(
&
pcie_law
[
1
].
bar
,
CONFIG_SYS_PCIE2_BASE
&
LAWBAR_BAR
);
out_be32
(
&
pcie_law
[
1
].
ar
,
LBLAWAR_EN
|
LBLAWAR_512MB
);
if
(
pex2
)
fsl_setup_serdes
(
CONFIG_FSL_SERDES2
,
FSL_SERDES_PROTO_PEX_X2
,
FSL_SERDES_CLK_100
,
FSL_SERDES_VDD_1V
);
else
fsl_setup_serdes
(
CONFIG_FSL_SERDES2
,
FSL_SERDES_PROTO_PEX
,
FSL_SERDES_CLK_100
,
FSL_SERDES_VDD_1V
);
mpc83xx_pcie_init
(
pex2
?
1
:
2
,
pcie_reg
,
0
);
}
...
...
board/keymile/common/common.c
浏览文件 @
014c595f
...
...
@@ -318,7 +318,7 @@ int ivm_read_eeprom (void)
if
(
buf
!=
NULL
)
dev_addr
=
simple_strtoul
((
char
*
)
buf
,
NULL
,
16
);
if
(
eeprom_read
(
dev_addr
,
0
,
i2c_buffer
,
CONFIG_SYS_IVM_EEPROM_MAX_LEN
)
!=
0
)
{
if
(
i2c_read
(
dev_addr
,
0
,
1
,
i2c_buffer
,
CONFIG_SYS_IVM_EEPROM_MAX_LEN
)
!=
0
)
{
printf
(
"Error reading EEprom
\n
"
);
return
-
2
;
}
...
...
board/keymile/kmeter1/kmeter1.c
浏览文件 @
014c595f
...
...
@@ -24,11 +24,14 @@
#include <miiphy.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <pci.h>
#include <libfdt.h>
#include "../common/common.h"
extern
void
disable_addr_trans
(
void
);
extern
void
enable_addr_trans
(
void
);
const
qe_iop_conf_t
qe_iop_conf_tab
[]
=
{
/* port pin dir open_drain assign */
...
...
@@ -59,27 +62,54 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
{
0
,
0
,
0
,
0
,
QE_IOP_TAB_END
},
};
static
int
board_init_i2c_busses
(
void
)
{
I2C_MUX_DEVICE
*
dev
=
NULL
;
uchar
*
buf
;
/* Set up the Bus for the DTTs */
buf
=
(
unsigned
char
*
)
getenv
(
"dtt_bus"
);
if
(
buf
!=
NULL
)
dev
=
i2c_mux_ident_muxstring
(
buf
);
if
(
dev
==
NULL
)
{
printf
(
"Error couldn't add Bus for DTT
\n
"
);
printf
(
"please setup dtt_bus to where your
\n
"
);
printf
(
"DTT is found.
\n
"
);
}
return
0
;
}
int
board_early_init_r
(
void
)
{
void
*
reg
=
(
void
*
)(
CONFIG_SYS_IMMR
+
0x14a8
);
u32
val
;
unsigned
short
svid
;
/*
* Because of errata in the UCCs, we have to write to the reserved
* registers to slow the clocks down.
*/
val
=
in_be32
(
reg
);
/* UCC1 */
val
|=
0x00003000
;
/* UCC2 */
val
|=
0x0c000000
;
out_be32
(
reg
,
val
);
svid
=
SVR_REV
(
mfspr
(
SVR
));
switch
(
svid
)
{
case
0x0020
:
setbits_be32
((
void
*
)(
CONFIG_SYS_IMMR
+
0x14a8
),
0x0c003000
);
break
;
case
0x0021
:
clrsetbits_be32
((
void
*
)(
CONFIG_SYS_IMMR
+
0x14ac
),
0x00000050
,
0x000000a0
);
break
;
}
/* enable the PHY on the PIGGY */
setbits
(
8
,
(
void
*
)(
CONFIG_SYS_PIGGY_BASE
+
0x10003
),
0x01
);
return
0
;
}
int
misc_init_r
(
void
)
{
/* add board specific i2c busses */
board_init_i2c_busses
();
return
0
;
}
int
fixed_sdram
(
void
)
{
volatile
immap_t
*
im
=
(
immap_t
*
)
CONFIG_SYS_IMMR
;
...
...
@@ -87,16 +117,7 @@ int fixed_sdram(void)
u32
ddr_size
;
u32
ddr_size_log2
;
msize
=
CONFIG_SYS_DDR_SIZE
;
for
(
ddr_size
=
msize
<<
20
,
ddr_size_log2
=
0
;
(
ddr_size
>
1
);
ddr_size
=
ddr_size
>>
1
,
ddr_size_log2
++
)
{
if
(
ddr_size
&
1
)
return
-
1
;
}
im
->
sysconf
.
ddrlaw
[
0
].
ar
=
LAWAR_EN
|
((
ddr_size_log2
-
1
)
&
LAWAR_SIZE
);
im
->
sysconf
.
ddrlaw
[
0
].
ar
=
LAWAR_EN
|
0x1e
;
im
->
ddr
.
csbnds
[
0
].
csbnds
=
CONFIG_SYS_DDR_CS0_BNDS
;
im
->
ddr
.
cs_config
[
0
]
=
CONFIG_SYS_DDR_CS0_CONFIG
;
im
->
ddr
.
timing_cfg_0
=
CONFIG_SYS_DDR_TIMING_0
;
...
...
@@ -112,6 +133,21 @@ int fixed_sdram(void)
udelay
(
200
);
im
->
ddr
.
sdram_cfg
|=
SDRAM_CFG_MEM_EN
;
msize
=
CONFIG_SYS_DDR_SIZE
<<
20
;
disable_addr_trans
();
msize
=
get_ram_size
(
CONFIG_SYS_DDR_BASE
,
msize
);
enable_addr_trans
();
msize
/=
(
1024
*
1024
);
if
(
CONFIG_SYS_DDR_SIZE
!=
msize
)
{
for
(
ddr_size
=
msize
<<
20
,
ddr_size_log2
=
0
;
(
ddr_size
>
1
);
ddr_size
=
ddr_size
>>
1
,
ddr_size_log2
++
)
if
(
ddr_size
&
1
)
return
-
1
;
im
->
sysconf
.
ddrlaw
[
0
].
ar
=
LAWAR_EN
|
((
ddr_size_log2
-
1
)
&
LAWAR_SIZE
);
im
->
ddr
.
csbnds
[
0
].
csbnds
=
(((
msize
/
16
)
-
1
)
&
0xff
);
}
return
msize
;
}
...
...
@@ -156,3 +192,12 @@ void ft_board_setup (void *blob, bd_t *bd)
ft_cpu_setup
(
blob
,
bd
);
}
#endif
#if defined(CONFIG_HUSH_INIT_VAR)
extern
int
ivm_read_eeprom
(
void
);
int
hush_init_var
(
void
)
{
ivm_read_eeprom
();
return
0
;
}
#endif
cpu/mpc83xx/cpu.c
浏览文件 @
014c595f
...
...
@@ -35,6 +35,10 @@
#include <tsec.h>
#include <netdev.h>
#include <fsl_esdhc.h>
#ifdef CONFIG_BOOTCOUNT_LIMIT
#include <asm/immap_qe.h>
#include <asm/io.h>
#endif
DECLARE_GLOBAL_DATA_PTR
;
...
...
@@ -399,3 +403,33 @@ int cpu_mmc_init(bd_t *bis)
return
0
;
#endif
}
#ifdef CONFIG_BOOTCOUNT_LIMIT
#if !defined(CONFIG_MPC8360)
#error "CONFIG_BOOTCOUNT_LIMIT only for MPC8360 implemented"
#endif
#if !defined(CONFIG_BOOTCOUNT_ADDR)
#define CONFIG_BOOTCOUNT_ADDR (0x110000 + QE_MURAM_SIZE - 2 * sizeof(unsigned long))
#endif
#include <asm/io.h>
void
bootcount_store
(
ulong
a
)
{
void
*
reg
=
(
void
*
)(
CONFIG_SYS_IMMR
+
CONFIG_BOOTCOUNT_ADDR
);
out_be32
(
reg
,
a
);
out_be32
(
reg
+
4
,
BOOTCOUNT_MAGIC
);
}
ulong
bootcount_load
(
void
)
{
void
*
reg
=
(
void
*
)(
CONFIG_SYS_IMMR
+
CONFIG_BOOTCOUNT_ADDR
);
if
(
in_be32
(
reg
+
4
)
!=
BOOTCOUNT_MAGIC
)
return
0
;
else
return
in_be32
(
reg
);
}
#endif
/* CONFIG_BOOTCOUNT_LIMIT */
cpu/mpc83xx/fdt.c
浏览文件 @
014c595f
...
...
@@ -32,6 +32,20 @@ extern void ft_qe_setup(void *blob);
DECLARE_GLOBAL_DATA_PTR
;
#if defined(CONFIG_BOOTCOUNT_LIMIT) && defined(CONFIG_MPC8360)
#include <asm/immap_qe.h>
void
fdt_fixup_muram
(
void
*
blob
)
{
ulong
data
[
2
];
data
[
0
]
=
0
;
data
[
1
]
=
QE_MURAM_SIZE
-
2
*
sizeof
(
unsigned
long
);
do_fixup_by_path
(
blob
,
"/qe/muram/data-only"
,
"reg"
,
data
,
sizeof
(
data
),
0
);
}
#endif
void
ft_cpu_setup
(
void
*
blob
,
bd_t
*
bd
)
{
immap_t
*
immr
=
(
immap_t
*
)
CONFIG_SYS_IMMR
;
...
...
@@ -83,4 +97,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
#endif
fdt_fixup_memory
(
blob
,
(
u64
)
bd
->
bi_memstart
,
(
u64
)
bd
->
bi_memsize
);
#if defined(CONFIG_BOOTCOUNT_LIMIT)
fdt_fixup_muram
(
blob
);
#endif
}
cpu/mpc83xx/spd_sdram.c
浏览文件 @
014c595f
...
...
@@ -319,7 +319,20 @@ long int spd_sdram()
ddrc_clk
=
gd
->
mem_clk
/
1000000
;
effective_data_rate
=
0
;
if
(
max_data_rate
>=
390
&&
max_data_rate
<
460
)
{
/* it is DDR 400 */
if
(
max_data_rate
>=
460
)
{
/* it is DDR2-800, 667, 533 */
if
(
spd
.
cas_lat
&
0x08
)
caslat
=
3
;
else
caslat
=
4
;
if
(
ddrc_clk
<=
460
&&
ddrc_clk
>
350
)
effective_data_rate
=
400
;
else
if
(
ddrc_clk
<=
350
&&
ddrc_clk
>
280
)
effective_data_rate
=
333
;
else
if
(
ddrc_clk
<=
280
&&
ddrc_clk
>
230
)
effective_data_rate
=
266
;
else
effective_data_rate
=
200
;
}
else
if
(
max_data_rate
>=
390
&&
max_data_rate
<
460
)
{
/* it is DDR 400 */
if
(
ddrc_clk
<=
460
&&
ddrc_clk
>
350
)
{
/* DDR controller clk at 350~460 */
effective_data_rate
=
400
;
/* 5ns */
...
...
@@ -466,6 +479,8 @@ long int spd_sdram()
}
else
{
twr_clk
=
picos_to_clk
(
spd
.
twr
*
250
);
twtr_clk
=
picos_to_clk
(
spd
.
twtr
*
250
);
if
(
twtr_clk
<
2
)
twtr_clk
=
2
;
}
/*
...
...
@@ -529,7 +544,7 @@ long int spd_sdram()
if
(
spd
.
mem_type
==
SPD_MEMTYPE_DDR2
&&
(
odt_wr_cfg
||
odt_rd_cfg
)
&&
(
caslat
<
4
))
{
add_lat
=
trcd_clk
-
1
;
add_lat
=
4
-
caslat
;
if
((
add_lat
+
caslat
)
<
4
)
{
add_lat
=
0
;
}
...
...
@@ -566,6 +581,9 @@ long int spd_sdram()
/* Convert SPD value from quarter nanos to picos. */
trtp_clk
=
picos_to_clk
(
spd
.
trtp
*
250
);
if
(
trtp_clk
<
2
)
trtp_clk
=
2
;
trtp_clk
+=
add_lat
;
cke_min_clk
=
3
;
/* By the book. */
four_act
=
picos_to_clk
(
37500
);
/* By the book. 1k pages? */
...
...
@@ -579,7 +597,9 @@ long int spd_sdram()
if
(
spd
.
mem_type
==
SPD_MEMTYPE_DDR2
)
{
if
(
effective_data_rate
==
266
)
{
cpo
=
0x4
;
/* READ_LAT + 1/2 */
}
else
if
(
effective_data_rate
==
333
||
effective_data_rate
==
400
)
{
}
else
if
(
effective_data_rate
==
333
)
{
cpo
=
0x6
;
/* READ_LAT + 1 */
}
else
if
(
effective_data_rate
==
400
)
{
cpo
=
0x7
;
/* READ_LAT + 5/4 */
}
else
{
/* Automatic calibration */
...
...
drivers/i2c/fsl_i2c.c
浏览文件 @
014c595f
...
...
@@ -42,6 +42,9 @@ DECLARE_GLOBAL_DATA_PTR;
#define CONFIG_SYS_SPD_BUS_NUM 0
#endif
static
unsigned
int
i2c_bus_num
__attribute__
((
section
(
".data"
)))
=
CONFIG_SYS_SPD_BUS_NUM
;
#if defined(CONFIG_I2C_MUX)
static
unsigned
int
i2c_bus_num_mux
__attribute__
((
section
(
"data"
)))
=
0
;
#endif
static
unsigned
int
i2c_bus_speed
[
2
]
=
{
CONFIG_SYS_I2C_SPEED
,
CONFIG_SYS_I2C_SPEED
};
...
...
@@ -369,6 +372,19 @@ i2c_probe(uchar chip)
int
i2c_set_bus_num
(
unsigned
int
bus
)
{
#if defined(CONFIG_I2C_MUX)
if
(
bus
<
CONFIG_SYS_MAX_I2C_BUS
)
{
i2c_bus_num
=
bus
;
}
else
{
int
ret
;
ret
=
i2x_mux_select_mux
(
bus
);
if
(
ret
)
return
ret
;
i2c_bus_num
=
0
;
}
i2c_bus_num_mux
=
bus
;
#else
#ifdef CONFIG_SYS_I2C2_OFFSET
if
(
bus
>
1
)
{
#else
...
...
@@ -378,7 +394,7 @@ int i2c_set_bus_num(unsigned int bus)
}
i2c_bus_num
=
bus
;
#endif
return
0
;
}
...
...
@@ -396,7 +412,11 @@ int i2c_set_bus_speed(unsigned int speed)
unsigned
int
i2c_get_bus_num
(
void
)
{
#if defined(CONFIG_I2C_MUX)
return
i2c_bus_num_mux
;
#else
return
i2c_bus_num
;
#endif
}
unsigned
int
i2c_get_bus_speed
(
void
)
...
...
include/configs/MPC8349ITX.h
浏览文件 @
014c595f
...
...
@@ -99,6 +99,7 @@
#define CONFIG_SYS_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100
#define CONFIG_SYS_SPD_BUS_NUM 1
/* The I2C bus for SPD */
#define CONFIG_SYS_RTC_BUS_NUM 1
/* The I2C bus for RTC */
#define CONFIG_SYS_I2C_8574_ADDR1 0x20
/* I2C1, PCF8574 */
#define CONFIG_SYS_I2C_8574_ADDR2 0x21
/* I2C1, PCF8574 */
...
...
@@ -168,6 +169,9 @@
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075)
#define CONFIG_VERY_BIG_RAM
#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20)
#ifdef CONFIG_HARD_I2C
#define CONFIG_SPD_EEPROM
/* use SPD EEPROM for DDR setup*/
#endif
...
...
@@ -457,6 +461,7 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_SDRAM
#if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114)
...
...
include/configs/keymile-common.h
浏览文件 @
014c595f
...
...
@@ -42,13 +42,9 @@
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
/* should go away, if kmeter I2C support is enabled */
#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGSUVD)
#define CONFIG_CMD_DTT
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#endif
#undef CONFIG_WATCHDOG
/* disable platform specific watchdog */
...
...
@@ -73,10 +69,7 @@
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Boot Argument Buffer Size */
#define CONFIG_CMDLINE_EDITING 1
/* add command line history */
/* should go away, if kmeter I2C support is enabled */
#if defined(CONFIG_MGCOGE) || defined(CONFIG_MGSUVD)
#define CONFIG_HUSH_INIT_VAR 1
#endif
#define CONFIG_SYS_ALT_MEMTEST
/* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START 0x00100000
/* memtest works on */
...
...
include/configs/kmeter1.h
浏览文件 @
014c595f
...
...
@@ -28,10 +28,12 @@
#define CONFIG_MPC83XX 1
/* MPC83XX family */
#define CONFIG_MPC8360 1
/* MPC8360 CPU specific */
#define CONFIG_KMETER1 1
/* KMETER1 board specific */
#define CONFIG_HOSTNAME kmeter1
/* include common defines/options for all Keymile boards */
#include "keymile-common.h"
#define CONFIG_MISC_INIT_R 1
/*
* System Clock Setup
*/
...
...
@@ -51,10 +53,11 @@
#define CONFIG_SYS_HRCW_HIGH (\
HRCWH_CORE_ENABLE | \
HRCWH_FROM_0X00000100 | \
HRCWH_BOOTSEQ_
NORMAL
| \
HRCWH_BOOTSEQ_
DISABLE
| \
HRCWH_SW_WATCHDOG_DISABLE | \
HRCWH_ROM_LOC_LOCAL_16BIT | \
HRCWH_BIG_ENDIAN | \
HRCWH_LALE_EARLY | \
HRCWH_LDP_CLEAR )
/*
...
...
@@ -91,8 +94,8 @@
* Manually set up DDR parameters
*/
#define CONFIG_DDR_II
#define CONFIG_SYS_DDR_SIZE 2
56
/* MB */
#define CONFIG_SYS_DDR_CS0_BNDS 0x000000
0
f
#define CONFIG_SYS_DDR_SIZE 2
048
/* MB */
#define CONFIG_SYS_DDR_CS0_BNDS 0x000000
7
f
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
CSCONFIG_ROW_BIT_13 | \
CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
...
...
@@ -101,11 +104,12 @@
SDRAM_CFG_SREN)
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
#define CONFIG_SYS_DDR_INTERVAL ((0x
10
0 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
(0x
406
<< SDRAM_INTERVAL_REFINT_SHIFT))
#define CONFIG_SYS_DDR_INTERVAL ((0x
08
0 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
(0x
3cf
<< SDRAM_INTERVAL_REFINT_SHIFT))
#define CONFIG_SYS_DDR_MODE 0x04440242
#define CONFIG_SYS_DDR_MODE2 0x00800000
#define CONFIG_SYS_DDRCDR 0x40000001
#define CONFIG_SYS_DDR_MODE 0x47860452
#define CONFIG_SYS_DDR_MODE2 0x8080c000
#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
...
...
@@ -116,22 +120,22 @@
(0 << TIMING_CFG0_WRT_SHIFT) | \
(0 << TIMING_CFG0_RWT_SHIFT))
#define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_
4
0) | \
#define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_
5
0) | \
( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
(
1
<< TIMING_CFG1_ACTTOACT_SHIFT) | \
(
2
<< TIMING_CFG1_WRREC_SHIFT) | \
(
2
<< TIMING_CFG1_REFREC_SHIFT) | \
(
2
<< TIMING_CFG1_ACTTORW_SHIFT) | \
(
6
<< TIMING_CFG1_ACTTOPRE_SHIFT) | \
(
2
<< TIMING_CFG1_PRETOACT_SHIFT))
#define CONFIG_SYS_DDR_TIMING_2 ((
5
<< TIMING_CFG2_FOUR_ACT_SHIFT) | \
(
2
<< TIMING_CFG1_ACTTOACT_SHIFT) | \
(
3
<< TIMING_CFG1_WRREC_SHIFT) | \
(
7
<< TIMING_CFG1_REFREC_SHIFT) | \
(
3
<< TIMING_CFG1_ACTTORW_SHIFT) | \
(
8
<< TIMING_CFG1_ACTTOPRE_SHIFT) | \
(
3
<< TIMING_CFG1_PRETOACT_SHIFT))
#define CONFIG_SYS_DDR_TIMING_2 ((
8
<< TIMING_CFG2_FOUR_ACT_SHIFT) | \
(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
(
1
<< TIMING_CFG2_RD_TO_PRE_SHIFT) | \
(
3
<< TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
(
2
<< TIMING_CFG2_RD_TO_PRE_SHIFT) | \
(
4
<< TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
(0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
(
4
<< TIMING_CFG2_CPO_SHIFT))
(
5
<< TIMING_CFG2_CPO_SHIFT))
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
...
...
@@ -141,9 +145,10 @@
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
/* start of monitor */
#define CONFIG_SYS_FLASH_BASE 0xF0000000
#define CONFIG_SYS_FLASH_BASE_1 0xF2000000
#define CONFIG_SYS_PIGGY_BASE 0x80000000
#define CONFIG_SYS_PIGGY_BASE 0xE8000000
#define CONFIG_SYS_PIGGY_SIZE 128
#define CONFIG_SYS_PAXE_BASE 0xA0000000
#define CONFIG_SYS_PAXE_SIZE
256
#define CONFIG_SYS_PAXE_SIZE
512
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
...
...
@@ -151,7 +156,7 @@
#undef CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_MONITOR_LEN (
256
* 1024)
/* Reserve 256 kB for Mon */
#define CONFIG_SYS_MONITOR_LEN (
384
* 1024)
/* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
/* Reserved for malloc */
/*
...
...
@@ -174,8 +179,8 @@
* Bank Bus Machine PortSz Size Device
* ---- --- ------- ------ ----- ------
* 0 Local GPCM 16 bit 256MB FLASH
* 1 Local GPCM 8 bit
256K
B GPIO/PIGGY
* 3 Local GPCM 8 bit
256
MB PAXE
* 1 Local GPCM 8 bit
128M
B GPIO/PIGGY
* 3 Local GPCM 8 bit
512
MB PAXE
*
*/
/*
...
...
@@ -209,12 +214,12 @@
* PRIO1/PIGGY on the local bus CS1
*/
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE
/* Window base at flash base */
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001
1
/* 256K
B window size */
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001
A
/* 128M
B window size */
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \
(1 << BR_PS_SHIFT) |
/* 8 bit port size */
\
BR_V)
#define CONFIG_SYS_OR1_PRELIM (
0xfffc0000 |
/* 256K
B */
\
#define CONFIG_SYS_OR1_PRELIM (
MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) |
/* 128M
B */
\
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_2 | \
OR_GPCM_TRLX | OR_GPCM_EAD)
...
...
@@ -223,7 +228,7 @@
* PAXE on the local bus CS3
*/
#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE
/* Window base at flash base */
#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001
b
/* 256
MB window size */
#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001
C
/* 512
MB window size */
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \
(1 << BR_PS_SHIFT) |
/* 8 bit port size */
\
...
...
@@ -296,10 +301,42 @@
#else
/* CFG_RAMBOOT */
#define CONFIG_SYS_NO_FLASH 1
/* Flash is not usable now */
#define CONFIG_ENV_IS_NOWHERE 1
/* Store ENV in memory only */
#define CONFIG_ENV_ADDR (C
FG
_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_ADDR (C
ONFIG_SYS
_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
/* CFG_RAMBOOT */
/* I2C */
#define CONFIG_HARD_I2C
/* I2C with hardware support */
#undef CONFIG_SOFT_I2C
/* I2C bit-banged */
#define CONFIG_FSL_I2C
#define CONFIG_SYS_I2C_SPEED 200000
/* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x3000
#define CONFIG_I2C_MULTI_BUS 1
#define CONFIG_I2C_CMD_TREE 1
#define CONFIG_SYS_MAX_I2C_BUS 2
#define CONFIG_I2C_MUX 1
/* EEprom support */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_MULTI_EEPROMS 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
/* Support the IVM EEprom */
#define CONFIG_SYS_IVM_EEPROM_ADR 0x50
#define CONFIG_SYS_IVM_EEPROM_MAX_LEN 0x400
#define CONFIG_SYS_IVM_EEPROM_PAGE_LEN 0x100
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
#define CONFIG_DTT_LM75 1
/* ON Semi's LM75 */
#define CONFIG_DTT_SENSORS {0, 1, 2, 3}
/* Sensor addresses */
#define CONFIG_SYS_DTT_MAX_TEMP 70
#define CONFIG_SYS_DTT_LOW_TEMP -30
#define CONFIG_SYS_DTT_HYSTERESIS 3
#define CONFIG_SYS_DTT_BUS_NUM (2)
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
#endif
...
...
@@ -345,7 +382,7 @@
/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_
256K
| BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_
128M
| BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
...
...
@@ -365,7 +402,7 @@
/* PAXE: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256
K
| BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256
M
| BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
...
...
@@ -401,16 +438,25 @@
#define BOOTFLAG_COLD 0x01
/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02
/* Software reboot */
#define BOOTFLASH_START F0000000
#define CONFIG_PRAM 512
/* protected RAM [KBytes] */
#define MTDIDS_DEFAULT "nor0=app"
#define MTDPARTS_DEFAULT \
"mtdparts=app:256k(u-boot),128k(env),128k(envred)," \
"1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var),768k(cfg)"
/*
* Environment Configuration
*/
#define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_UEC_ETH)
#define CONFIG_HAS_ETH0
#ifndef CONFIG_KM_DEF_ENV
/* if not set by keymile-common.h */
#define CONFIG_KM_DEF_ENV "km-common=empty\0"
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
CONFIG_KM_DEF_ENV \
"netdev=eth0\0" \
"rootpath=/opt/eldk/ppc_82xx\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
...
...
@@ -452,6 +498,14 @@
"loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0" \
"loadkernel=tftp ${kernel_addr_r} ${boot_file}\0" \
"unlock=yes\0" \
"EEprom_ivm=pca9547:70:9\0" \
"dtt_bus=pca9547:70:a\0" \
"mtdids=nor0=app \0" \
"mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0" \
""
#if defined(CONFIG_UEC_ETH)
#define CONFIG_HAS_ETH0
#endif
#endif
/* __CONFIG_H */
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