- 01 6月, 2017 3 次提交
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git://git.denx.de/u-boot-mips由 Tom Rini 提交于
Please pull another update for Broadcom MIPS. This contains new SoC's, new boards and new drivers and some bugfixes.
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git://www.denx.de/git/u-boot-marvell由 Tom Rini 提交于
Mostly including the Armada 37xx pinctrl / gpio driver.
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由 Daniel Thompson 提交于
Currently these (board agnostic) commands cannot be selected using menuconfig and friends. Fix this the obvious way. As part of this, don't muddle the meaning of CONFIG_HASH_VERIFY to mean both 'hash -v' and "we have a hashing command" as this makes the Kconfig logic odd. Signed-off-by: NDaniel Thompson <daniel.thompson@linaro.org> [trini: Re-apply, add imply for a few cases, run moveconfig.py, also migrate CRC32_VERIFY] Signed-off-by: NTom Rini <trini@konsulko.com>
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- 31 5月, 2017 37 次提交
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由 Álvaro Fernández Rojas 提交于
Instead of having a peripheral clock of 50 MHz like the BCM63xx family, it has a 48 MHz clock. This fixes uart baud rate calculation for BCM3380. Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com>
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由 Álvaro Fernández Rojas 提交于
Now that the uart driver has been fixed we support more baud rates. Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com>
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由 Álvaro Fernández Rojas 提交于
It's currently bugged and doesn't work for even cases. Right shift bits instead of dividing and fix even cases. Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com>
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由 Álvaro Fernández Rojas 提交于
I missed this when I added support for BMIPS UART driver and it's needed to achieve a real 115200 8N1 setup. Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com>
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由 Álvaro Fernández Rojas 提交于
Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Álvaro Fernández Rojas 提交于
Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Álvaro Fernández Rojas 提交于
Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Álvaro Fernández Rojas 提交于
BCM6338 has a fixed CPU frequency of 240 MHz. Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Álvaro Fernández Rojas 提交于
Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Álvaro Fernández Rojas 提交于
Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Álvaro Fernández Rojas 提交于
As far as I know BCM3380 has a fixed CPU frequency since I couldn't find its PLL registers in any documentation. Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Álvaro Fernández Rojas 提交于
Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Álvaro Fernández Rojas 提交于
Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Álvaro Fernández Rojas 提交于
Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Álvaro Fernández Rojas 提交于
This is done in order to reuse ram size calculation for BCM6338/BCM6348 Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Álvaro Fernández Rojas 提交于
Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Álvaro Fernández Rojas 提交于
Use a generic name for cpu_desc functions instead of using a specific SoC one. Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Álvaro Fernández Rojas 提交于
This driver allows rebooting the SoC by calling wdt_expire_now op. Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Álvaro Fernández Rojas 提交于
This driver allows rebooting the SoC by calling wdt_expire_now op. Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Álvaro Fernández Rojas 提交于
This driver allows rebooting the SoC by calling wdt_expire_now op. Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Álvaro Fernández Rojas 提交于
Add a new sysreset driver that uses the recently added watchdog support. It performs a full SoC reset by calling wdt_expire_now op. Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Álvaro Fernández Rojas 提交于
This driver controls the watchdog present on this SoC. Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Álvaro Fernández Rojas 提交于
This driver controls the watchdog present on this SoC. Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Álvaro Fernández Rojas 提交于
This driver controls the watchdog present on this SoC. Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Álvaro Fernández Rojas 提交于
This driver is a simplified version of linux/drivers/watchdog/bcm63xx_wdt.c Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Patrick Wildt 提交于
image_version_file()'s only use is to return the version number of the specified image, and it's only called by kwbimage_generate(). This version function mallocs "image_cfg" and reads the contents of the image into that buffer. Before return to its caller it frees the buffer. After extracting the version, kwb_image_generate() tries to calculate the header size by calling image_headersz_v1(). This function now accesses "image_cfg", which has already been freed. Since image_version_file() is only used by a single function, inline it into kwbimage_generate() and only free the buffer after it is no longer needed. This also improves code readability since the code is mostly equal to kwbimage_set_header(). Signed-off-by: NPatrick Wildt <patrick@blueri.se> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Patrick Wildt 提交于
Switch Clearfog to the generic distro defaults. This has been taken from a Debian mailing list thread: https://lists.debian.org/debian-boot/2016/10/msg00026.htmlSigned-off-by: NPatrick Wildt <patrick@blueri.se> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Patrick Wildt 提交于
Use GPIO19 which is wired to the uSOM phy reset signal in order to reset the uSOM's 1512 Gigabit Ethernet phy. This GPIO is valid on ClearFog rev 2.1 and newer. Taken from SolidRun's specialised u-boot, see https://github.com/SolidRun/u-boot-armada38x/commit/f906e3df172e07ac82cdd87b278d7896949262eaSigned-off-by: NPatrick Wildt <patrick@blueri.se> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
The dram_init and dram_init_banksize functions were using a board specific implementation for decoding the memory banks from the fdt. This change makes the dram_init* functions use a generic implementation of decoding and populating memory bank and size data. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Nathan Rossi <nathan@nathanrossi.com> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
This patch enables the mvpp2 port 0 usage on the Armada 7k DB by setting the correct PHY type (KR / SFI) for the COMPHY driver and enabling the ethernet0 device node in the dts. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Stefan Chulski <stefanc@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com>
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由 Stefan Roese 提交于
This patch enable the PINCTRL and GPIO support, including the GPIO command on the Armada 3720 DB. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Konstantin Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com>
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由 Stefan Roese 提交于
To enable support for the Armada 37xx pinctrl driver, we need to change the Kconfig symbol for the Armada 7k/8k pinctrl driver and its dependencies to distinguish between both platforms and drivers. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Konstantin Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com>
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由 Gregory CLEMENT 提交于
GPIO management is pretty simple and is part of the same IP than the pin controller for the Armada 37xx SoCs. This patch adds the GPIO support to the pinctrl-armada-37xx.c file, it also allows sharing common functions between the gpio and the pinctrl drivers. Ported to U-Boot based on the Linux version by Stefan Roese. Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com>
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由 Gregory CLEMENT 提交于
The Armada 37xx SoC come with 2 pin controllers: one on the south bridge (managing 28 pins) and one on the north bridge (managing 36 pins). At the hardware level the controller configure the pins by group and not pin by pin. This constraint is reflected in the design of the driver: only the group related functions are implemented. Ported to U-Boot based on the Linux version by Stefan Roese. Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com>
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由 Gregory CLEMENT 提交于
Start to populate the device tree of the Armada 37xx with the pincontrol configuration used on the board providing a dts. Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com>
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由 Gregory CLEMENT 提交于
Add the nodes for the two pin controller present in the Armada 37xx SoCs. Initially the node was named gpio1 using the same name that for the register range in the datasheet. However renaming it pinctr_nb (nb for North Bridge) makes more sens. Minor changes for U-Boot because of the slightly different dts version done by Stefan Roese. Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: NStefan Roese <sr@denx.de> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Konstantin Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com>
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