Pull slightly modified version of Documentation/DocBook, the related perl
script scripts/kernel-doc and the scripts/docproc.c from Linux kernel and
implant it into U-Boot. This will allow smooth generation of kerneldoc
style documentation.

It was necessary to modify the DocBook/Makefile to work with U-Boot build
system. The changes were only minor though and involved replacing the kbuild
specific parts.

It was also necessary to replace use of variables like KERNEL_VERSION with
U_BOOT_VERSION, strings like Linux kernel with U-Boot Bootloader etc. so
the generated result actually matches.

Finally, it was necessary to adjust docproc.c, since the documentation in
U-Boot is located in doc/DocBook instead of Documentation/DocBook as is in
case of the Linux kernel.

Some parts of the DocBook Makefile are unused, but to allow easier sync with
Linux kernel, these parts are still left in. The targets enabled now are
"htmldocs" "pdfdocs" "psdocs" "xmldocs" and "cleandocs" to remove the results
of documentation build.

Linux scripts/docproc.c:
commit f0f3ca8d967462dafb815412b14ca3339b9817a6
Date:   Wed Jun 15 11:53:13 2011 +0200

Linux scripts/kernel-doc:
commit 1b40c1944db445c1de1c47ffd8cd426167f488e8
Date:   Sun Aug 12 10:46:15 2012 +0200

Linux Documentation/DocBook:
commit bb8187d35f820671d6dd76700d77a6b55f95e2c5
Date:   Thu May 17 19:06:13 2012 -0400
Signed-off-by: NMarek Vasut <marex@denx.de>

Since commit 50d4a707f0 (mx5/6: Define default SoC input clock frequencies)
we can use the default clock values.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

mx6qsabreauto has a AR8031 Gigabit PHY.

Add support for it.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Clean up mx25 lowlevel_init:
 - Add comments.
 - Do not use write32 repeatedly with the same value in order not to increase
   code size.
 - Make register values configurable.
 - Use macro parameters with default values instead of literal constants.
 - Use defined macros instead of duplicating code.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: John Rigby <jcrigby@gmail.com>
Cc: Matthias Weisser <weisserm@arcor.de>

The CSI PODF bit-field used by the previous code for the i.MX31 CCM PDR0
register is actually composed of two bit-fields: one pre-divider and one
post-divider. This patch fixes the CCM access macros and the code using them
accordingly.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>

Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>

Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>

Optimize mx5 lowlevel_init.S code size:
 - Compute values at compile time rather than at runtime where possible.
 - Assign r4 to hold the zero value rather than setting registers to 0 again and
   again.
 - Associate a function to setup_pll rather than expanding its large macro code
   multiple times.
 - Allocate constant values in section only if used.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Tested-by: NStefano Babic <sbabic@denx.de>
Acked-by: NStefano Babic <sbabic@denx.de>

The mx6qsabreauto console is different than mx6qsabresd so the console
configuration is now set in the board file.
Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>
Acked-by: NStefano Babic <sbabic@denx.de>

The MMC driver appropriate for the i.MX25 is fsl_esdhc, which has nothing to do
with mxcmmc.

Also, each eSDHC instance has a dedicated clock, so gd->sdhc_clk must be set
accordingly. This is good for the case only a single SDHC instance is used
(initialization made with fsl_esdhc_mmc_init()). A future patch will fix the
multi-instance use case (initialization made directly with
fsl_esdhc_initialize()).
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Eric Bénard <eric@eukrea.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>

The FEC is the only SoC Ethernet support available on i.MX25, so define
cpu_eth_init() only for it instead of returning a misleading success code.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>

Use the standard mxc_get_clock() instead of exporting internal functions and
using literal constant values.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>

mxc_get_clock(MXC_FEC_CLK) should return the IPG clock, not the AHB clock.

Also, imx_get_fecclk() was correct but reimplemented the calculation of the IPG
clock, so remove the duplicated code.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>

Define AHB, IPG and CSPI clocks.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>

Avoid possible overflow in clock calculations, and do not waste calls to lldiv()
to divide simple ulongs.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>

The MFN bit-field of the PLL registers represents a signed value. See the
reference manual.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>

The i.MX5 eSDHC clocks were considered as coming from the IPG clock although
they have dedicated clock paths.

Also, on i.MX5/6, each SDHC instance has a dedicated clock, so gd->sdhc_clk must
be set accordingly. This is good for the case only a single SDHC instance is
used (initialization made with fsl_esdhc_mmc_init()). A future patch will fix
the multi-instance use case (initialization made directly with
fsl_esdhc_initialize()).
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Eric Bénard <eric@eukrea.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>

There are only 2 I²C instances on i.MX51, but 3 on i.MX53.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>

The FEC clock does not come from PLL1, but from the IPG clock. The previous code
was even inconsistent with itself, returning the IPG clock as expected for
imx_get_fecclk(), but the PLL1 clock for mxc_get_clock(MXC_FEC_CLK).
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>

The code handling the dividers was duplicated for each possible input clock, and
this function can benefit from the newly introduced get_standard_pll_sel_clk()
function instead of duplicating this mux handling code.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>

This function returned 66500000 instead of the correct lp_apm clock frequency if
the CCM.CSCMR1.uart_clk_sel mux is set to 3.

This patch fixes this issue by introducing the get_standard_pll_sel_clk()
function that will be used by future patches to handle identical muxes used by
many other clocks.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>

This fixes the "IPG PERCLK" frequency printed by the clocks command. The issue
was that get_ipg_per_clk() used periph_clk instead of lp_apm in the case
CCM.CBCMR.perclk_lp_apm_sel is set.

It also fixes I²C support.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>

In the case periph_clk comes from periph_apm_clk, the latter is selected by the
CCM.CBCMR.periph_apm_sel mux, which can source the lp_apm clock from its
input ♯2. get_periph_clk() returned 0 instead of the lp_apm clock frequency in
this case.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>

If CCM.CCSR.lp_apm is set, the lp_apm clock is not necessarily 32768 Hz x 1024.
In that case:
 - on i.MX51, this clock comes from the output of the FPM,
 - on i.MX53, this clock comes from the output of PLL4.

This patch fixes the code accordingly.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>

This fixes config_pll_clk(), which used 0x20 instead of 0x200 for PLL4_CLOCK.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>

The i.MX51 has a single USB PHY clock, while the i.MX53 has two. These 3 clocks
have different clock gate control bit-fields.

The existing code was correct only for i.MX53, so this patch fixes the i.MX51
use case.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Jana Rapava <fermata7@gmail.com>
Cc: Wolfgang Grandegger <wg@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>

The clock gate values are 2-bit bit-fields. Hence, setting or clearing only one
of these bits like what was done is wrong and can lead to unpredictable behavior
depending on the original value of these bit-fields.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>

Use clock gate definitions having names showing clearly the gated clock instead
of names giving only a register field index.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>

Clean up the i.MX5 clock driver:
 - Use readl() and writel() instead of their __raw_ counterparts.
 - Use the clr/setbits_le32() family of macros rather than expanding code.
 - Use accessor macros for bit-fields instead of _MASK and _OFFSET.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>

Define default SoC input clock frequencies for i.MX5/6 in order to get rid of
duplicated definitions.
Signed-off-by: NBenoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Jason Liu <r64343@freescale.com>
Cc: Matt Sealey <matt@genesi-usa.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>

i2c didn't work on imx25 due to missing MXC_IPG_PERCLK. Now using
MXC_I2C_CLK on all imx systems using i2c.
Signed-off-by: NMatthias Weisser <weisserm@arcor.de>
Acked-by: NStefano Babic <sbabic@denx.de>

tested on a MCIMX257CJM4A which now reports :
CPU:   Freescale i.MX25 rev1.2 at 399 MHz
Signed-off-by: NEric Bénard <eric@eukrea.com>
Acked-by: NOtavio Salvador <otavio@ossystems.com.br>

mx6qsabreauto is a board based on mx6q SoC with the following features:
- 2GB of DDR3
- 2 USB ports
- 1 HDMI output port
- SPI NOR
- 2 LVDS LCD ports
- Gigabit Ethernet
- Camera
- eMMC and SD card slot
- Multichannel Audio
- CAN
- SATA
- NAND
- PCIE
- Video Input

Add very basic support for it.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Add a common mx6 config file that can be shared between some mx6 boards.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com>

Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com>
Acked-by: NStefano Babic <sbabic@denx.de>

Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com>
Acked-by: NStefano Babic <sbabic@denx.de>

Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com>

Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com>

Register CCM_CHSCCDR (offset 0x34 in CCM) is named CCM_CHSCCDR in
reference manual, but was named chscdr in struct mxc_ccm_reg.
Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com>