- 26 12月, 2019 6 次提交
-
-
由 Tom Rini 提交于
- Update maintainer on omapl138_lcdk - Match TRM sequence & settings in the TI pipe3 PHY
-
由 Lokesh Vutla 提交于
As per the email discussion[0], add myself as a maintainer to OMAPL138_LCDK and drop Peter's entry. [0] http://u-boot.10912.n7.nabble.com/OMAP-L138-LCDK-giving-up-maintainership-td394211.htmlSigned-off-by: NLokesh Vutla <lokeshvutla@ti.com>
-
由 Roger Quadros 提交于
As per "Table 26-7. SATA PHY Subsystem Low-Level Programming Sequence" in TRM [1] we need to turn on SATA_PHY_TX before SATA_PHY_RX. [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdfSigned-off-by: NRoger Quadros <rogerq@ti.com>
-
由 Roger Quadros 提交于
For increased DPLL stability use the settings recommended in the TRM [1] for PHY_RX registers for SATA and USB. For SATA we need to use spread spectrum settings even though we don't have spread spectrum enabled. The suggested non-spread spectrum settings don't work. [1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdfSigned-off-by: NRoger Quadros <rogerq@ti.com>
-
由 Roger Quadros 提交于
Introduce a mode property in the driver data so that we don't have to keep using "of_device_is_compatible()" throughtout the driver. No functional change. Signed-off-by: NRoger Quadros <rogerq@ti.com>
-
由 Roger Quadros 提交于
The AM572x Technical Reference Manual, SPRUHZ6H, Revised November 2016 [1], shows recommended settings for the SATA DPLL in Table 26-8. DPLL CLKDCOLDO Recommended Settings. Use those settings in the driver. The TRM does not show a value for 20MHz SYS_CLK so we use something close to the 26MHz setting. [1] - http://www.ti.com/lit/ug/spruhz6h/spruhz6h.pdfSigned-off-by: NRoger Quadros <rogerq@ti.com>
-
- 22 12月, 2019 5 次提交
-
-
-
https://gitlab.denx.de/u-boot/custodians/u-boot-net由 Tom Rini 提交于
- Fix phy_connect() call in two drivers - fw_setenv bugfix
-
由 Jagan Teki 提交于
DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface initialization code would handle them properly along with UNKNOWN type by default if none of the user/board doesn't need to use the phy interfaces at all. The current code is masking the 8/16-bit UTMI+ interface bits globally which indeed effect the UNKNOWN cases, therefore it effects the platforms which are not using phy interfaces at all. So, handle the phy masking bits accordingly on respective interface type cases. Fixes: 6b7ebff0 ("usb: dwc3: Add phy interface for dwc3_uboot") Reported-by: NAndy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
-
由 Heinrich Schuchardt 提交于
Marek is already maintaining USB. Assign files common/usb.c and common/usb_kbd.c to him. Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
-
由 Vignesh Raghavendra 提交于
Since, commit 62f9b654 ("common: Move older CPU functions to their own header") cache ops functions are declared in a separate header. Include the same to avoid build warnings. Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>
-
- 21 12月, 2019 3 次提交
-
-
由 Rasmus Villemoes 提交于
In the case where one deletes an already-non-existing variable, or sets a variable to the value it already has, there is no point in writing the environment back, thus reducing wear on the underlying storage device. In the case of redundant environments, if the two environments differ (e.g. because one is corrupt), make sure that any call of fw_setenv causes the two to become synchronized, even if the fw_setenv call does not change anything in the good copy. Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
-
由 Alex Marginean 提交于
Passing 0 to PHY connect used to trigger a MDIO scan due to a bug fixed in the meantime. It's unclear if bcm-sf2 wants to connect to PHY @ addr 0 or is scanning the bus, passing -1 here should keep it functional either way. Signed-off-by: NAlex Marginean <alexandru.marginean@nxp.com> Cc: Jiandong Zheng <jdzheng@broadcom.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
-
由 Marek Vasut 提交于
PHY address 0 is a valid PHY address, to scan for all PHYs, pass -1 to phy_connect(). Passing 0 used to work before be accident, but does no longer. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: NPatrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NRamon Fried <rfried.dev@gmail.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
-
- 18 12月, 2019 4 次提交
-
-
https://gitlab.denx.de/u-boot/custodians/u-boot-stm由 Tom Rini 提交于
- Fix stm32mp1 crash (bootstage) and warning (cls)
-
由 Patrick Delaunay 提交于
Rsync all defconfig files using moveconfig.py Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Acked-by: NPatrick Delaunay <patrick.delaunay@st.com>
-
由 Patrick Delaunay 提交于
This patch is only a temporarily workaround for crash introduced by commit ac9cd480 ("bootstage: Correct relocation algorithm"). The crash occurs because the bootstage struct is not correctly aligned when BOOTSTAGE feature is activated. Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Acked-by: NPatrick Delaunay <patrick.delaunay@st.com>
-
由 Patrick Delaunay 提交于
Activate by default the command CLS (clear screen); this command used in pxe or sysboot command (DISTRO support) when the "menu background" keyword is present. This patch avoid the warning "Unknown command 'cls'" with extlinux.conf: # Generic Distro Configuration file generated by OpenEmbedded menu title Select the boot mode MENU BACKGROUND /splash.bmp TIMEOUT 20 DEFAULT stm32mp157c-ev1-emmc LABEL stm32mp157c-ev1-emmc KERNEL /uImage FDT /stm32mp157c-ev1.dtb APPEND root=/dev/mmcblk1p4 rootwait rw console=ttySTM0,115200 ... Retrieving file: /mmc0_stm32mp157c-ev1_extlinux/extlinux.conf 614 bytes read in 36 ms (16.6 KiB/s) Retrieving file: /splash.bmp 46180 bytes read in 40 ms (1.1 MiB/s) Unknown command 'cls' - try 'help' Select the boot mode 1: stm32mp157c-ev1-sdcard ... Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Acked-by: NPatrick Delaunay <patrick.delaunay@st.com>
-
- 16 12月, 2019 1 次提交
-
-
由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@konsulko.com>
-
- 14 12月, 2019 8 次提交
-
-
由 Tom Rini 提交于
- Assorted minor fixes
-
由 Grygorii Strashko 提交于
Move BOOTP_DNS2 and PHY_TI from dra7xx_evm.h to dra7xx_evm_defconfig. Signed-off-by: NGrygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: NLokesh Vutla <lokeshvutla@ti.com>
-
由 Heinrich Schuchardt 提交于
With commit 37db55b7 ("linux/types.h: fix typo unchar") we have a duplicate typedef for uchar. As linux/types.h is included in common.h we don't need another typedef for uchar there. Fixes: 37db55b7 ("linux/types.h: fix typo unchar") Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com>
-
由 Heinrich Schuchardt 提交于
Describe that a signature node can be added to a binary device tree using the mkimage tool. Provide an example device tree node. Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
-
由 Heinrich Schuchardt 提交于
Boris' email address has changed. Copy two entries from the Linux .mailmap file. Boris confirmed the new email address: https://lists.denx.de/pipermail/u-boot/2019-December/393774.html Cc: Boris Brezillon <bbrezillon@kernel.org> Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
-
由 Rasmus Villemoes 提交于
Commit 656d8da9 (doc: Remove duplicated documentation directory) got rid of most of Documentation/. But there's still an obviously useless .gitignore left behind. Also, there's a copy of the linux kernel's net/ethernet.txt binding imported from v5.0, while the existing one in doc/ is from 4.0-rc1. So replace the latter by the former, and making Documentation/ finally empty. Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: NSimon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
-
由 Rasmus Villemoes 提交于
Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk>
-
由 Hannes Schmelzer 提交于
commit 3b3e8a37 ("arm: dts: am335x: sync cpsw/mdio/phy with latest linux - drop phy_id") did sync with recent linux kernel and replaced therefore the 'phy_id' property with a phy-handle pointing to the mdio. This is OK for linux, but introduces trouble with the already running vxWorks on this target. So this commit here re-inerts the phy_id property beside the phy-handle property to be compatible with both. Signed-off-by: NHannes Schmelzer <hannes.schmelzer@br-automation.com>
-
- 11 12月, 2019 8 次提交
-
-
https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi由 Tom Rini 提交于
- fix DRAM bank detection for unified binary - fix 32bit RPi4 config
-
https://gitlab.denx.de/u-boot/custodians/u-boot-i2c由 Tom Rini 提交于
i2c bugfixes for 2020.01 - i2c: i2c_cdns: fix write timeout on fifo boundary fixes timout issue when writting number of bytes is multiple of the FIFO depth.
-
https://gitlab.denx.de/u-boot/custodians/u-boot-atmel由 Tom Rini 提交于
- First set of u-boot-atmel fixes for 2020.01 cycle: This set includes a small fix for gpio bank names, one for removing unused headers (also touches some other boards), and a fix for the QSPI env read on one of the boards.
-
由 Matthias Brugger 提交于
The rpi_4_32b_defconfig states that only one DRAM bank is present. This leads to a wrong configuration of the available DRAM. Fix this by setting the DRAM bank config accordingly. Fixes: 193279d7 ("RPI: Add defconfigs for rpi4 (32/64)") Signed-off-by: NMatthias Brugger <mbrugger@suse.com>
-
由 Matthias Brugger 提交于
Up to now we only update the DRAM banks when we are define CONFIG_BCM2711. But our one binary approach uses a config that supports BCM2837 and BCM2711. As a result we only see one gibibyte of RAM on Raspberry Pi 4, even if it has more RAM. Fix this by calling dram_init_banksize. Fixes: 56940906 ("ARM: defconfig: add unified config for RPi3 and RPi4") Signed-off-by: NMatthias Brugger <mbrugger@suse.com>
-
由 Matthias Brugger 提交于
To update the dram bank information from device-tree we use fdtdec_decode_ram_size() which expectes the the size-cells and address-cells to be defined in the memory node. For normal system RAM these values are defined in the root node. When the values differ from the default values defined in the spec, we can end up with wrong RAM bank information. Switch to the "standard" way to update the RAM bank information to avoid this. Fixes: 9de5b89e ("rpi4: enable dram bank initialization") Signed-off-by: NMatthias Brugger <mbrugger@suse.com>
-
由 Michael Auchter 提交于
This fixes an issue that would cause I2C writes to timeout when the number of bytes is a multiple of the FIFO depth (i.e. 16 bytes). Within the transfer loop, after writing the data register with a new byte to transfer, if the transfer size equals the FIFO depth, the loop pauses until the INTERRUPT_COMP bit asserts to indicate data has been sent. This same check is performed after the loop as well to ensure data has been transferred prior to returning. In the case where the amount of data to be written is a multiple of the FIFO depth, the transfer loop would wait for the INTERRUPT_COMP bit to assert after writing the final byte, and then wait for this bit to assert once more. However, since the transfer has finished at this point, no new data has been written to the data register, and hence INTERRUPT_COMP will never assert. Fix this by only waiting for INTERRUPT_COMP in the transfer loop if there's still data to be written. Signed-off-by: NMichael Auchter <michael.auchter@ni.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
-
https://gitlab.denx.de/u-boot/custodians/u-boot-video由 Tom Rini 提交于
- fix crash and board reset when drawing RLE8 bitmaps bigger than the framebuffer resolution - reduce dead code in video and console uclass routines (tested on mx53cx9020, sama5d2_xplained, stm32mp157c-ev1, stm32f746-disco, stm32f769-disco and wandboard)
-
- 10 12月, 2019 5 次提交
-
-
由 Swapna Gurumani 提交于
In the initial SPI flash setup, the default bus mode being used was 3, which is incorrect, causing a CRC error when the ENV was being read from QSPI. Setting the default bus mode to 0 which is the correct mode. Signed-off-by: NSwapna Gurumani <swapna.gurumani@microchip.com>
-
https://gitlab.denx.de/u-boot/custodians/u-boot-riscv由 Tom Rini 提交于
- Increase stack size to avoid a stack overflow during distro boot. - Add hifive-unleashed-a00.dts for SIFIVE FU540. - Add OF_SEPARATE support for SIFIVE FU540. - Add SPL support for Andes AX25 AE350. - Improve U-Boot SPL / OpenSBI smp boot flow for RISC-V.
-
由 Lukas Auer 提交于
At the start, OpenSBI relocates itself to its link address. If the link address ranges of U-Boot SPL and OpenSBI overlap, the relocation can lead to code corruption if a hart is still running U-Boot SPL during relocation. To avoid this problem, the main hart is specified as the preferred boot hart to perform the relocation. This fixes the code corruption problems based on the assumption that since the main hart schedules the secondary harts to enter OpenSBI, it will be the last to enter OpenSBI. However it was reported that this assumption is not always correct. To make sure the assumption always holds true, wait for all secondary harts to acknowledge the call-function request before entering OpenSBI on the main hart. Reported-by: NRick Chen <rick@andestech.com> Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: NRick Chen <rick@andestech.com> Tested-by: NRick Chen <rick@andestech.com> Reviewed-by: NAnup Patel <anup.patel@wdc.com>
-
由 Lukas Auer 提交于
Add a wait option to smp_call_function() to wait for the secondary harts to acknowledge the call-function request. The request is considered to be acknowledged once each secondary hart has cleared the corresponding IPI. As part of the call-function request, the secondary harts invalidate the instruction cache after clearing the IPI. This adds a delay between acknowledgment (clear IPI) and fulfillment (call function) of the request. We want to use the acknowledgment to be able to judge when the request has been completed. Remove the delay by clearing the IPI after cache invalidation and just before calling the function from the request. Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: NRick Chen <rick@andestech.com> Tested-by: NRick Chen <rick@andestech.com> Reviewed-by: NAnup Patel <anup.patel@wdc.com>
-
由 Lukas Auer 提交于
Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: NRick Chen <rick@andestech.com>
-