BD ram address may vary in various SOC, so removing the hardcoding and
passing the same information through platform data
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>

Add a README for the family of boards the am335x_evm covers, and include
instructions on preparing and using falcon mode, for various media.
Signed-off-by: NTom Rini <trini@ti.com>
Reviewed-by: NPeter Korsgaard <jacmet@sunsite.dk>
Reviewed-by: NLukasz Majewski <l.majewski@samsung.com>

We use CONFIG_CMD_SPL_WRITE_SIZE when reading/writing the args portion
of falcon mode to NAND.  Previously it was half the size of the
eraseblock which is too small, increase to eraseblock size.
Signed-off-by: NTom Rini <trini@ti.com>

The previous location used for the "args" portion of falcon mode was too
small to allow for a device tree to be saved there, so move the location
slightly and increase the size.  In addition, our previous kernel
location was part of the area we set aside for U-Boot itself, so move it
up a bit higher.
Signed-off-by: NTom Rini <trini@ti.com>
Reviewed-by: NPeter Korsgaard <jacmet@sunsite.dk>

Now that we have falcon mode enabled, the partiton numbers for NAND have
changed, and we need to list entries for updating these parts of the
system.  While adding falcon mode entires for eMMC (raw), we round up
the limit on U-Boot for ease of math later.
Signed-off-by: NTom Rini <trini@ti.com>
Reviewed-by: NPeter Korsgaard <jacmet@sunsite.dk>

Reviewed-by: NPeter Korsgaard <jacmet@sunsite.dk>
Signed-off-by: NTom Rini <trini@ti.com>

The OMAP36xx/OMAP37xx family uses L3 frequency of 200MHz instead of 165MHz
used by OMAP34xx/OMAP35xx.

Also fix checkpatch warning about alignment.
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

Currently, we assume that if we can read from MMC correctly, we have
found a valid image.  This is not the case as an empty area will read
just fine.  Add a check for a valid IH_MAGIC.
Signed-off-by: NTom Rini <trini@ti.com>
Reviewed-by: NPeter Korsgaard <jacmet@sunsite.dk>

The current code uses clrbits_be32 which is incorrect since we are on
a little endian machine here. This patch fixes this issue and also removes
some unnecessary code: Reading the current GPIO bank state is not required
if we are using the SET and CLEAR GPIO registers for setting/clearing
bits.
Signed-off-by: NChristian Riesch <christian.riesch@omicron.at>
Cc: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
Cc: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>

Currently in OMAP3 SPL, the GPMC for NAND is configured for 16bit
access. This patch adds support for 8bit NAND devices as well.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>

Signed-off-by: NTom Rini <trini@ti.com>

Conflict over SPDX changes means that one change was effectively dropped
as it was fixing typos in a removed hunk of text.

Conflicts:
	arch/mips/cpu/mips64/start.S
Signed-off-by: NTom Rini <trini@ti.com>

Acked-by: NHeiko Schocher <hs@denx.de>
Signed-off-by: NTom Rini <trini@ti.com>

Because the SOCFPGA platform will include support for Cyclone V and
Arria V FPGA parts, renaming socfpga_cyclone5 folder to socfpga to
be more generic.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Reviewed-by: NPavel Machek <pavel@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Wolfgang Denk <wd@denx.de>
CC: Pavel Machek <pavel@denx.de>
Cc: Tom Rini <trini@ti.com>

v2:
- Add Reviewed-by: Pavel Machek
- Cc: Tom Rini

Some version of Andes core support FPU coprocessor,
if this is the case, and toolchain support FPU instruction set,
we should enable it at low level initialization time.
Signed-off-by: NKuan-Yu Kuo <ken.kuoky@gmail.com>
Cc: Macpaul Lin <macpaul@gmail.com>

Signed-off-by: NTom Rini <trini@ti.com>

Signed-off-by: NKuan-Yu Kuo <ken.kuoky@gmail.com>
Cc: Macpaul Lin <macpaul@gmail.com>

Restrict autoboot interruption to "s" or "d" keys. This will prevent some
unwanted stopping and also allow disabling the reset on command timeout.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

Compile misc_init_r only if CONFIG_MISC_INIT_R is enabled.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

Accessing powered down peripherals will hang the bus, so check power
domain status before initializing SATA and fixup the FDT to disable
unused peripherals.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

Enable resetting on command timeout. The timeout is set with environment
setting bootretry.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

The timer_init function is called before relocation and writes to bss data
were corrupting relocation data. Fix this by removing the call to
reset_timer_masked. The initial timer count should be 0 or near 0 anyway,
so initializing the variables are not needed.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

The 150MHz clock rate gives u-boot time functions problems and there's no
benefit to a fast clock, so lower the rate.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

get_tbclk should return the timer's frequency, not CONFIG_SYS_HZ.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

Various changes to highbank config:

Enable EFI partitions
Enable ext4 and FAT filesystems
Enable bootz command and raw initrd
Increase cmd and print buffer size to 1K
Change serial baudrate to 115200
Enable hush shell
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

There is no reason to wait for the entire frame to start DMA on receive,
so enable rx cut-thru for better performance.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

interrupt_init also sets up the abort stack, but is not setup before
relocation. So any aborts during relocation will hang and not print out
any useful information. Fix this by moving the interrupt_init to after
the stack setup in board_init_f.
Signed-off-by: NRob Herring <rob.herring@calxeda.com>

Synchronize the code with mips64/cache.S, in order to
allow further unifications.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

Synchronize the code with mips64/cache.S, in order to
allow further unifications.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

Synchronize the code with mips64/cache.S, in order to
allow further unifications.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

Make it similar to the code in mips{32,64}/start.S, in order to
allow further unifications.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

Make it similar to the code in mips64/start.S, in order to
allow further unifications.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

Synchronize the code with mips64/start.S, in order to
allow further unifications.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

The t4 register already holds the cache
line size, and the value of the register
is not changed in mips_init_icache.

Get the cache line size value from t4 for
mips_init_dcache as well and remove the
superfluous assignment of t5 register.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>