USB TLL clocks do not support 'explicit_en', only 'hw_auto'
control (R. Sricharan). cm_l3init_hsusbtll_clkctrl has to be
moved to the clk_modules_hw_auto_essential[] array in order
to make the clock work.

This fix is needed (but not sufficient) for USB EHCI operation
in U-Boot.
Signed-off-by: NLubomir Popov <lpopov@mm-sol.com>

The IGEP COM AQUILA and CYGNUS are industrial processors modules with
following highlights:

  o AM3352/AM3354 Texas Instruments processor
  o Cortex-A8 ARM CPU
  o 3.3 volts Inputs / Outputs use industrial
  o 256 MB DDR3 SDRAM / 128 Megabytes FLASH
  o MicroSD card reader on-board
  o Ethernet controller on-board
  o JTAG debug connector available
  o Designed for industrial range purposes
Signed-off-by: NEnric Balletbo i Serra <eballetbo@iseebcn.com>

These boards uses Samsung K4B2G1646E-BIH9 a 2Gb E-die DDR3 SDRAM.
Signed-off-by: NEnric Balletbo i Serra <eballetbo@iseebcn.com>

EMIF supports a global warm reset mode, during which the
EMIF keeps the SDRAM content. But if leveling is enabled
at the time of warm reset for DDR3, the following steps
needs to be done after warm reset:
1) Keep EMIF in self refresh mode.
2) Reset PHY to bring back the PHY to a known state.
3) Start Levelling procedure.
Doing the same.
And also enabling DLL lock and code output after warm reset.

Tested on OMAP5432 ES2.0
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

We are able to tell the difference between xM Rev Ax/Bx and xM Rev Cx,
and have been for some time.  The comment above the function however did
not list this, so update.
Signed-off-by: NTom Rini <trini@ti.com>

I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms.
In order to be able to select one of these buses however, I2C_BUS_MAX
has to be set to 5; do this here.

Please note that for working bus selection, a fix to the i2c driver
is required as well (subject of a separate patch).
Signed-off-by: NLubomir Popov <lpopov@mm-sol.com>

I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms.
The I2C4 and I2C5 base addresses were however not defined; do this
here.
Signed-off-by: NLubomir Popov <lpopov@mm-sol.com>

I2C4 and I2C5 are utilized on all known OMAP5 hardware platforms.
The i2c5 clock was however not enabled; do this here.
Signed-off-by: NLubomir Popov <lpopov@mm-sol.com>

Add an header guard to common header file to prevent multiple
includes messing things up.
Signed-off-by: NNishanth Menon <nm@ti.com>

commit 21144298 (power: twl6035: add palmas PMIC support)
introduced twl6035_i2c_[read|write]_u8
Then, commit dd23e59d (omap5: pbias ldo9 turn on)
introduced palmas_[read|write]_u8 for precisely the same access
function. TWL6035 belongs to the palmas family, so instead of having
an twl6035 API, we could use an generic palmas API instead.

To stay consistent with the function naming of twl4030,6030 accessors,
we use palmas_i2c_[read|write]_u8

Cc: Balaji T K <balajitk@ti.com>
Cc: Sricharan R <r.sricharan@ti.com>
Reported-by: NRuchika Kharwar <ruchika@ti.com>
Signed-off-by: NNishanth Menon <nm@ti.com>

Since TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs,
rename twl6035_mmc1_poweron_ldo by a more generic palmas_mmc1_poweron_ldo
function.
Signed-off-by: NNishanth Menon <nm@ti.com>

Since TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs,
rename twl6035_init_settings with an more generic palmas_init_settings
Signed-off-by: NNishanth Menon <nm@ti.com>

TPS659038/TWL6035/TWL6037 all belong to palmas family of TI PMICs
Rename twl6035 to palmas to allow reuse across multiple current and
future platforms

As part of this change, change the CONFIG_TWL6035_POWER to
CONFIG_PALMAS_POWER and update usage of header file accordingly.
Signed-off-by: NNishanth Menon <nm@ti.com>

Add an header guard to common header file to prevent multiple includes
messing things up.
Signed-off-by: NNishanth Menon <nm@ti.com>

twl6030_i2c_[read|write]_u8 can be used else where to access
multi-function device such as twl6030, so move the register access
functions to the common twl6030.h header file.
Signed-off-by: NNishanth Menon <nm@ti.com>

u-boot standard i2c register access prototype is
i2c_read(addr, reg, 1, &buf, 1)
i2c_reg_write(u8 addr, u8 reg, u8 val)

twl6030_i2c_read_u8(u8 addr, u8 *val, u8 reg)
twl6030_i2c_write_u8(u8 addr, u8 val, u8 reg)
does not provide consistency, so switch the prototype to be
consistent with rest of u-boot i2c operations:
twl6030_i2c_read_u8(u8 addr, u8 reg, u8 *val)
twl6030_i2c_write_u8(u8 addr, u8 reg, u8 val)
Signed-off-by: NNishanth Menon <nm@ti.com>

u-boot standard i2c read prototype is
i2c_read(addr, reg, 1, &buf, 1)

twl4030_i2c_read_u8(u8 addr, u8 *val, u8 reg)
does not provide consistency, so switch the prototype to be
consistent with rest of u-boot i2c operations:
twl4030_i2c_read_u8(u8 addr, u8 reg, u8 *val)
Signed-off-by: NNishanth Menon <nm@ti.com>

u-boot standard i2c register write prototype is
i2c_reg_write(u8 addr, u8 reg, u8 val)

twl4030_i2c_write_u8(u8 addr, u8 val, u8 reg)
does not provide consistency, so switch the prototype to be
consistent with rest of u-boot i2c operations:
twl4030_i2c_write_u8(u8 addr, u8 reg, u8 val)
Signed-off-by: NNishanth Menon <nm@ti.com>

Adds CPSW support to the TI814X EVM configured with
an ET1011C PHY in GMII mode.
Signed-off-by: NMatt Porter <mporter@ti.com>
Reviewed-by: NTom Rini <trini@ti.com>

Adds an ET1011C PHY driver which is derived from the
Linux kernel PHY driver (drivers/net/phy/et1011c.c)
from the v3.9-rc2 tag. Note that an errata workaround
config option is implemented to allow for TX_CLK to be
enabled even when gigabit mode is negotiated. This
workaround is used on the PG1.0 TI814X EVM.
Signed-off-by: NMatt Porter <mporter@ti.com>
Reviewed-by: NTom Rini <trini@ti.com>

TI814x's version 1 CPSW has a different slave_regs layout.
Add support for the differing registers.
Signed-off-by: NMatt Porter <mporter@ti.com>
Reviewed-by: NTom Rini <trini@ti.com>

Enables required PLLs and clocks for CPSW on TI814x.
Signed-off-by: NMatt Porter <mporter@ti.com>
Reviewed-by: NTom Rini <trini@ti.com>

Support Xilinx Zynq i2c controller.
Signed-off-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NHeiko Schocher <hs@denx.de>
Reviewed-by: NTom Rini <trini@ti.com>

Add support for SD, MMC and eMMC card on Xilinx Zynq.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NTom Rini <trini@ti.com>

Autodetect phy if phyaddress is setup to -1.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NTom Rini <trini@ti.com>

Avoid overwriting GEMx_RCLK_CTRL and GEMx_CLK_CTRL
if the Ethernet interface is connect on EMIO

Do not enable emio for this standard board configuration for now.
Signed-off-by: NDavid Andrey <david.andrey@netmodule.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NTom Rini <trini@ti.com>

Pass the PHY address to the driver init to
allow parallel use of both interfaces
Signed-off-by: NDavid Andrey <david.andrey@netmodule.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NTom Rini <trini@ti.com>

Add all fixed addresses to hardware.h and change petalinux
configuration to support this.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NTom Rini <trini@ti.com>

The whole driver used 100Mbps because of zc702 rev B.
Fix problem with not setup proper clock for gem1.
This is generic approach for clk setup.
Signed-off-by: NMichal Simek <monstr@monstr.eu>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NTom Rini <trini@ti.com>

BDs can be correctly setup just once and init function
performs only phy autodetection and enabling RX/TX.
RX/TX are disabled in halt function.

This patch solves the problem with repeatable tftp transfers.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NTom Rini <trini@ti.com>

Remove one return from the code.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NTom Rini <trini@ti.com>

Removing this bit causes that frame is sent only once.
(With wrap big one packet has been sent several times
which dramatically decrease throughput)

TRM: (Table 16-3: Tx Buffer Descriptor Entry)
Signed-off-by: NMichal Simek <monstr@monstr.eu>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NTom Rini <trini@ti.com>

This phy is used on zedboard (xilinx zynq platform).
Signed-off-by: NMichal Simek <monstr@monstr.eu>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NTom Rini <trini@ti.com>

Move baseaddr to hardware.h to be shared between
configurations.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NTom Rini <trini@ti.com>

XPSS prefix was used in past and it is obsolete for quite
some time. Let's use correct SoC name which is Zynq.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NTom Rini <trini@ti.com>

Rework the __udelay function of U-Boot Zynq Arch to handle
delay < 1000 usec
Signed-off-by: NDavid Andrey <david.andrey@netmodule.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NTom Rini <trini@ti.com>

Signed-off-by: NTom Rini <trini@ti.com>

When crc32 is handled by the hash library, it requires the data to be in
big-endian format, since it reads it byte-wise. Thus at present the 'crc32'
command reports incorrect data. For example, previously we might see:

Peach # crc32 40000000 100
CRC32 for 40000000 ... 400000ff ==> 0d968558

but instead with the hash library we see:

Peach # crc32 40000000 100
CRC32 for 40000000 ... 400000ff ==> 5885960d

Correct this.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NVadim Bendebury <vbendeb@google.com>

The git config parameter log.decorate is quite useful when working with git.
Patman, however can not handle the decorated output when parsing the commit.
To prevent this use the '--no-decorate' switch for git-log.
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Quick manual fixup to merge the USB boot related defines and TPM related
defines.

Conflicts:
	include/configs/exynos5250-dt.h
Signed-off-by: NTom Rini <trini@ti.com>