Convert T1040QDS and T1040RDB to use generic board code.
Signed-off-by: NVijay Rai <vijay.rai@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

When device is configured to load RCW from NAND flash IFC_A[16:31] are driven
low after RCW loading. Hence Devices connected on IFC_CS[1:7] and using
IFC_A[16:31] lines are not accessible.

Workaround is already in-place.
Put the errata number to adhere errata handling framework.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Since commit 0defddc8 (config: Add a default CONFIG_SYS_PROMPT),
each board header does not need to define CONFIG_SYS_PROMPT
as long as it uses the default prompt "=> ".
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

Enable blob commands for platforms having SEC 4.0 or greater
for secure boot scenarios
Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Enable CAAM in platforms supporting the hardware block.
Hash command enabled along with hardware accelerated support for
SHA-1 and SHA-256 for platforms which have CAAM block.
Signed-off-by: NRuchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

T1042RDB is a Freescale reference board that hosts the T1042 SoC
(and variants). The board is similar to T1040RDB, T1042 is a reduced
personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).

T1042RDB is configured with serdes protocol 0x86 which can support
following interfaces
- 2 RGMII's on DTSEC4, DTSEC5
- 1 SGMII on DTSEC3
DTSEC1, DTSEC2 are not connected on board.

This Patch
- add T1042RDB support
- updates README file for T1042RDB details and update commands for switching
  to alternate banks from vBank0 to vBank4 and vice versa

This patch also does minor clean ups for fdt defines for T1042RDB and
T1042RDB_PI board
Signed-off-by: NVijay Rai <vijay.rai@freescale.com>
Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

This patch adds support of rcw for T1042RDB, it makes following changes :
- Adds t1042_rcw.cfg file for serdes protocol 0x86 for T1042RDB
- Renames t1042_pi_rcw.cfg file from t1042_rcw.cfg and also updates
  comments for valid serdes protocol which is 0x06
- Also updates CONFIG_SYS_FSL_PBL_RCW for T1042RDB
Signed-off-by: NVijay Rai <vijay.rai@freescale.com>
Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Enable the Extend address to support SPI flash more than 16MB.
Signed-off-by: NHou Zhiqiang <B48286@freescale.com>
Reviewed-by: NJagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>

Add deep sleep support in SPI/SD boot. The destination address
second stage uboot image is loaded to is changed because
currently this address will be used by kernel which means
we can't reserve it for resume.

Entry point to kernel is still placed in second stage uboot.
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

T1042 has internal display interface unit (DIU) for driving video.
T1042RDB supports video mode via
-LCD using TI enconder
-HDMI type interface via HDMI encoder

Chrontel, CH7301C encoder which is I2C programmable is used
as HDMI connector on T1042RDB.
This patch add support to
-enable Video interface for T1042RDB
-route qixis multiplexing to enable DIU-HDMI interface on board
-program DIU pixel clock gerenartor for T1042
-program HDMI encoder via I2C on board

This patch refer to the upstream diu patch
(337b0c52) for T1040qds.
Signed-off-by: NJason Jin <Jason.Jin@freescale.com>
Signed-off-by: NWang Dongsheng <dongsheng.wang@freescale.com>
[York Sun: resolve conflict and move changes to T104xRDB.h]
Reviewed-by: NYork Sun <yorksun@freescale.com>

Now CONFIG_SPL and CONFIG_TPL are defined in Kconfig.

Remove the redundant definition in config headers.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

We are about to switch to Kconfig in the next commit.
But there are something to get done beforehand.

In Kconfig, include/generated/autoconf.h defines boolean
CONFIG macros as 1.

CONFIG_SPL and CONFIG_TPL, if defined, must be set to 1.
Otherwise, when switching to Kconfig, the build log
would be sprinkled with warning messages like this:
  warning: "CONFIG_SPL" redefined [enabled by default]
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

- Fix base address of I2C2 as 0x118100 instead of 0x119000.
- Add definitions for I2C3 & I2C4.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

On some platforms, CSn FTIM2.TCH is set to zero which is invalid,
an invalid hold time makes DUT timing variances, whether it works
or not on luck.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

This is a workaround for 32 bit hardware limitation of TDM.
T1040 has 36 bit physical addressing, TDM DMAC register
are 32 bit wide but need to store address of CCSR space
which lies beyond 32 bit address range. This workaround
creats a LAW to enable access of TDM DMA to CCSR by
mapping CCSR to overlap with DDR.
A hole of 16M is created in memory using device tree. This
workaround law is set only if "tdm" is defined in hwconfig.
Also disable POST tests and add LIODN for TDM
Signed-off-by: NSandeep Singh <Sandeep@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

AFAICT, c=ffe does nothing and was a typo from the original commit
d1712369 "powerpc/p4080: Add support
for the P4080DS board" and just kept on getting duplicated
in subsequently added board config files.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
Acked-by: NEdward Swarthout <ed.swarthout@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

U-boot binary size has been increased from 512KB to 768KB.

So update CONFIG_SYS_MONITOR_LEN to reflect the same.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Add support of 2 stage NAND, SD, SPI boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(160KB). This further
initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
Finally SPL transer control to u-boot.

Initialise/create followings required for SPL framework
      - Add spl.c which defines board_init_f, board_init_r
      - update tlb and ddr accordingly
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

T1042RDB_PI board does not have QE connector.

So disable CONFIG_QE and CONFIG_U_QE for T1042RDB_PI
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Add deep sleep support on T104xRDB platforms.
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

T1040RDB and T1042RDB_PI has CPLD. Here CPLD controls board mux/features.

This support of CPLD includes
 - files and register defintion
 - Commands to swtich alternate bank and default bank
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

We use dynamical mtdparts partition instead of directly puting
mtd partitions nodes in device tree.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

T1040RDB, T1042RDB header files are very similar so merged into new header file T104xRDB.
T104xRDB header file can support both T1040RDB and T1042RDB_PI header.

Patch makes following changes
-Update Boards.cfg file for T1040RDB and T1042RDB_PI
-Add new T104xRDB header file
-Delete T1040RDB, T1042RDB_PI header file
Signed-off-by: NVijay Rai <vijay.rai@freescale.com>
Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

add CONFIG_QE, CONFIG_U_QE and CONFIG_SYS_QE_FW_ADDR into
"include/configs/T1040RDB.h"
Signed-off-by: NZhao Qiang <B45475@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

CONFIG_SYS_QE_FMAN_FW_ADDR is used to both Fman and QE for microcode address.
Now using CONFIG_SYS_FMAN_FW_ADDR for Fman microcode address,
and CONFIG_SYS_QE_FW_ADDR for QE microcode address.
Signed-off-by: NZhao Qiang <B45475@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Update following DDR related settings for T1040RDB, T1042RDB_PI
-Correct number of chip selects to two as t1040 supports
 two Chip selects.
-Update board_specific_parameters udimm structure with settings
 derived via calibration.
-Update ddr_raw_timing sructure corresponding to DIMM.
-Set ODT to off. Typically on FSL board, ODT is set to 75 ohm,
 but on T104xRDB, on setting this , DDR instability is observed.
 Board-level debugging is in progress.

Verified the updated settings to be working fine with dual-ranked
Micron, MT18KSF51272AZ-1G6 DIMM at data rate 1600MT/s.
Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>

This commit removes platform CONFIG_SYS_HZ definition for the
remainders of part1 (commit cdb23792) and part2 (commit f232950f).
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Rob Herring <rob.herring@calxeda.com>

This covers only non-L2 switch ethernet interfaces i.e.
RGMII and SGMII interface for both T1040RDB and T1042RDB_PI

T1040RDB is configured as serdes protocol 0x66 which can
support following interfaces
    2 RGMIIS on DTSEC4, DTSEC5
    1 SGMII on DTSEC3

T1042RDB_PI is configured as serdes protocol 0x06 which can
support following interfaces
    2 RGMIIS on DTSEC4, DTSEC5
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
[York Sun: Minor change in commit message]
Signed-off-by: NYork Sun <yorksun@freescale.com>

Add usb2 node entry in "hwconfig string"

Remove controller interleaving from hwconfig string as T1040
has only one DDR conroller

SPI related macros which were earlier under #ifdef CONFIG_SPIFLASH
are move outside so that they are defined for all cases as these
macros are also used by other u-boot code

Add CONFIG_SYS_CSPR2_EXT to make CPLD accessible
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
[York Sun: Minor change to commit message]
Signed-off-by: NYork Sun <yorksun@freescale.com>

Define CONFIG_MPC85xx in arch/powerpc/cpu/mpc85xx/config.mk
because all target boards with mpc85xx cpu define it.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>

u-boot binary size for Freescale mpc85xx platforms is 512KB.
This has been reached to upper limit for some of the platforms causig
linker error.

So, Increase the u-boot binary size to 768KB.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>

The last users of CONFIG_KGDB_SER_INDEX were removed more than 3 years
ago in commits 550650dd and bf16500f, either kgdb subsystem should
care about this parameter or it should be gone completely.
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>

Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.
Signed-off-by: NYork Sun <yorksun@freescale.com>

T1040RDB is Freescale Reference Design Board supporting
the T1040 QorIQ Power Architecture™ processor.

 T1040RDB board Overview
 -----------------------
 - Four e5500 cores, each with a private 256 KB L2 cache
 - 256 KB shared L3 CoreNet platform cache (CPC)
 - Interconnect CoreNet platform
 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
   support
 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
 for the following functions:
    -  Packet parsing, classification, and distribution
    -  Queue management for scheduling, packet sequencing, and congestion
       management
    -  Cryptography Acceleration
    - RegEx Pattern Matching Acceleration
    - IEEE Std 1588 support
    - Hardware buffer management for buffer allocation and deallocation
 - Ethernet interfaces
    - Integrated 8-port Gigabit Ethernet switch
    - Four 1 Gbps Ethernet controllers
 - SERDES Connections, 8 lanes supporting:
    - PCI
    - SGMII
    - QSGMII
    - SATA 2.0
 - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
   Interleaving
 -IFC/Local Bus
    - NAND flash: 1GB 8-bit NAND flash
    - NOR: 128MB 16-bit NOR Flash
 - Ethernet
    - Two on-board RGMII 10/100/1G ethernet ports.
    - PHY #0 remains powered up during deep-sleep
 - CPLD
 - Clocks
    - System and DDR clock (SYSCLK, “DDRCLK”)
    - SERDES clocks
 - Power Supplies
 - USB
    - Supports two USB 2.0 ports with integrated PHYs
    - Two type A ports with 5V@1.5A per port.
 - SDHC
    - SDHC/SDXC connector
 - SPI
    - On-board 64MB SPI flash
 - I2C
    - Devices connected: EEPROM, thermal monitor, VID controller
 - Other IO
    - Two Serial ports
    - ProfiBus port
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
[York Sun: fixed Makefile]
Acked-by: NYork Sun <yorksun@freescale.com>

Use a default RCW of protocol 0x66.
A PBI configure file which uses CPC as 256KB SRAM. It can be used by
PBL tool on T1040 to build a pbl boot image.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>

T1040QDS is a high-performance computing evaluation, development and
test platform supporting the T1040 QorIQ Power Architecture™ processor.

 T1040QDS board Overview
 -----------------------
 - Four e5500 cores, each with a private 256 KB L2 cache
 - 256 KB shared L3 CoreNet platform cache (CPC)
 - Interconnect CoreNet platform
 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
   support
 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
 for the following functions:
    -  Packet parsing, classification, and distribution
    -  Queue management for scheduling, packet sequencing, and congestion
    	management
    -  Cryptography Acceleration
    - RegEx Pattern Matching Acceleration
    - IEEE Std 1588 support
    - Hardware buffer management for buffer allocation and deallocation
 - Ethernet interfaces
    - Integrated 8-port Gigabit Ethernet switch
    - Four 1 Gbps Ethernet controllers
 - SERDES Connections, 8 lanes supporting:
      — PCI Express: supporting Gen 1 and Gen 2;
      — SGMII
      — QSGMII
      — SATA 2.0
      — Aurora debug with dedicated connectors
 - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
   Interleaving
 -IFC/Local Bus
     - NAND flash: 8-bit, async, up to 2GB.
     - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
     - GASIC: Simple (minimal) target within Qixis FPGA
     - PromJET rapid memory download support
 - Ethernet
     - Two on-board RGMII 10/100/1G ethernet ports.
     - PHY #0 remains powered up during deep-sleep
 - QIXIS System Logic FPGA
 - Clocks
     - System and DDR clock (SYSCLK, “DDRCLK”)
     - SERDES clocks
 - Power Supplies
 - Video
     - DIU supports video at up to 1280x1024x32bpp
 - USB
     - Supports two USB 2.0 ports with integrated PHYs
     — Two type A ports with 5V@1.5A per port.
     — Second port can be converted to OTG mini-AB
 - SDHC
     - SDHC port connects directly to an adapter card slot, featuring:
     - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
     — Supporting eMMC memory devices
 - SPI
    -  On-board support of 3 different devices and sizes
 - Other IO
    - Two Serial ports
    - ProfiBus port
    - Four I2C ports
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: fix conflict in boards.cfg]
Acked-by-by: NYork Sun <yorksun@freescale.com>

Use a default RCW of protocol 0x2A_0x98, and a PBI configure file which
uses CPC1 as 512KB SRAM, then PBL tool can be used on B4860 to build a
pbl boot image.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>

This patch is for board config file not to add CONFIG_SECURE_BOOT
condition for include the asm/fsl_secure_boot.h.
Signed-off-by: NPo Liu <Po.Liu@freescale.com>

1. Add CONFIG_SYS_DPAA_RMAN macro to t4240 and b4860.
2. Decrease RMan liodn offset number.
SET_RMAN_LIODN() is used to set liodn offset of RMan blocks 0-3.
For t4240 and b4860, RMan liodn base is assigned to 922, the original
offset number is too large that the liodn (base+offset 922+678 = 1600)
is greater than 0x500 the maximum liodn number.
Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>

1) Add support in B4860 board files for using IDT driver where
   IDT8T49N222A is a low phase noise Frequency Translator / Synthesizer
   that generate different refclks for SerDes modules, used this driver
   for reconfiguring SerDes1 Refclks(based on SerDes1 protocols)
   for CPRI to work. CPRI works on 122.88MHz and default refclks coming
   on board are not suitable for it
2) Move SerDes1 refclk1 source selection from eth_b4860qds.c file
   to b4860qds board file, as SerDes1 Refclk1 would come from
   PHY MUX in case of certain protocols, that have been checked here.
   This change would make on board SGMIIs to work
3) Add I2C addresses for IDT8T49N222A devices in board/include file
4) Add define for PCA-I2C bus multiplexer, on which IDT devices exist
Signed-off-by: NShaveta Leekha <shaveta@freescale.com>
Acked-by: NYork Sun <yorksun@freescale.com>