- 12 10月, 2019 1 次提交
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由 Tero Kristo 提交于
Add support for CDCE913/925/937/949 family of devices. These are modular PLL-based low cost, high performance, programmable clock synthesizers, multipliers and dividers. They generate up to 9 output clocks from a single input frequency. The initial version of the driver does not support programming of the PLLs, and thus they run in the bypass mode only. The code is loosely based on the linux kernel cdce9xx driver. Signed-off-by: NTero Kristo <t-kristo@ti.com>
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- 08 10月, 2019 1 次提交
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This patch adds clock driver support for Versal platform. The clock driver queries and performs clock operations using PLM firmware by communicating with it using SMC calls. Signed-off-by: NSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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- 31 7月, 2019 2 次提交
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由 Peng Fan 提交于
Import clk composite clk support from Linux Kernel 5.1-rc5 Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Import clk-gate support from Linux Kernel 5.1-rc5 Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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- 19 7月, 2019 3 次提交
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由 Lukasz Majewski 提交于
This patch provides code to implement the CCF clock tree in sandbox. It uses all the introduced primitives; some generic ones are reused, some sandbox specific were developed. In that way (after introducing the real CCF tree in sandbox) the recently added to clk-uclass.c: clk_get_by_id() and clk_get_parent_rate() are tested in their natural work environment. Usage (sandbox_defconfig and sandbox_flattree_defconfig): ./u-boot --fdt arch/sandbox/dts/test.dtb --command "ut dm clk_ccf" Signed-off-by: NLukasz Majewski <lukma@denx.de>
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由 Lukasz Majewski 提交于
This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: NLukasz Majewski <lukma@denx.de>
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由 Anup Patel 提交于
To match SiFive clock driver with latest Linux, we factor-out PLL library as separate module under drivers/clk/analogbits. Signed-off-by: NAnup Patel <anup.patel@wdc.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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- 23 4月, 2019 1 次提交
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由 Jerome Brunet 提交于
In order to support the Amlogic G12A clock controller, re-architect the clock files into a meson directory. No functionnal changes. MAINTAINERS entry is also updated. Signed-off-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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- 27 2月, 2019 2 次提交
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由 Anup Patel 提交于
This patch adds fixed-factor clock driver which derives clock rate by dividing (div) and multiplying (mult) fixed factors to a parent clock. Signed-off-by: NAtish Patra <atish.patra@wdc.com> Signed-off-by: NAnup Patel <anup.patel@wdc.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Anup Patel 提交于
Add driver code for the SiFive FU540 PRCI IP block. This IP block handles reset and clock control for the SiFive FU540 device and implements SoC-level clock tree controls and dividers. Based on code written by Wesley Terpstra <wesley@sifive.com> found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of: https://github.com/riscv/riscv-linux Boot and PLL rate change were tested on a SiFive HiFive Unleashed board. Signed-off-by: NPaul Walmsley <paul.walmsley@sifive.com> Signed-off-by: NAtish Patra <atish.patra@wdc.com> Signed-off-by: NAnup Patel <anup.patel@wdc.com> Reviewed-by: NAlexander Graf <agraf@suse.de>
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- 19 1月, 2019 1 次提交
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由 Jagan Teki 提交于
Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>
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- 29 11月, 2018 1 次提交
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由 Ryder Lee 提交于
This patch adds clock modules for MediaTek SoCs: - Shared part: a common driver which contains the general operations for plls, muxes, dividers and gates so that we can reuse it in future. - Specific SoC part: the group of structures used to hold the hardware configuration for each SoC. We take MT7629 as an example to demonstrate how to implement driver if any other MediaTek chips would like to use it. Signed-off-by: NRyder Lee <ryder.lee@mediatek.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 26 11月, 2018 1 次提交
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由 Neil Armstrong 提交于
This patch adds a minimal clock driver for the Amlogic AXG SoC to handle the basic gates and PLLs. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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- 28 10月, 2018 1 次提交
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由 Patrick Delaunay 提交于
Complete in the drivers directory the work started with commit 83d290c5 ("SPDX: Convert all of our single license tags to Linux Kernel style"). Reviewed-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
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- 22 10月, 2018 1 次提交
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由 Peng Fan 提交于
Add clk driver for i.MX8QXP. This basic version supports clk enable/disable/get_rate/set_rate operations for I2C, ENET, SDHC0 and UART clocks. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Signed-off-by: NAnatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
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- 01 10月, 2018 1 次提交
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由 Liviu Dudau 提交于
The Arm Versatile Express and Juno development boards contain an OSC clock generator that can be accessed through the Versatile Express config bus. The generators are quite often being controlled by some MCU and the config bus offers a uniform way of exposing them. Signed-off-by: NLiviu Dudau <liviu.dudau@foss.arm.com> Reviewed-by: NHeiko Schocher <hs@denx.de>
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- 18 9月, 2018 1 次提交
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由 Mario Six 提交于
Add a clock driver for the MPC83xx architecture. Signed-off-by: NMario Six <mario.six@gdsys.cc>
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- 11 9月, 2018 1 次提交
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由 Andreas Dannenberg 提交于
Some TI Keystone 2 and K3 family of SoCs contain a system controller (like the Power Management Micro Controller (PMMC) on 66AK2G SoCs and the Device Management and Security Controller on AM65x SoCs) that manage the low-level device control (like clocks, resets etc) for the various hardware modules present on the SoC. These device control operations are provided to the host processor OS through a communication protocol called the TI System Control Interface (TI SCI) protocol. This patch adds a clock driver that communicates to the system controller over the TI SCI protocol for performing clock management of various devices present on the SoC. Various clock functionality is achieved by the means of different TI SCI device operations provided by the TI SCI framework. This code is loosely based on the drivers/clk/keystone/sci-clk.c driver of the Linux kernel. Reviewed-by: NTom Rini <trini@konsulko.com> Signed-off-by: NAndreas Dannenberg <dannenberg@ti.com> Signed-off-by: NVignesh R <vigneshr@ti.com> Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
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- 14 8月, 2018 1 次提交
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由 Marek Vasut 提交于
Add clock driver for the Arria10, which allows reading the clock frequency from all the clock described in the DT. The driver also allows enabling and disabling the clock. Reconfiguring frequency is not supported thus far. Since the DT bindings for the SoCFPGA clock are massively misdesigned and the handoff DT adds additional incorrectly described entries to the DT, the driver contains workarounds which attempt to rectify all of those problems. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
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- 10 7月, 2018 1 次提交
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由 Manivannan Sadhasivam 提交于
This commit adds Actions Semi OWL family base clock and S900 SoC specific clock support. For S900 peripheral clock support, only UART clock has been added for now. Signed-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 19 6月, 2018 1 次提交
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由 Beniamino Galvani 提交于
Introduce a basic clock driver for Amlogic Meson SoCs which supports enabling/disabling clock gates and getting their frequency. Signed-off-by: NBeniamino Galvani <b.galvani@gmail.com> Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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- 14 5月, 2018 1 次提交
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由 Marek Behún 提交于
The drivers are based on Linux driver by Gregory Clement. The TBG clocks support only the .get_rate method. - since setting rate is not supported, the driver computes the rates when probing and so subsequent calls to the .get_rate method do not read the corresponding registers again The peripheral clocks support methods .get_rate, .enable and .disable. - the .set_parent method theoretically could be supported on some clocks (the parent would have to be one of the TBG clocks) - the .set_rate method would have to try all the divider values to find the best approximation of a given rate, and it doesn't seem like this should be needed in U-Boot, therefore not implemented Signed-off-by: NMarek Behun <marek.behun@nic.cz> Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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- 09 5月, 2018 1 次提交
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由 Mario Six 提交于
Add a driver for the ICS8N3QV01 Quad-Frequency Programmable VCXO. Signed-off-by: NMario Six <mario.six@gdsys.cc>
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- 20 3月, 2018 1 次提交
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由 Patrick Delaunay 提交于
add RCC clock driver for STMP32MP157 - base on driver model = UCLASS_CLK - support ops to enable, disable and get rate of all SOC clock needed by U-Boot Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
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- 22 1月, 2018 1 次提交
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由 Mario Six 提交于
The Makefile entries in the clk driver directory were not alphabetically sorted. Correct this. Reviewed-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NMario Six <mario.six@gdsys.cc>
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- 11 12月, 2017 1 次提交
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由 Eugeniy Paltsev 提交于
Synopsys HSDK clock controller generates and supplies clocks to various controllers and peripherals within the SoC. Each clock has assigned identifier and client device tree nodes can use this identifier to specify the clock which they consume. All available clocks are defined as preprocessor macros in the dt-bindings/clock/snps,hsdk-cgu.h header and can be used in device tree sources. Signed-off-by: NEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>
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- 30 11月, 2017 1 次提交
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由 Patrice Chotard 提交于
Now that clk_stm32f7.c manages clocks for both STM32F4 and F7 SoCs rename it to a more generic clk_stm32f.c Fix also some checkpatch errors/warnings. Signed-off-by: NPatrice Chotard <patrice.chotard@st.com> Reviewed-by: NVikas Manocha <vikas.manocha@st.com>
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- 22 9月, 2017 1 次提交
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由 Patrice Chotard 提交于
This driver implements basic clock setup, only clock gating is implemented. This driver doesn't implement .of_match as it's binded by MFD RCC driver. Files include/dt-bindings/clock/stm32h7-clks.h and doc/device-tree-bindings/clock/st,stm32h7-rcc.txt will be available soon in a kernel tag, as all the bindings have been acked by Rob Herring [1]. [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.htmlSigned-off-by: NPatrice Chotard <patrice.chotard@st.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 13 8月, 2017 1 次提交
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由 Philipp Tomsich 提交于
Introduce TPL_CLK to allow finer-grained selection of TPL features for feature-rich (i.e. DM-based) TPL stages. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NTom Rini <trini@konsulko.com>
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- 03 8月, 2017 1 次提交
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由 Marek Vasut 提交于
Add clock driver for the RCar Gen3 R8A7795 and R8A7796 SoCs . This driver allows reading out the clock configuration set by previous boot stages and enabling and disabling clock using the MSTP registers. Setting clock is not supported thus far. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>
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- 10 5月, 2017 1 次提交
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由 Álvaro Fernández Rojas 提交于
This is a simplified version of linux/arch/mips/bcm63xx/clk.c Signed-off-by: NÁlvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 18 3月, 2017 1 次提交
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由 Vikas Manocha 提交于
add basic clock driver support for stm32f7 to enable clocks required by the peripherals. Signed-off-by: NVikas Manocha <vikas.manocha@st.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 17 2月, 2017 1 次提交
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由 Stefan Herbrechtsmeier 提交于
Add a clock framework driver for the zynq platform. The driver is based on the platform zynq clock driver but reworked to use static functions instead of run-time generated objects even for unused clocks. Additionally the CONFIG_ZYNQ_PS_CLK_FREQ is replaced by the ps-clk-frequency from the device tree. Signed-off-by: NStefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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- 29 1月, 2017 1 次提交
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由 maxims@google.com 提交于
Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 10 1月, 2017 1 次提交
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Add basic clock driver support for zynqmp which sets the required clock for GEM controller Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 21 9月, 2016 1 次提交
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由 Paul Burton 提交于
Add a simple driver for the clocks provided by the MIPS Boston development board. The system provides information about 2 clocks whose rates are fixed by the bitfile flashed in the boards FPGA, and this driver simply reads the rates of these 2 clocks. Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 16 8月, 2016 2 次提交
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由 Wenyou Yang 提交于
The patch is referred to at91 clock driver of Linux, to make the clock node descriptions in DT aligned with the Linux's. Signed-off-by: NWenyou Yang <wenyou.yang@atmel.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Stephen Warren 提交于
In Tegra186, on-SoC clocks are manipulated using IPC requests to the BPMP (Boot and Power Management Processor). This change implements a driver that does that. A tegra/ sub-directory is created to follow the existing pattern. It is unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186 build of U-Boot will need the feature. Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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- 06 8月, 2016 2 次提交
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由 Heiko Stübner 提交于
With the number of Rockchip clock drivers increasing, don't clutter up the core drivers/clk directory with them and instead move them out of the way into a separate subdirectory. Suggested-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Acked-by: NSimon Glass <sjg@chromium.org> Updated for rk3399: Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Kever Yang 提交于
This patch add driver for: - clock driver including set_rate for cpu, mmc, vop, I2C. - sysreset driver - grf syscon driver Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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