Add support for CDCE913/925/937/949 family of devices. These are modular
PLL-based low cost, high performance, programmable clock synthesizers,
multipliers and dividers. They generate up to 9 output clocks from a
single input frequency. The initial version of the driver does not
support programming of the PLLs, and thus they run in the bypass mode
only. The code is loosely based on the linux kernel cdce9xx driver.
Signed-off-by: NTero Kristo <t-kristo@ti.com>

This patch adds clock driver support for Versal platform. The clock driver
queries and performs clock operations using PLM firmware by communicating
with it using SMC calls.
Signed-off-by: NSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add simple ZynqMP firmware drive to populate child nodes under
zynqmp_firmware DT node.
Signed-off-by: NRajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The Special Function Registers (SFR) are present in sam9x5 and
sam9x60 too, rename sama5_sfr to at91_sfr.h.
Signed-off-by: NTudor Ambarus <tudor.ambarus@microchip.com>

There is no real driver for clk enable/disable now, and we actually
don't need it now, remove it so that not waste CPU cycles and code size.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

There is no real driver for clk enable/disable now, and we actually
don't need it now, remove it so that not waste CPU cycles and code size.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

There is no real driver for clk enable/disable now, and we actually
don't need it now, remove it so that not waste CPU cycles and code size.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

There is no real driver for clk enable/disable now, and we actually
don't need it now, remove it so that not waste CPU cycles and code size.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

Add code to enable the SD clock on the ast2500 SoC.
Reviewed-by: NCédric Le Goater <clg@kaod.org>
Signed-off-by: NEddie James <eajames@linux.ibm.com>

The G12B clock controller is almost identical to the G12A and
so far the differences don't matter.  Adding the G12B compatible
makes USB work on the Odroid-N2.
Signed-off-by: NMark Kettenis <kettenis@openbsd.org>
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

Use existing gd structure to store frequency information
which can be used in drivers or arch without new request.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

Remove many debug trace.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

Several options are presenting themselves on a various boards
where the options are clearly not used.  (ie, SPL/TPL options
when SPL or TPL are not defined)

This patch is not attempting to be a complete list of items, but
more like low hanging fruit.  In some instances, I wasn't sure
of DM was required, so I simply made them SPL or TPL.

This patch attempts to reduce some of the menuconfig noise
by defining dependencies so they don't appear when not used.
Signed-off-by: NAdam Ford <aford173@gmail.com>

Required to successfully probe the ehci generic driver
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

Add i.MX8MM clk driver support.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Import i.MX8M composite clk from Linux Kernel 5.3.0-rc2
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Add pll14xx driver for i.MX8MM usage, modifed
from Linux Kernel 5.3.0-rc1
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Expose CCF entry, then we could avoid expand the SoC support list
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Since we added clk enable_count and prograte clk child enabling
operation to clk parent, so add a new function sandbox_clk_enable_count
to get enable_count for test usage.

And add test code to get the enable_count after we enable/disable
the device clk.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

On i.MX8MM, thinking such as clk path
OSC->PLL->PLL GATE->CCM ROOT->CCGR GATE->Device

Only enabling CCGR GATE is not enough, we also need to enable PLL GATE
to make sure the clk path work. So when enabling CCGR GATE,
we could prograte to enabling PLL GATE to make life easier.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

As what Linux Kernel 5.3.0 provides when enable/disable clk,
there is an enable_count in clk_core_disable/enable. Introduce
enable_count to track the clk enable/disable count when
clk_enable/disable for CCF. And Initialize enable_count to 0 when
register the clk.

And clk tree dump with enable_count will be supported, it will
be easy for us to check the clk status with enable_count
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Add support for clk_is_match() which is required to
know if two clock pointers point to the same exact
physical clock.

Also add a unit test for the new API.
Reviewed-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Import R8A77980 V3H clock tables from Linux 5.2.7 , commit 5697a9d3d55f.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

This adds high speed interface subsystem - hifsys (i.e. PCIe and USB)
for MT7623 SoC and enables its reset controller.

The control block is shared with ethsys and accordingly rename the
related defines.
Tested-by: NFrank Wunderlich <frank-w@public-files.de>
Signed-off-by: NRyder Lee <ryder.lee@mediatek.com>

First thing we check in meson_clk_set_rate_by_id() is current_rate == rate.
There is not need to check it again.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>

Add composite clk to sandbox driver
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Introduce io_gate_val for sandbox clk gate test usage
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Import clk composite clk support from Linux Kernel 5.1-rc5
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

When the device not binded with a node, we need ignore
the parents and rate settings.

Cc: Simon Glass <sjg@chromium.org>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Add set rate for imx clk-gate2
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Import some clk helpers from Linux Kernel for i.MX8MM usage
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Export the structure for others to use.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Import clk-gate support from Linux Kernel 5.1-rc5
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Add set parent support for clk mux
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Preparing to support composite clk.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

When support Clock Common Framework, U-Boot use dev for
clk tree information, there is no clk->parent. When
support composite clk, it contains mux/gate/divider,
but the mux/gate/divider is not binded with device.
So we could not use dev_get_uclass_priv to get the correct
clk_mux/gate/divider. So add clk_dev_binded to let
choose the correct method.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Init CPU frquency in clock driver instead of in SPL board file,
this will help for use common board file later.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

Right now when using clk_of_xlate_default(), clk->data
remains un-initialized because clk_get_bulk() does not
initialize memory on allocation of clock structure.

This can cause problems when data is used to match if
two clocks pointers are exactly the same underlying
clocks, for example.

Fix it by initializing clk->data to 0.
Suggested-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Add RTCAPB and RTC clock support.
Signed-off-by: NBenjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>