Move DDR3, DDR4 and realted options to Kconfig and clean up existing
uses.
Signed-off-by: NYork Sun <york.sun@nxp.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Move these options to Kconfig and clean up existing uses.
Signed-off-by: NYork Sun <york.sun@nxp.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Move this option to Kconfig and clean up existing uses.
NUM_DDR_CONTROLLERS is also used by PowerPC SoCs.
Signed-off-by: NYork Sun <york.sun@nxp.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Move this option to Kconfig and clean up existing uses.
This option is also used by PowerPC SoCs.
Signed-off-by: NYork Sun <york.sun@nxp.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Move MAX_CPUS option to Kconfig and clean up existing uses for ARM. This
option is used by Freescale Layerscape SoCs.
Signed-off-by: NYork Sun <york.sun@nxp.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Move these options to Kconfig and create a sub-menu to avoid name
conflict with other architectures.
Signed-off-by: NYork Sun <york.sun@nxp.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Some config options should not have prompt. They are selected by choosing
target.
Signed-off-by: NYork Sun <york.sun@nxp.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

SYSCLK is used as a reference clock for USB. When the USB controller
is used, SYSCLK must meet the additional requirement of 100 MHz.
Signed-off-by: NSriram Dash <sriram.dash@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Add the USB node for LS1043 in dts.
Signed-off-by: NSriram Dash <sriram.dash@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Enables driver model flag CONFIG_DM_USB for LS1043A
platform defconfigs.
Signed-off-by: NSriram Dash <sriram.dash@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Pin mux logic has 2 options in priority order, one is through RCW_SRC
and then through RCW_Fields. In case of QSPI booting, RCW_SRC logic
takes the priority for SPI pads and do not allow RCW_BASE and SPI_EXT
to control the SPI muxing. But actually those are DSPI controller's
pads instead of QSPI controller's, so this workaround allows RCW
fields SPI_BASE and SPI_EXT to control relevant pads muxing.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: NYork Sun <york.sun@nxp.com>

Following commits 217f92bb and 15446988, these two config
CPU_V7_HAS_NONSEC and CPU_V7_HAS_VIRT are moved to Kconfig,
for correctly select ARMV7_PSCI.
Signed-off-by: NHongbo Zhang <hongbo.zhang@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: NYork Sun <york.sun@nxp.com>

The core position is not continuous for some SoCs. For example,
valid cores may present at position 0, 1, 4, 5, 8, 9, etc. Some
registers (including boot release register) only count existing
cores. Current implementation of cpu_mask() complies with the
continuous numbering. However, command "cpu status" queries the
spin table with actual core position. Add functions to calculate
core position from core number, to correctly calculate offsets.

Tested on LS2080ARDB and LS1043ARDB.
Signed-off-by: NYork Sun <york.sun@nxp.com>

The exact SoC revsion number can be recognized from U-Boot log.
Signed-off-by: NWenbin Song <wenbin.song@nxp.com>
Signed-off-by: NMingkai Hu <mingkai.hu@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

SFP v3.4 supports 8 keys in SRK table which leads to corresponding
changes in OSPR key revocation field. So modify OSPR_KEY_REVOC_XXX
macros accordingly.
Signed-off-by: NSumit Garg <sumit.garg@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Delete CONFIG_SKIP_LOWLEVEL_INIT define in ls1021atwr.h and
ls1021aqds.h can let it run cpu_init_cp15 to enable i-cache. First
stage of u-boot can run faster after that. There is a description
about skip lowlevel init in board/freescale/ls1021atwr/README.
Signed-off-by: NXiaoliang Yang <xiaoliang.yang@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Update the API's for transition of Security Monitor states. Instead
of providing both initial and final states for transition, just
provide final state for transition as Security Monitor driver will
take care of it internally.
Signed-off-by: NSumit Garg <sumit.garg@nxp.com>
[York Sun: Reformatted commit message slightly]
Reviewed-by: NYork Sun <york.sun@nxp.com>

By default the SATA IP on the ls1043a/ls1046a SoCs does not
generating coherent/snoopable transactions.  This patch enable
it in the SCFG_SNPCNFGCR register along with sata axicc register.
In addition, the dma-coherent property must be set on the SATA
controller nodes.
Signed-off-by: NTang Yuantian <yuantian.tang@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: NYork Sun <york.sun@nxp.com>

The default values for Port Phy2Cfg register and
Port Phy3Cfg register are better, no need to overwrite them.
Signed-off-by: NTang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Signed-off-by: NTom Rini <trini@konsulko.com>

Authentication of images in Falcon Mode is not supported. Do not enable
SPL_OS_BOOT when TI_SECURE_DEVICE is enabled. This prevents attempting
to directly load kernel images which will fail, for security reasons,
on HS devices, the board is locked if a non-authenticatable image load
is attempted, so we disable attempting Falcon Mode.
Signed-off-by: NAndrew F. Davis <afd@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NLokesh Vutla <lokeshvutla@ti.com>

This config option seems to be unused and is probably vestigial.
Remove it.
Signed-off-by: NAndrew F. Davis <afd@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NLokesh Vutla <lokeshvutla@ti.com>

Like OMAP54xx and AM43xx family SoCs, AM33xx based SoCs have high
security enabled models. Allow AM33xx devices to be built with
HS Device Type Support.
Signed-off-by: NAndrew F. Davis <afd@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NLokesh Vutla <lokeshvutla@ti.com>

When CONFIG_FIT_IMAGE_POST_PROCESS or CONFIG_SPL_FIT_IMAGE_POST_PROCESS
is enabled board_fit_image_post_process will be called, add this
function to am33xx boards when CONFIG_TI_SECURE_DEVICE is set to
verify the loaded image.
Signed-off-by: NAndrew F. Davis <afd@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NLokesh Vutla <lokeshvutla@ti.com>

The option SPL_SPI_SUPPORT is used to enable support in SPL for loading
images from SPI flash, it should not be used to determine the build type
of the SPL image itself. The ability to read images from SPI flash does
not imply the SPL will be booted from SPI flash.

Unconditionally build SPI flash compatible SPL images.
Signed-off-by: NAndrew F. Davis <afd@ti.com>
Acked-by: NLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Add a section describing the additional boot types used on AM33xx
secure devices.
Signed-off-by: NAndrew F. Davis <afd@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NLokesh Vutla <lokeshvutla@ti.com>

Depending on the boot media, different images are needed
for secure devices. The build generates u-boot*_HS_* files
as appropriate for the different boot modes.

For AM33xx devices additional image types are needed for
various SPL boot modes as the ROM checks for the name of
the boot mode in the file it loads.
Signed-off-by: NAndrew F. Davis <afd@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NLokesh Vutla <lokeshvutla@ti.com>

The config option AM33XX is used in several boards and should be
defined as a stand-alone option for this SOC. We break this out
from target boards that use this SoC and common headers then enable
AM33XX on in all the boards that used these targets to eliminate any
functional change with this patch.

This is similar to what has already been done in
9de852642cae ("arm: Kconfig: Add support for AM43xx SoC specific Kconfig")
and is done for the same reasons.
Signed-off-by: NAndrew F. Davis <afd@ti.com>
Acked-by: NLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Adds a secure dram reservation fixup for secure
devices, when a region in the emif has been set aside
for secure world use. The size is defined by the
CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE config option.
Signed-off-by: NDaniel Allred <d-allred@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

If the ending portion of the DRAM is reserved for secure
world use, then u-boot cannot use this memory for its relocation
purposes. To prevent issues, we mark this memory as PRAM and this
prevents it from being used by u-boot at all.
Signed-off-by: NDaniel Allred <d-allred@ti.com>

After EMIF DRAM is configured, but before it is used,
calls are made on secure devices to reserve any configured
memory region needed by the secure world and then to lock the
EMIF firewall configuration. If any other firewall
configuration needs to be applied, it must happen before the
lock call.
Signed-off-by: NDaniel Allred <d-allred@ti.com>

Create a few public APIs which rely on secure world ROM/HAL
APIs for their implementation. These are intended to be used
to reserve a portion of the EMIF memory and configure hardware
firewalls around that region to prevent public code from
manipulating or interfering with that memory.
Signed-off-by: NDaniel Allred <d-allred@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Adds start address and size config options for setting aside
a portion of the EMIF memory space for usage by security software
(like a secure OS/TEE). There are two sizes, a total size and a
protected size. The region is divided into protected (secure) and
unprotected (public) regions, that are contiguous and start at the
start address given. If the start address is zero, the intention
is that the region will be automatically placed at the end of the
available external DRAM space.
Signed-off-by: NDaniel Allred <d-allred@ti.com>

rockchip platform have a protocol to pass the the kernel reboot mode to bootloader
by some special registers when system reboot. In bootloader we should read it and take action.

We can only setup boot_mode in board_late_init becasue "setenv" need env setuped.
So add CONFIG_BOARD_LATE_INIT to common header and use a entry "rk_board_late_init"
to replace "board_late_init" in board file.
Signed-off-by: NJacob Chen <jacob2.chen@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

To keep it same with 3288
Signed-off-by: NJacob Chen <jacob2.chen@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Signed-off-by: NJacob Chen <jacob2.chen@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

To keep it same with 3288.
Signed-off-by: NJacob Chen <jacob2.chen@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

The latest rk3288-miniarm board doesn't have eMMC device, so remove it.
Signed-off-by: NZiyuan Xu <xzy.xu@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Enable the pwm regulator for evb-rk3399.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>