The file fsl_secure_boot.h must be included in config file for
Secure Boot. This is not required to be protected by any macro.
CONFIG_FSL_CAAM must be defined and CONFIG_CMD_HASH should be
turned on.

The above was missing in some config files and all files have been
made uniform in this respect.
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: NRuchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This patch also expose the complete DDR region(s) to Linux.
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Move CONFIG_SYS_NS16550 to Kconfig, and run moveconfig.py.
Signed-off-by: NThomas Chou <thomas@wytron.com.tw>

After the secondary cores enter U-Boot, use CONFIG_ARMV8_MULTIENTRY to
make secondary cores excute in spin loop.
Signed-off-by: NHou Zhiqiang <B48286@freescale.com>
Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

This patch adds esdhc support for ls1043ardb.
Signed-off-by: NYangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Signed-off-by: NHou Zhiqiang <B48286@freescale.com>
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
Signed-off-by: NHou Zhiqiang <B48286@freescale.com>
Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

LS1043ARDB Specification:
-------------------------
Memory subsystem:
 * 2GByte DDR4 SDRAM (32bit bus)
 * 128 Mbyte NOR flash single-chip memory
 * 512 Mbyte NAND flash
 * 16 Mbyte high-speed SPI flash
 * SD connector to interface with the SD memory card

Ethernet:
 * XFI 10G port
 * QSGMII with 4x 1G ports
 * Two RGMII ports

PCIe:
 * PCIe2 (Lanes C) to mini-PCIe slot
 * PCIe3 (Lanes D) to PCIe slot

USB 3.0: two super speed USB 3.0 type A ports

UART: supports two UARTs up to 115200 bps for console
Signed-off-by: NHou Zhiqiang <B48286@freescale.com>
Signed-off-by: NLi Yang <leoli@freescale.com>
Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>