- 28 1月, 2016 23 次提交
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由 Gong Qianyu 提交于
It might be missed when converting spi_flash_probe() in cmd_sf.c. This patch refers to commit fbb09918 ("dm: Convert spi_flash_probe() and 'sf probe' to use driver model"). Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Gong Qianyu 提交于
In current driver, we always copy 4 bytes to the dest memory. Actually the dest memory may be shorter than 4 bytes. Add an argument to indicate the dest memory length. Avoid writing memory outside of the bounds. Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Gong Qianyu 提交于
In current driver everytime we memcpy 4 bytes to the dest memory regardless of the remaining length. This patch adds checking the remaining length before memcpy. If the length is shorter than 4 bytes, memcpy the actual length of data to the dest memory. Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Gong Qianyu 提交于
This patch fixes the following compile warning: drivers/spi/fsl_qspi.c: In function 'fsl_qspi_probe': drivers/spi/fsl_qspi.c:937:15: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] priv->regs = (struct fsl_qspi_regs *)plat->reg_base; ^ Just make the cast explicit. Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Yangbo Lu 提交于
According to SD spec, CMD12, CMD52 for writing I/O abort in CCCR need to be set an Abort command type when they are sent. So, we remove all chip-specific #ifdefs and make it available for all platforms. Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Wenbin Song 提交于
Add lpuart support using the driver model. Signed-off-by: NWenbin Song <wenbin.song@nxp.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Wenbin Song 提交于
Move new /chosen node out of the board device tree. Signed-off-by: NWenbin Song <wenbin.song@nxp.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Shaohui Xie 提交于
Set Board Configuration Register to select the lpuart pins of various muxes. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Yangbo Lu 提交于
The MMC spec says "It is strongly recommended for hosts to implement more than 500ms timeout value even if the card indicates the 250ms maximum busy length." Even the previous value of 300ms is known to be insufficient for some cards. So, increase the timeout to 500ms. Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Prabhakar Kushwaha 提交于
Management Complex firmware 9.0 has fixed the issue of dprc_destroy_container i.e. the used portal is not return to the free pool. Which was resulting in error ethernet driver want to use this portal via either DPL or dynamically in Linux. Hard-coding of portal id is removed. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Prabhakar Kushwaha 提交于
Add debug information prints to provide DPMAC statistics - Number of bytes received - Number of received and discard frames - Number of bytes transferred - Number of frames transferred etc. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Prabhakar Kushwaha 提交于
Management Complex FW 9.0 set the hardware depletion to be 20 buffers in order to support multiple pools in DPNI. This requires driver to fill the pool with at least 21 to be able to receive frames. So, Increase number of buffers for a pool. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Prabhakar Kushwaha 提交于
Management Complex FW 9.0 puts a new requirement to provide Tx confirmation and error queue configuration by calling dpni_set_tx_conf API. Configure report of only error frames for a tx frame. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Prabhakar Kushwaha 提交于
Management Complex FW 9.0 puts a new requirement to prepare extended parameters which should be provided as input in dpni_create. extended parameters includes traffic class and IP reassembly configurations. So prepare extended parameters with default "0" as input for dpni_create. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Prabhakar Kushwaha 提交于
MC firmware version 9.0.0 contains - Support of new APIs - Update in existing APIs - Change in Major and minor version of DPAA2 objects This patch contains modifications in FLIB files to support new MC firmware version. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Prabhakar Kushwaha 提交于
Check and compare version of management complex's object with the version supported by Freescale ldpaa2 ethernet driver. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Aneesh Bansal 提交于
In case of error while executing esbc_validate command, SNVS transition and issue of reset is required only for secure-boot. If boot mode is non-secure, this is not required. Similarly, esbc_halt command which puts the core in Spin Loop is applicable only for Secure Boot. Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com> Acked-by: NRuchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Aneesh Bansal 提交于
Chain of Trust is enabled for PowerPC platforms for Secure Boot. CONFIG_BOARD_LATE_INIT is defined. In board_late_init(), fsl_setenv_chain_of_trust() is called which will perform the following: - If boot mode is non-secure, return (No Change) - If boot mode is secure, set the following environmet variables: bootdelay = 0 (To disable Boot Prompt) bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com> Acked-by: NRuchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Aneesh Bansal 提交于
Chain of Trust is enabled for ARM platforms (LS1021 and LS1043). In board_late_init(), fsl_setenv_chain_of_trust() is called which will perform the following: - If boot mode is non-secure, return (No Change) - If boot mode is secure, set the following environmet variables: bootdelay = 0 (To disable Boot Prompt) bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com> Acked-by: NRuchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Aneesh Bansal 提交于
A function is created to detrmine if the boot mode is secure or non-secure for differnt SoC's. Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com> Acked-by: NRuchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Aneesh Bansal 提交于
There are two phases in Secure Boot 1. ISBC: In BootROM, validate the BootLoader (U-Boot). 2. ESBC: In U-Boot, continuing the Chain of Trust by validating and booting LINUX. For ESBC phase, there is no difference in SoC's based on ARM or PowerPC cores. But the exit conditions after ISBC phase i.e. entry conditions for U-Boot are different for ARM and PowerPC. PowerPC: If Secure Boot is executed, a separate U-Boot target is required which must be compiled with a diffrent Text Base as compared to Non-Secure Boot. There are some LAW and TLB settings which are required specifically for Secure Boot scenario. ARM: ARM based SoC's have a fixed memory map and exit conditions from BootROM are same irrespective of boot mode (Secure or Non-Secure). Thus the current Secure Boot functionlity has been split into two parts: CONFIG_CHAIN_OF_TRUST This will have the following functionality as part of U-Boot: 1. Enable commands like esbc_validate, esbc_halt 2. Change the environment settings based on bootmode, determined at run time: - If bootmode is non-secure, no change - If bootmode is secure, set the following: - bootdelay = 0 (Don't give boot prompt) - bootcmd = Validate and execute the bootscript. CONFIG_SECURE_BOOT This is defined only for creating a different compile time target for secure boot. Traditionally, both these functionalities were defined under CONFIG_SECURE_BOOT. This patch is aimed at removing the requirement for a separate Secure Boot target for ARM based SoC's. CONFIG_CHAIN_OF_TRUST will be defined and boot mode will be determine at run time. Another Security Requirement for running CHAIN_OF_TRUST is that U-Boot environemnt must not be picked from flash/external memory. This cannot be done based on bootmode at run time in current U-Boot architecture. Once this dependency is resolved, no separate SECURE_BOOT target will be required for ARM based SoC's. Currently, the only code under CONFIG_SECURE_BOOT for ARM SoC's is defining CONFIG_ENV_IS_NOWHERE Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com> Acked-by: NRuchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Aneesh Bansal 提交于
CONFIG_CMD_BLOB must be defined in case of Secure Boot. It was earlier defined in all config files. The definition has been moved to a common file which is included by all configs. Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com> Acked-by: NRuchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Aneesh Bansal 提交于
The file fsl_secure_boot.h must be included in config file for Secure Boot. This is not required to be protected by any macro. CONFIG_FSL_CAAM must be defined and CONFIG_CMD_HASH should be turned on. The above was missing in some config files and all files have been made uniform in this respect. Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com> Acked-by: NRuchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 26 1月, 2016 17 次提交
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Current code compares the return pointer of function qbman_cena_write_start with NULL. Instead the value of the return pointer should be compared. Signed-off-by: NPratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Acked-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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Freescale's management complex (MC) uses System DDR for internal usage. Increase used System DDR size from 256MB to 512 MB. Signed-off-by: NPratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Acked-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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Freescale's LS2040A is a another personality of LS2080A SoC without AIOP support consisting of 4 armv8 cores. Signed-off-by: NPratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Acked-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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LS2080A has support for 8 DPMAC ports out of which only 5 ports can be used at a time. Enabling all 8 DPMAC ports of LS2080A personality. Signed-off-by: NPratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Acked-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Aneesh Bansal 提交于
Some images to be validated are relocated to a dynamic address at run time. So, these addresses cannot be known befor hand while signing the images and creating the header offline. So, support is required to pass the image address to the validate function as an argument. If an address is provided to the function, the address field in Header is not read and is treated as a reserved field. Signed-off-by: NSaksham Jain <saksham@freescale.com> Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com> Acked-by: NRuchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Aneesh Bansal 提交于
The code for image hash calculation, hash calculation from RSA signature and comparison of hashes has been mobed to a separate function. Signed-off-by: NSaksham Jain <saksham@freescale.com> Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com> Acked-by: NRuchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Aneesh Bansal 提交于
Separate functions are created for reading and checking the sanity of Public keys: - read_validate_single_key - read_validate_ie_tbl - read_validate_srk_table Signed-off-by: NSaksham Jain <saksham@freescale.com> Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com> Acked-by: NRuchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Aneesh Bansal 提交于
The prototype and defination of function fsl_secboot_validate has been changed to support calling this function from another function within u-boot. Only two aruments needed: 1) header address - Mandatory 2) SHA256 string - optional Signed-off-by: NSaksham Jain <saksham@freescale.com> Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com> Acked-by: NRuchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Ed Swarthout 提交于
Following commit 61bd2f75, exclude unused DDR controller from calculating RAM size for SPL boot. Signed-off-by: NEd Swarthout <Ed.Swarthout@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Shaohui Xie 提交于
Fixes lsch2 SerDes registers define according to LS1043A RM Rev D. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Tang Yuantian 提交于
Updated the default sata register values to enhance the performance and stability. Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Shengzhou Liu 提交于
Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0 before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE] to the desired value after DDR initialization has completed. When DDR controller is configured to operate in auto-precharge mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Prabhakar Kushwaha 提交于
SYSCLK frequency is dependent on on-board switch settings. It may vary as per requirement. boot-loader is aware of board switch configurations. So Fixup Linux device tree from boot-loader. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> CC: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Gong Qianyu 提交于
Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Gong Qianyu 提交于
Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Gong Qianyu 提交于
1.Use "qixis_reset sd" to boot from SD 2.Use "qixis_reset sd_qspi" to boot from SD with QSPI support 3.Use "qixis_reset qspi" to boot from QSPI flash On some SoCs such as LS1021A and LS1043A, IFC and QSPI could be pin-multiplexed. So the switches are different between SD boot with IFC support and SD boot with QSPI support. The default booting from SD is with IFC support. Once QSPI is enabled(IFC disabled), only use I2C to access QIXIS. Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Shaohui Xie 提交于
This patch also exposes the complete DDR region(s) to Linux. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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