- 19 1月, 2017 20 次提交
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由 Hou Zhiqiang 提交于
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Minghuan Lian 提交于
All Layerscape SoCs have supported new PCIe driver based on DM. The lagecy PCIe driver code is unused and can be removed. Signed-off-by: NMinghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Minghuan Lian 提交于
The patch enables PCIe in ls2080a defconfigs and removes unused PCIe related macro defines. Signed-off-by: NMinghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Minghuan Lian 提交于
The patch enables PCIe and E1000 in ls1046a related defconfigs. Signed-off-by: NMinghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Minghuan Lian 提交于
The patch enables PCIe and E1000 in ls1043a defconfigs and removes unused PCIe related macro defines. Signed-off-by: NMinghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Minghuan Lian 提交于
The patch enables PCIe and E1000 in ls1012a defconfigs and removes unused PCIe related macro defines Signed-off-by: NMinghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Minghuan Lian 提交于
The patch enables PCIe in ls1021a defconfigs and removes unused PCIe related macro defines. Signed-off-by: NMinghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Minghuan Lian 提交于
There are more than five kinds of Layerscape SoCs. unfortunately, PCIe controller of each SoC is a little bit different. In order to avoid too many macro definitions, the patch addes a new implementation of PCIe driver based on DM. PCIe dts node is used to describe the difference. Signed-off-by: NMinghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Hou Zhiqiang 提交于
To make the layerscape pcie driver clear, move the kernel DT fixup code from pcie_layerscape.c to pcie_layerscape_fixup.c. Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Minghuan Lian 提交于
Signed-off-by: NMinghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Minghuan Lian 提交于
Signed-off-by: NMinghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Minghuan Lian 提交于
Signed-off-by: NMinghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Minghuan Lian 提交于
Signed-off-by: NMinghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Minghuan Lian 提交于
Signed-off-by: NMinghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Minghuan Lian 提交于
There may be multiple PCIe controllers in a SoC. It is not correct that always calling pci_bus_to_hose(0) to get the first PCIe controller for the PCIe device connected other controllers. We just remove this calling because hose always point the correct PCIe controller. Signed-off-by: NMinghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Minghuan Lian 提交于
for the legacy PCI driver, the function pci_bus_to_hose() returns the real PCIe controller. To keep consistency, this function is changed to return the PCIe controller pointer of the root bus instead of the current PCIe bus. Signed-off-by: NMinghuan Lian <Minghuan.Lian@nxp.com> Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Hou Zhiqiang 提交于
Enable DT to support Driver Model. Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Minghuan Lian 提交于
For the function alloc_stream_ids() append_mmu_masters() and fdt_fixup_smmu_pcie() there are no related definitions and they are never called. So the patch removes the unnecessary declares. Signed-off-by: NMinghuan Lian <Minghuan.Lian@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 Priyanka Jain 提交于
It is recommended to set forced-order mode in RNI-6, RNI-20 for performance optimization in LS2088A. Both LS2080A, LS2088A families has CONFIG_LS2080A define. As above update is required only for LS2088A, skip this for LS2080A SoC family. Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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由 jerry.huang@nxp.com 提交于
Enable usb feature for ls1046ardb Signed-off-by: NChangming Huang <jerry.huang@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 10 1月, 2017 1 次提交
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由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@konsulko.com>
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- 09 1月, 2017 2 次提交
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由 Ladislav Michl 提交于
Signed-off-by: NLadislav Michl <ladis@linux-mips.org>
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由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@konsulko.com>
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- 08 1月, 2017 3 次提交
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由 Jagan Teki 提交于
Add 'Peng Fan' as MAINTAINERS of configs/mx6ull_14x14_evk_plugin_defconfig which is missing in below commit "imx: mx6ull_14x14_evk: add plugin defconfig" (sha1: b90ebf49) Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: NPeng Fan <peng.fan@nxp.com> Signed-off-by: NJagan Teki <jagan@openedev.com>
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由 Andrew F. Davis 提交于
The SPL load address changes based on boot type in HS devices, ISW_ENTRY_ADDR is used to set this address for AM43xx based SoCs for similar reasons. Add this same logic for AM33xx devices. Also make the default value for ISW_ENTRY_ADDR correct for GP devices based on SoC, HS devices already pick the correct value in their defconfig. Signed-off-by: NAndrew F. Davis <afd@ti.com>
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由 Andrew F. Davis 提交于
When TI_SECURE_DEV_PKG is not defined we warn that the file '*_HS' was not generated but generate an unsigned one anyway, first fix this warning to say that it was generated but not secured. When the user then exports TI_SECURE_DEV_PKG after getting this warning, and tries to re-build, 'make' will detect the build artifacts as unchanged and so assume they do not need to be re-generated. This causes it to fail to sign the files and it will pack unsigned files into the final image, even though TI_SECURE_DEV_PKG is now correctly defined and working. Fix this by using FORCE on the targets causes them to be re-run even if the dependent files have not changed. This then causes another issue. We currently rename the signed dtb files to overwrite the non-signed ones. We do this so the 'mkimage' tool gives the packaged dtb sections the correct name. If we do not rename the files then SPL will not find them during boot. Fix this by renaming the dtb files by appending _HS to the end of the filename, after the ".dtb", this causes them to still be named correctly in the FIT blob. Signed-off-by: NAndrew F. Davis <afd@ti.com>
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- 05 1月, 2017 14 次提交
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由 York Sun 提交于
Use Kconfig option SYS_PPC64 instead. Signed-off-by: NYork Sun <york.sun@nxp.com>
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由 York Sun 提交于
Use Kconfig option to select chassis version. Signed-off-by: NYork Sun <york.sun@nxp.com>
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由 York Sun 提交于
Use Kconfig option E6500 and clean up existing usage. Signed-off-by: NYork Sun <york.sun@nxp.com>
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由 York Sun 提交于
After most config options are moved to Kconfig, the unused ifdef or elif can be removed. Signed-off-by: NYork Sun <york.sun@nxp.com>
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由 York Sun 提交于
Use Kconfig to select DDR version instead of using config header. Signed-off-by: NYork Sun <york.sun@nxp.com>
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由 York Sun 提交于
These two macros are used for the same thing, the total number of DDR controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and merge existing usage. Signed-off-by: NYork Sun <york.sun@nxp.com>
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由 York Sun 提交于
Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing usage in ls102xa and fsl-layerscape. Remove all powerpc macros in config header and board header files. Signed-off-by: NYork Sun <york.sun@nxp.com>
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由 York Sun 提交于
Use Kconfig to select errata workaround. Signed-off-by: NYork Sun <york.sun@nxp.com>
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由 York Sun 提交于
Add option SYS_FSL_ERRATUM_ESDHC111, SYS_FSL_ERRATUM_ESDHC13, SYS_FSL_ERRATUM_ESDHC135, SYS_FSL_ERRATUM_ESDHC_A001 to mmc Kconfig. Move existing macros to related Kconfig. Signed-off-by: NYork Sun <york.sun@nxp.com> [trini: Migrate bk4r1] Signed-off-by: NTom Rini <trini@konsulko.com>
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由 York Sun 提交于
Use Kconfig to select errata workaround. Signed-off-by: NYork Sun <york.sun@nxp.com>
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由 York Sun 提交于
Create driver/ddr/fsl/Kconfig and move existing options. Clean up existing macros. Signed-off-by: NYork Sun <york.sun@nxp.com> [trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s] Signed-off-by: NTom Rini <trini@konsulko.com>
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由 York Sun 提交于
Remove this macro. It was added by e622d9ed but actually wasn't used. Signed-off-by: NYork Sun <york.sun@nxp.com>
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