Buffer coming from upper layers should be cacheline aligned/padded
to perform safe cache operations. For now we don't do bounce
buffering so getting unaligned buffer is an upper layer error.
We can't check if the buffer is properly padded with current
interface so just assume it is (consider changing with in the
future). The following changes are done:

1. Remove useless length alignment check. We get actual transfer
length not the size of the underlying buffer so it's perfectly
valid for it to be unaligned.
2. Move flush_dcache_range() out of while loop or it will
flush too much.
3. Don't try to fix buffer address before calling invalidate:
if it's unaligned it's an error anyway so let cache subsystem
cry about that.
4. Fix end buffer address to be cacheline aligned assuming upper
layer reserved enough space. This is potentially dangerous
operation so upper layers should be careful about that.
Signed-off-by: NIlya Yanok <ilya.yanok@cogentembedded.com>

The USB spec says that 32 bytes is the minimum required alignment.
However on some platforms we have a larger minimum requirement for cache
coherency.  In those cases, use that value rather than the USB spec
minimum.  We add a cpp check to <usb.h> to define USB_DMA_MINALIGN and
make use of it in ehci-hcd.c and musb_core.h.  We cannot use MAX() here
as we are not allowed to have tests inside of align(...).
Signed-off-by: NTom Rini <trini@ti.com>
[marek.vasut]: introduce some crazy macro voodoo
Signed-off-by: NMarek Vasut <marex@denx.de>
[ilya.yanok]: moved external buffer fixes to separate patch,
we use {ALLOC,DEFINE}_ALIGN_BUFFER macros with alignment of USB_DMA_MINALIGN
for qh_list, qh and qtd structures to make sure they are proper aligned
for both controller and cache operations.
Signed-off-by: NIlya Yanok <ilya.yanok@cogentembedded.com>

Move or_asynclistaddr programming to ehci_submit_async()
function to make sure queue head is properly programmed
before every transfer. This solves the problem with changing
qh address.

Also remove unneeded qh_list->qh_link reprogramming at the
end of transfer.
Signed-off-by: NIlya Yanok <ilya.yanok@cogentembedded.com>

This is the out-of-function-scope counterpart of
ALLOC_CACHE_ALIGN_BUFFER.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
[ilya.yanok]: added missing <linux/compiler.h> include and
{DEFINE,ALLOC}_ALIGN_BUFFER macros allowing explicit alignment
specification.
Signed-off-by: NIlya Yanok <ilya.yanok@cogentembedded.com>

This has never been completely sufficient and now happens too late to
paper over the cache coherency problems with the current USB stack.

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: NTom Rini <trini@ti.com>
Signed-off-by: NIlya Yanok <ilya.yanok@cogentembedded.com>

* 'next' of git://git.denx.de/u-boot-video:
  ipu_common: Add ldb_clk for use in parenting the pixel clock
  ipu_common: Do not hardcode the ipu_clk frequency
  ipu_common: Rename MXC_CCM_BASE
  ipu_common: Let clk_ipu_enable/disable only run on MX51 and MX53
  ipu_common: Only apply the erratum to MX51
  video: Rename CONFIG_VIDEO_MX5
  mx6: Allow mx6 to access the IPUv3 registers
  common lcd: minor coding style changes
Signed-off-by: NWolfgang Denk <wd@denx.de>

* 'master' of git://git.denx.de/u-boot-nios:
  nios2: move gd and bd into BSS
Signed-off-by: NWolfgang Denk <wd@denx.de>

As suggested by Graeme Russ, move gd and bd data structrures
to BSS instead of calculating the locations around the stack
and heap.
Signed-off-by: NThomas Chou <thomas@wytron.com.tw>
Acked-by: NMike Frysinger <vapier@gentoo.org>

For FSL low-end processors (VVN2.2), in order to detect the SD card,
we should enable PEREN, HCKEN and IPGEN to enable the clock.
Otherwise, after booting the u-boot, and then inserting the SD card,
the SD card can't be detected.
For SDHC VVN2.3 IP, these bits are reserved, and SDCLKEN is used.
And when accessing to these reserved bit, no any impact happened.
Signed-off-by: NJerry Huang <Chang-Ming.Huang@freescale.com>
CC: Andy Fleming <afleming@gmail.com>
CC: Marek Vasut <marex@denx.de>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Use the function 'mmc_send_status' to check the card status.
only when the card is ready, driver can send the next erase command
to the card, otherwise, the erase will failed:
=> mmc erase 0 1
MMC erase: dev # 0, block # 0, count 1 ... 1 blocks erase: OK
=> mmc erase 0 2
MMC erase: dev # 0, block # 0, count 2 ... mmc erase failed
1 blocks erase: ERROR
=> mmc erase 0 4
MMC erase: dev # 0, block # 0, count 4 ... mmc erase failed
1 blocks erase: ERROR
Signed-off-by: NJerry Huang <Chang-Ming.Huang@freescale.com>
CC: Andy Fleming <afleming@gmail.com>
CC: Marek Vasut <marex@denx.de>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

This code adds call to mmc_init(), for partition related commands (e.g.
fatls, fatinfo etc.).

It is safe to call mmc_init() multiple times since mmc->has_init flag
prevents from multiple initialization.

The FAT related code calls get_dev high level method and then uses
elements from mmc->block_dev, which is uninitialized until the mmc_init
(and thereof mmc_startup) is called.

This problem appears on boards, which don't use mmc as the default
place for envs
Signed-off-by: NLukasz Majewski <l.majewski@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

mmc_set_clock is set to the hard-coding.
But i think good that use the tran_speed value.
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

* 'master' of git://git.denx.de/u-boot-i2c:
  mx28evk: Add I2C support
  mxs-i2c: Fix internal address byte order
  mxc_i2c: remove setting speed at each start
  mx6qsabrelite: add i2c support
  mxc_i2c: specify i2c base address in config file
Signed-off-by: NWolfgang Denk <wd@denx.de>

Add I2C support.

Tested by placing a 24LC16 EEPROM into the U50 slot which comes empty from factory.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Acked-by: NMarek Vasut <marex@denx.de>

Large EEPROMs, e.g. 24lc32, need 2 byte to address the internal memory.
These devices require that the high byte of the internal address has to be
written first.
The mxs_i2c driver currently writes the address' low byte first.

The following patch fixes the byte order of the internal address that should
be written to the I2C device.
Signed-off-by: NTorsten Fleischer <to-fleischer@t-online.de>

CC: Marek Vasut <marex@denx.de>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: NMarek Vasut <marex@denx.de>
Acked-by: NStefano Babic <sbabic@denx.de>

Other then being very weird, this code was also wrong.
For example, say I set speed to 100K. I'll read back the speed
as 85937. But the speed is really 85937.5, so we I reset
the speed to 85937, I'll get 73660.7. After a couple of transactions
my speed is now exactly 68750 so it will remain there.
Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com>
Acked-by: NMarek Vasut <marex@denx.de>
Acked-by: NStefano Babic <sbabic@denx.de>

Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com>
Acked-by: NStefano Babic <sbabic@denx.de>

The following platforms had their config files changed
flea3, imx31_phycore, mx35pdk, mx53ard, mx53evk, mx53smd
and mx53loco.
Signed-off-by: NTroy Kisky <troy.kisky@boundarydevices.com>
Acked-by: NStefano Babic <sbabic@denx.de>

The clean up patch missed an &, so we end up passing an int rather than
a pointer to the sprintf function.

arp.c: In function 'ArpReceive':
arp.c:197: warning: format '%p' expects type 'void *', but argument 3 has type 'int'
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

When support sh7734 of sh-ether, ECSIPR_BRCRXIP and other were removed.
Therefore SH7757 and SH7724 can not build. This revise this probelem.
Signed-off-by: NNobuhiro Iwamatsu <iwamatsu@nigauri.org>
Tested-by: NYoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Add ldb_clk for use in parenting the pixel clock.
Signed-off-by: NEric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Do not hardcode the ipu_clk frequency and let the board file pass this value.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Rename MXC_CCM_BASE to CCM_BASE_ADDR as this is already defined for MX6.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

The registers accessed inside clk_ipu_enable/disable are not present on MX6,
so make sure they only run on MX51 and MX53.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

The following erratum :

"ENGcm08316
IPU: Clarification regarding the bypass mode registers setup for
display and camera interfaces"

only applies to mx51, so restrict its usage for this SoC only.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Rename CONFIG_VIDEO_MX5 as this driver can also be used on mx6.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

Adjust the IPUv3 registers, so that the IPUv3 driver can be extended for mx6 as well.
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>

No functional changes
Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: NIgor Grinberg <grinberg@compulab.co.il>

Signed-off-by: NWolfgang Denk <wd@denx.de>

Signed-off-by: NWolfgang Denk <wd@denx.de>

* 'master' of git://git.denx.de/u-boot-arm:
  tegra: define fdt_load/fdt_high variables
  tegra: enable bootz command
  tegra: usb: Fix device enumeration problem of USB1
  tegra: trimslice: set up serial flash pinmux
  tegra: add pin_mux_spi() board initialization function
  tegra: add GMC/GMD funcmux entry for SFLASH
  tegra: bootcmd: start USB only when needed
  tegra: bootcmd enhancements
  tegra: add enterrcm command
  tegra: enable CONFIG_ENV_VARS_UBOOT_CONFIG
  Add env vars describing U-Boot target board
  tegra: usb: fix wrong error check
  tegra: add ULPI on USB2 funcmux entry
  tegra: fix leftover CONFIG_TEGRA2_MMC & _SPI build switches
  tegra: Add Tamonten Evaluation Carrier support
  tegra: Use SD write-protect GPIO on Tamonten
  tegra: Implement gpio_early_init() on Tamonten
  tegra: Allow boards to perform early GPIO setup
  tegra: plutux: Add device tree support
  tegra: medcom: Add device tree support
  tegra: Rework Tamonten support
  beagle: add eeprom expansion board info for bct brettl4
Signed-off-by: NWolfgang Denk <wd@denx.de>

Fixed the compiler warning message.
Signed-off-by: NRajeshwari Shinde <rajeshwari.s@samsung.com>
Acked-by: NMarek Vasut <marex@denx.de>

* 'master' of git://git.denx.de/u-boot-usb:
  CONFIG: EXYNOS5: USB: Enable USB 2.0 on smdk5250
  EXYNOS5: USB: Fix incorrect USB base addresses
  EXYNOS: Add power Enable/Disable for USB-EHCI
  USB: EXYNOS: Set USB 2.0 HOST Link mode
  EXYNOS5: Add structure for PMU registers
  EXYNOS5: Fix system register structure
  USB: EXYNOS: Incorporate EHCI review comments
Signed-off-by: NWolfgang Denk <wd@denx.de>

These variables act like loadaddr, but for a device tree image. Defining
them in the environment allows boot scripts to be identical on Tegra20 and
Tegra30, which have different memory base addresses, and hence need
different values for these variables.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

bootz is just like bootm, except that it can boot a raw zImage, without
requiring it to be wrapped inside a uImage.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

A known hardware issue of USB1 port where bit 1 (connect status
change) of PORTSC register will be set after issuing Port Reset
(like "usb reset" in u-boot command line).
This will be treated as an error and stops later device enumeration.

Therefore we clear that bit after Port Reset in order to proceed
later device enumeration.
Signed-off-by: NJim Lin <jilin@nvidia.com>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NTom Warren <twarren@nvidia.com>

When Trimslice is booted from serial flash, the boot ROM does this, so
U-Boot doesn't need to. However, booting from the SD slot for recovery
purposes, the boot ROM does not set up the pinmux for serial flash. Add
code to U-Boot to set this up, so that an SD-based recovery U-Boot image
can upgrade the U-Boot in serial flash.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

Boards can override this to set up the pinmux correctly to access serial
flash.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

This is used on TrimSlice.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>