Merge branch 'master' of git://git.denx.de/u-boot-usb

* 'master' of git://git.denx.de/u-boot-usb:
  CONFIG: EXYNOS5: USB: Enable USB 2.0 on smdk5250
  EXYNOS5: USB: Fix incorrect USB base addresses
  EXYNOS: Add power Enable/Disable for USB-EHCI
  USB: EXYNOS: Set USB 2.0 HOST Link mode
  EXYNOS5: Add structure for PMU registers
  EXYNOS5: Fix system register structure
  USB: EXYNOS: Incorporate EHCI review comments
Signed-off-by: NWolfgang Denk <wd@denx.de>

arch/arm/cpu/armv7/exynos/power.c

@@ -52,3 +52,25 @@ void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable)
 	if (cpu_is_exynos4())
 		exynos4_mipi_phy_control(dev_index, enable);
 }
+
+void exynos5_set_usbhost_phy_ctrl(unsigned int enable)
+{
+	struct exynos5_power *power =
+		(struct exynos5_power *)samsung_get_base_power();
+
+	if (enable) {
+		/* Enabling USBHOST_PHY */
+		setbits_le32(&power->usbhost_phy_control,
+				POWER_USB_HOST_PHY_CTRL_EN);
+	} else {
+		/* Disabling USBHOST_PHY */
+		clrbits_le32(&power->usbhost_phy_control,
+				POWER_USB_HOST_PHY_CTRL_EN);
+	}
+}
+
+void set_usbhost_phy_ctrl(unsigned int enable)
+{
+	if (cpu_is_exynos5())
+		exynos5_set_usbhost_phy_ctrl(enable);
+}

arch/arm/cpu/armv7/exynos/system.c

@@ -25,6 +25,28 @@
 #include <asm/io.h>
 #include <asm/arch/system.h>
 
+static void exynos5_set_usbhost_mode(unsigned int mode)
+{
+	struct exynos5_sysreg *sysreg =
+		(struct exynos5_sysreg *)samsung_get_base_sysreg();
+	unsigned int phy_cfg;
+
+	/* Setting USB20PHY_CONFIG register to USB 2.0 HOST link */
+	if (mode == USB20_PHY_CFG_HOST_LINK_EN) {
+		setbits_le32(&sysreg->usb20phy_cfg,
+				USB20_PHY_CFG_HOST_LINK_EN);
+	} else {
+		clrbits_le32(&sysreg->usb20phy_cfg,
+				USB20_PHY_CFG_HOST_LINK_EN);
+	}
+}
+
+void set_usbhost_mode(unsigned int mode)
+{
+	if (cpu_is_exynos5())
+		exynos5_set_usbhost_mode(mode);
+}
+
 static void exynos4_set_system_display(void)
 {
 	struct exynos4_sysreg *sysreg =

arch/arm/include/asm/arch-exynos/cpu.h

@@ -46,6 +46,7 @@
 #define EXYNOS4_USBOTG_BASE		0x12480000
 #define EXYNOS4_MMC_BASE		0x12510000
 #define EXYNOS4_SROMC_BASE		0x12570000
+#define EXYNOS4_USB_HOST_EHCI_BASE	0x12580000
 #define EXYNOS4_USBPHY_BASE		0x125B0000
 #define EXYNOS4_UART_BASE		0x13800000
 #define EXYNOS4_ADC_BASE		0x13910000
@@ -69,10 +70,11 @@
 #define EXYNOS5_DMC_CTRL_BASE		0x10DD0000
 #define EXYNOS5_GPIO_PART1_BASE		0x11400000
 #define EXYNOS5_MIPI_DSIM_BASE		0x11D00000
+#define EXYNOS5_USB_HOST_EHCI_BASE	0x12110000
+#define EXYNOS5_USBPHY_BASE		0x12130000
+#define EXYNOS5_USBOTG_BASE		0x12140000
 #define EXYNOS5_MMC_BASE		0x12200000
 #define EXYNOS5_SROMC_BASE		0x12250000
-#define EXYNOS5_USBOTG_BASE		0x12480000
-#define EXYNOS5_USBPHY_BASE		0x12480000
 #define EXYNOS5_UART_BASE		0x12C00000
 #define EXYNOS5_PWMTIMER_BASE		0x12DD0000
 #define EXYNOS5_GPIO_PART2_BASE		0x13400000
@@ -159,6 +161,7 @@ SAMSUNG_BASE(swreset, SWRESET)
 SAMSUNG_BASE(timer, PWMTIMER_BASE)
 SAMSUNG_BASE(uart, UART_BASE)
 SAMSUNG_BASE(usb_phy, USBPHY_BASE)
+SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE)
 SAMSUNG_BASE(usb_otg, USBOTG_BASE)
 SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
 SAMSUNG_BASE(power, POWER_BASE)

arch/arm/include/asm/arch-exynos/ehci-s5p.h → arch/arm/include/asm/arch-exynos/ehci.h

 /*
- * SAMSUNG S5P USB HOST EHCI Controller
+ * SAMSUNG EXYNOS USB HOST EHCI Controller
  *
  * Copyright (C) 2012 Samsung Electronics Co.Ltd
  *	Vivek Gautam <gautam.vivek@samsung.com>
@@ -20,8 +20,8 @@
  * MA 02110-1301 USA
  */
 
-#ifndef __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__
-#define __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__
+#ifndef __ASM_ARM_ARCH_EHCI_H__
+#define __ASM_ARM_ARCH_EHCI_H__
 
 #define CLK_24MHZ		5
 
@@ -43,7 +43,7 @@
 #define EHCICTRL_ENAINCR16			(1 << 26)
 
 /* Register map for PHY control */
-struct s5p_usb_phy {
+struct exynos_usb_phy {
 	unsigned int usbphyctrl0;
 	unsigned int usbphytune0;
 	unsigned int reserved1[2];
@@ -63,4 +63,4 @@ struct s5p_usb_phy {
 /* Switch on the VBUS power. */
 int board_usb_vbus_init(void);
 
-#endif /* __ASM_ARM_ARCH_EXYNOS5_EHCI_S5P_H__ */
+#endif /* __ASM_ARM_ARCH_EHCI_H__ */

arch/arm/include/asm/arch-exynos/system.h

@@ -42,12 +42,16 @@ struct exynos5_sysreg {
 	unsigned int	reserved;
 	unsigned int	ispblk_cfg;
 	unsigned int	usb20phy_cfg;
+	unsigned char	res2[0x29c];
 	unsigned int	mipi_dphy;
 	unsigned int	dptx_dphy;
 	unsigned int	phyclk_sel;
 };
 #endif
 
+#define USB20_PHY_CFG_HOST_LINK_EN	(1 << 0)
+
+void set_usbhost_mode(unsigned int mode);
 void set_system_display_ctrl(void);
 
 #endif	/* _EXYNOS4_SYSTEM_H */

drivers/usb/host/Makefile

@@ -42,6 +42,7 @@ COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-mpc512x.o
 else
 COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o
 endif
+COBJS-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o
 COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
 COBJS-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o
 COBJS-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o
@@ -51,7 +52,6 @@ COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
 COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o
 COBJS-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
 COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o
-COBJS-$(CONFIG_USB_EHCI_S5P) += ehci-s5p.o
 COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
 COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o
 

drivers/usb/host/ehci-s5p.c → drivers/usb/host/ehci-exynos.c

 /*
- * SAMSUNG S5P USB HOST EHCI Controller
+ * SAMSUNG EXYNOS USB HOST EHCI Controller
  *
  * Copyright (C) 2012 Samsung Electronics Co.Ltd
  *	Vivek Gautam <gautam.vivek@samsung.com>
@@ -23,13 +23,19 @@
 #include <common.h>
 #include <usb.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/ehci-s5p.h>
+#include <asm/arch/ehci.h>
+#include <asm/arch/system.h>
+#include <asm/arch/power.h>
 #include "ehci.h"
 #include "ehci-core.h"
 
 /* Setup the EHCI host controller. */
-static void setup_usb_phy(struct s5p_usb_phy *usb)
+static void setup_usb_phy(struct exynos_usb_phy *usb)
 {
+	set_usbhost_mode(USB20_PHY_CFG_HOST_LINK_EN);
+
+	set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_EN);
+
 	clrbits_le32(&usb->usbphyctrl0,
 			HOST_CTRL0_FSEL_MASK |
 			HOST_CTRL0_COMMONON_N |
@@ -61,7 +67,7 @@ static void setup_usb_phy(struct s5p_usb_phy *usb)
 }
 
 /* Reset the EHCI host controller. */
-static void reset_usb_phy(struct s5p_usb_phy *usb)
+static void reset_usb_phy(struct exynos_usb_phy *usb)
 {
 	/* HOST_PHY reset */
 	setbits_le32(&usb->usbphyctrl0,
@@ -70,6 +76,8 @@ static void reset_usb_phy(struct s5p_usb_phy *usb)
 			HOST_CTRL0_SIDDQ |
 			HOST_CTRL0_FORCESUSPEND |
 			HOST_CTRL0_FORCESLEEP);
+
+	set_usbhost_phy_ctrl(POWER_USB_HOST_PHY_CTRL_DISABLE);
 }
 
 /*
@@ -79,12 +87,12 @@ static void reset_usb_phy(struct s5p_usb_phy *usb)
  */
 int ehci_hcd_init(void)
 {
-	struct s5p_usb_phy *usb;
+	struct exynos_usb_phy *usb;
 
-	usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy();
+	usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
 	setup_usb_phy(usb);
 
-	hccr = (struct ehci_hccr *)(EXYNOS5_USB_HOST_EHCI_BASE);
+	hccr = (struct ehci_hccr *)samsung_get_base_usb_ehci();
 	hcor = (struct ehci_hcor *)((uint32_t) hccr
 				+ HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
 
@@ -101,9 +109,9 @@ int ehci_hcd_init(void)
  */
 int ehci_hcd_stop()
 {
-	struct s5p_usb_phy *usb;
+	struct exynos_usb_phy *usb;
 
-	usb = (struct s5p_usb_phy *)samsung_get_base_usb_phy();
+	usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
 	reset_usb_phy(usb);
 
 	return 0;

include/configs/smdk5250.h

@@ -102,6 +102,12 @@
 #define CONFIG_BOOTDELAY		3
 #define CONFIG_ZERO_BOOTDELAY_CHECK
 
+/* USB */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_EXYNOS
+#define CONFIG_USB_STORAGE
+
 /* MMC SPL */
 #define CONFIG_SPL
 #define COPY_BL2_FNPTR_ADDR	0x02020030