- 06 4月, 2021 5 次提交
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由 Neil Armstrong 提交于
These compatibles are now handled by the dwmac_meson8b glue driver. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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由 Neil Armstrong 提交于
This adds a proper glue driver for the Designware DWMAC ethernet MAC IP found in the Amlogic Meson8, GXBB, GXL, GXM, G12A, G12B & SM1 SoCs. This is aimed to replace the static ethernet link setup found on the board init code for the Amlogic SoC based boards. Tested on a libretech-cc (S905x Internal RMII 10/100 PHY) and Khadas VIM3 (A113d with external 10/100/1000 RGMII PHY) to cover the most extreme setups. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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由 Neil Armstrong 提交于
The Amlogic G12A & compatible SoCs embeds a mux to either communicate with the external PHY or the internal 10/100 PHY. This adds support for this mux as a MDIO MUX device. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Reviewed-by: NRamon Fried <rfried.dev@gmail.com>
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由 Neil Armstrong 提交于
Add support for DM_MDIO to connect to PHY and expose a MDIO device for the internal MDIO bus in order to dynamically connect to MDIO PHYs with DT with eventual MDIO muxes in between. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Reviewed-by: NRamon Fried <rfried.dev@gmail.com>
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由 Neil Armstrong 提交于
Add support for MMIO register MDIO muxes based on the Linux mdio-mux-mmioreg driver. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Reviewed-by: NRamon Fried <rfried.dev@gmail.com>
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- 30 3月, 2021 1 次提交
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由 Robert Hancock 提交于
The code was trying to disable PCS auto-negotiation when a fixed-link node is present and enable it otherwise. However, the PCS registers were being written before the PCSSEL bit was set in the network configuration register, and it appears that in this state, PCS register writes are ignored. The result is that the intended change only took effect on the second network operation that was performed, since at that time PCSSEL is already enabled. Fix the order of register writes so that PCS registers are only written to after the PCS is enabled. Fixes: 26e62cc9 ("net: gem: Disable PCS autonegotiation in case of fixed-link") Signed-off-by: NRobert Hancock <robert.hancock@calian.com> Reviewed-by: NRamon Fried <rfried.dev@gmail.com> Reviewed-by: NAshok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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- 25 2月, 2021 1 次提交
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由 Heinrich Schuchardt 提交于
When copying to a u32 field we should use sizeof(u32) and not sizeof(*u32) in memcpy. On 64bit systems like cortina_presidio-asic-emmc_defconfig using sizeof(*u32) leads to a buffer overrun. Fixes: febe13b4 ("net: cortina_ni: Add eth support for Cortina Access CAxxxx SoCs") Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-By: NRamon Fried <rfried.dev@gmail.com>
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- 23 2月, 2021 3 次提交
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由 Michal Simek 提交于
Clean up error path in connection where priv->rxbuffers and priv->tx_bd are allocated. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 T Karthik Reddy 提交于
Enable rx clock along with tx clock for versal platform. Use compatible data to enable/disable clocks in the driver. Signed-off-by: NT Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Reviewed-by: NRamon Fried <rfried.dev@gmail.com>
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由 Michal Simek 提交于
A lot of Xilinx drivers are checking -ENOSYS which means that clock driver doesn't have enable function. Remove this checking from drivers and create dummy enable function as was done for clk_fixed_rate driver by commit 6bf6d81c ("clk: fixed_rate: add dummy enable() function"). Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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- 22 2月, 2021 2 次提交
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由 Rasmus Villemoes 提交于
Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: NHeiko Schocher <hs@denx.de>
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由 Rasmus Villemoes 提交于
Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: NHeiko Schocher <hs@denx.de>
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- 17 2月, 2021 4 次提交
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由 Alex Marginean 提交于
This driver is used for the Ethernet switch integrated into LS1028A NXP. Felix on LS1028A has 4 front panel ports and two internal ports, I/O to/from the switch is done through an ENETC Ethernet interface. The 4 front panel ports are available as Ethernet interfaces and can be used with the typical network commands like tftp. Signed-off-by: NAlex Marginean <alexandru.marginean@nxp.com> Signed-off-by: NClaudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
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由 Claudiu Manoil 提交于
DSA stands for Distributed Switch Architecture and it covers switches that are connected to the CPU through an Ethernet link and generally use frame tags to pass information about the source/destination ports to/from CPU. Front panel ports are presented as regular ethernet devices in U-Boot and they are expected to support the typical networking commands. DSA switches may be cascaded, DSA class code does not currently support this. Signed-off-by: NAlex Marginean <alexandru.marginean@nxp.com> Signed-off-by: NClaudiu Manoil <claudiu.manoil@nxp.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com>
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由 Vladimir Oltean 提交于
The DSA (Distributed Switch Architecture) implementation has made a design decision when it got introduced to the Linux kernel in 2008. That was to hide away from the user the CPU-facing Ethernet MAC, since it does not make sense to register it as a struct net_device (UCLASS_ETH udevice for U-Boot), because that would never be beneficial for a user: they would not be able to use it for traffic, since conceptually, a packet delivered to the CPU port should loop back into the system. Nonetheless, DSA has had numerous growing pains due to the lack of a struct net_device for the CPU port, but so far it has overcome them. It is unlikely at this stage of maturity that this aspect of it will change. We would like U-Boot to present the same information as Linux, to be at parity in terms of number of interfaces, so that ethNaddr environment variables could directly be associated between U-Boot and Linux. Therefore, we would implicitly like U-Boot to hide the CPU port from the user as well. But the paradox is that DSA still needs a struct phy_device to inform the driver of the parameters of the link that it should configure the CPU port to. The problem is that the phy_device is typically returned via a call to phy_connect, which needs an udevice to attach the PHY to, and to search its ofnode for the 'fixed-link' property. But we don't have an udevice to present for the CPU port. Since 99% of DSA setups are MAC-to-MAC connections between the switch and the host Ethernet controller, the struct phy_device is going to be a fixed PHY. This simplifies things quite a bit. In U-Boot, a fixed PHY does not need an MDIO bus, and does not need an attached dev either. Basically, the phy_connect call doesn't do any connection, it just creates the fixed PHY. The proposal of this patch is to introduce a new fixed_phy_create function which will take a single argument: the ofnode that holds this: port@4 { reg = <4>; phy-mode = "internal"; fixed-link { speed = <2500>; full-duplex; }; }; and probe a fixed PHY driver using the information from this ofnode. DSA will probably be the only user of this function. Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: NClaudiu Manoil <claudiu.manoil@nxp.com>
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由 Vladimir Oltean 提交于
Unlike the Linux fixed PHY driver, the one in U-Boot does not attempt to emulate the clause 22 register set of a gigabit copper PHY driver through the swphy framework. Therefore, the limitation of being unable to support speeds higher than gigabit in fixed-link does not apply to the U-Boot fixed PHY driver. This makes the fixed-link U-Boot implementation more similar to the one from phylink, which can work with any valid link speed. Signed-off-by: NVladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: NClaudiu Manoil <claudiu.manoil@nxp.com>
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- 16 2月, 2021 1 次提交
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由 Simon Glass 提交于
At present this function does not accept a size for the FIT. This means that it must be read from the FIT itself, introducing potential security risk. Update the function to include a size parameter, which can be invalid, in which case fit_check_format() calculates it. For now no callers pass the size, but this can be updated later. Also adjust the return value to an error code so that all the different types of problems can be distinguished by the user. Signed-off-by: NSimon Glass <sjg@chromium.org> Reported-by: NBruce Monroe <bruce.monroe@intel.com> Reported-by: NArie Haenel <arie.haenel@intel.com> Reported-by: NJulien Lenoir <julien.lenoir@intel.com>
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- 15 2月, 2021 2 次提交
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由 Tom Rini 提交于
This board has not been converted to CONFIG_DM by the deadline of v2020.01 and is missing other conversions which depend on this as well. Remove it. As this is the last SH4A board, remove that support as well. Cc: Marek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Tom Rini 提交于
This board has not been converted to CONFIG_DM by the deadline of v2020.01 and is missing other conversions which depend on this as well. Remove it. Patch-cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Patch-cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: NTom Rini <trini@konsulko.com>
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- 12 2月, 2021 1 次提交
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由 Michael Walle 提交于
If probe fails, the mdio bus isn't unregistered. Fix it. Signed-off-by: NMichael Walle <michael@walle.cc> Reviewed-by: NRamon Fried <rfried.dev@gmail.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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- 08 2月, 2021 2 次提交
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由 Ye Li 提交于
Current MDIO wait time is too long, which introduce long delay when PHY negotiation register checking. Reduce it to 10us Signed-off-by: NYe Li <ye.li@nxp.com> Reviewed-by: NFugang Duan <Fugang.duan@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com> Reviewed-by: NPriyanka Jain <priyanka.jain@nxp.com>
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由 Ioana Ciornei 提交于
We have encountered circumstances when a board design does not include pull-up resistors on the external MDIO buses which are not used. This leads to the MDIO data line not being pulled-up, thus the MDIO controller will always see the line as busy. Without a timeout in the MDIO bus driver, the execution is stuck in an infinite loop when any access is initiated on that external bus. Add a timeout in the driver so that we are protected in this circumstance. This is similar to what is being done in the Linux xgmac_mdio driver. Signed-off-by: NIoana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: NMadalin Bucur <madalin.bucur@oss.nxp.com> [Rebased] Signed-off-by: NPriyanka Jain <priyanka.jain@nxp.com>
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- 03 2月, 2021 2 次提交
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由 Bin Meng 提交于
priv->iobase was declared as phys_addr_t which is now a 64-bit address. In a 32-bit build, this causes the following warning seen when building ftmac100.c: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Cast priv->iobase with uintptr_t. Signed-off-by: NBin Meng <bin.meng@windriver.com>
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由 Simon Glass 提交于
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Rini <trini@konsulko.com>
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- 01 2月, 2021 2 次提交
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由 Andre Przywara 提交于
The pinmux choice for the RMII/RGMII pins the EMAC is connected to is not dependent on the EMAC IP, but on the SoC it is integrated in. Deriving the pinmux from the DT compatible string (as we do at the moment) will thus cause problems with certain EMAC IP / SoC combinations. To avoid this exact issue with the H616, let's use our Kconfig MACH symbols to choose the correct pinmux setup. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Tested-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NJernej Skrabec <jernej.skrabec@siol.net>
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由 Andre Przywara 提交于
At the moment we only consider the EPHY register for those SoCs were we actually have an internal PHY to configure. However even other SoCs have this register, an expect the EPHY select bit to be cleared for proper operation with an external PHY. Rework sun8i_emac_set_syscon_ephy() to be called regardless of the EMAC model, and clear the H3_EPHY_SELECT bit if no internal PHY is used. We get away without it so far because SoCs like the A64 clear this bit on reset, but we need to explicitly clear it on the H616, for instance. The Linux driver does so as well. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Tested-by: NJernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: NJernej Skrabec <jernej.skrabec@siol.net>
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- 27 1月, 2021 6 次提交
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由 Marek Vasut 提交于
The phydev structure has a PHY OF node pointer in it, use that OF node first when looking up PHY OF node properties, since that is likely the correct PHY OF node pointer. If the pointer is not valid, which is the case e.g. on legacy DTs, fall back to parsing MAC ethernet-phy subnode. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Ramon Fried <rfried.dev@gmail.com>
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由 Abbie Chang 提交于
Add phy driver support for MACs embedded inside Cortina Access SoCs Signed-off-by: NAbbie Chang <abbie.chang@cortina-access.com> Signed-off-by: NAlex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Joe Hershberger <joe.hershberger@ni.com> CC: Tom Rini <trini@konsulko.com> CC: Aaron Tseng <aaron.tseng@cortina-access.com> Moved out PHY specific code out of Cortina NI Ethernet driver and into a Cortina Access PHY interface driver
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由 Aaron Tseng 提交于
Add Cortina Access Ethernet device driver for CAxxxx SoCs. This driver supports both legacy and DM_ETH network models. Signed-off-by: NAaron Tseng <aaron.tseng@cortina-access.com> Signed-off-by: NAlex Nemirovsky <alex.nemirovsky@cortina-access.com> Signed-off-by: NAbbie Chang <abbie.chang@cortina-access.com> CC: Joe Hershberger <joe.hershberger@ni.com> CC: Abbie Chang <abbie.chang@Cortina-Access.com> CC: Tom Rini <trini@konsulko.com>
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由 Stefan Roese 提交于
Add some missing address translations from virtual address in local DRAM to physical address, which is needed for the DMA transactions to work correctly. This issue was detected while testing the e1000 driver on the MIPS Octeon III platform, which needs address translation. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
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由 Stefan Roese 提交于
Using (dm_)pci_virt_to_mem() is incorrect to translate the virtual address in local DRAM to a physical address. The correct macro here is virt_to_phys() so switch to using this macro. As virt_to_bus() is now not used any more, this patch also removes both definitions (DM and non-DM). This issue was detected while testing the e1000 driver on the MIPS Octeon III platform, which needs address translation. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
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由 Stefan Roese 提交于
bus_to_phys() is defined but not referenced at all. This patch removes it completely. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
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- 26 1月, 2021 1 次提交
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由 Andre Przywara 提交于
So far all GBit users of the sun8i-emac driver were using the "rgmii" PHY mode, even though this turns out to be wrong. It just worked because the PHY driver doesn't do the proper setup (yet). In fact for most boards the "rgmii-id" or "rgmii-txid" PHY modes are the correct ones. To allow the DTs to describe the phy-mode correctly, and to stay compatible with Linux, at least allow those other RGMII modes in the driver. This avoids breakage if mainline DTs will be synced with U-Boot. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Acked-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
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- 25 1月, 2021 1 次提交
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由 Weijie Gao 提交于
This patch adds ethernet driver for MediaTek MT7620 SoC. The MT7620 SoC has a built-in ethernet (Frame Engine) and a built-in 7-port switch and two xMII interfaces (can be MII/RMII/RGMII). The port 0-3 of the switch connects to intergrited FE PHYs. Port 4 can be configured to connect to either the intergrited FE PHY, or the xMII. Port 5 always connects to the xMII. Port 6 is the CPU port. This driver supports MT7530 giga switch connects to port 5. Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NWeijie Gao <weijie.gao@mediatek.com>
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- 22 1月, 2021 5 次提交
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由 Claudiu Beznea 提交于
Take into account all RGMII interface types. Depending on it the RGMII PHY's timings are setup. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
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由 Claudiu Beznea 提交于
Add support for SAMA7G5 EMAC. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
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由 Claudiu Beznea 提交于
Add support for SAMA7G5 GMAC. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
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由 Claudiu Beznea 提交于
clk_set_rate() returns the set rate in case of success and a negative number in case of failure. Consider failure only the negative numbers. Fixes: 3ef64444 ("dm: net: macb: Implement link speed change callback") Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
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由 Claudiu Beznea 提交于
Different implementation of USER IO register needs different mapping for bit fields of this register. Add implementation for this and, since clken is part of USER IO and it needs to be activated based on per SoC capabilities, add caps in macb_config where clken specific information needs to be filled. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
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- 19 1月, 2021 1 次提交
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由 Marek Vasut 提交于
The DWMAC4 IP has the possibility to skip up to 7 AXI bus width size words after the descriptor. Use this to pad the descriptors to cacheline size and remove the need for noncached memory altogether. Moreover, this lets Tegra use the generic cache flush / invalidate operations. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Stephen Warren <swarren@nvidia.com> Tested-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NStephen Warren <swarren@nvidia.com> Tested-by: NPatrice Chotard <patrice.chotard@foss.st.com>
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