- 07 6月, 2017 4 次提交
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由 Andy Yan 提交于
Add clock driver support for Rockchip rv1108 soc Signed-off-by: NAndy Yan <andy.yan@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Kever Yang 提交于
- hclk/pclk_div range should use '<=' instead of '<' - use GPLL for pd_bus clock source - pd_bus HCLK/PCLK clock rate should not bigger than ACLK Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Kever Yang 提交于
Embeded the shift in mask MACRO definition in cru header file and clock driver. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Andy Yan 提交于
Add driver to setup the various PLLs and peripheral clocks on the RK3368. Signed-off-by: NAndy Yan <andy.yan@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 01 6月, 2017 1 次提交
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由 Simon Glass 提交于
These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 11 5月, 2017 9 次提交
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由 Philipp Tomsich 提交于
This allows requests (via the DTS) for PCLK_HDMI_CTRL/PCLK_VIO_GRF, which are clock gates in the HDMI output path for the RK3399. As these are enabled by default (i.e. after reset), we don't implement any logic to actively open/close these clock gates and simply assume that their reset-default has not been changed. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
The (non-secure) efuse node in the DTS requests PCLK_EFUSE1024NS. To allow us to add a efuse-driver (and more importantly, to allow probes of such a driver to succeed), we need need to accept requests for PCLK_EFUSE1024NS and return a non-error result. As PCLK_EFUSE1024NS is enabled by default (i.e. after reset), we don't implement any logic to manage this clock gate and simply assume that the reset-default has not been changed. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: NKlaus Goger <klaus.goger@theobroma-systems.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
The clocking of the designware MMC controller in the upstream (i.e. Linux) RK3399 has changed/does not match what the current DTS in U-Boot uses: the first clock entry now is HCLK_SDMMC instead of SCLK_SDMMC. With the simple clock driver used for the RK3399, this needs a change in the selector understood by the various case statements in the driver to ensure that the driver still loads successfully. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
For the RK3399, i2c_set_rate (and by extension: our spi_set_rate, which had been mindlessly following the template of the i2c_set_rate implementation) miscalculates the rate returned due to a off-by-one error resulting from the following sequence of events: 1. calculates 'src_div := src_freq / target_freq' 2. stores 'src_div - 1' into the register (the actual divider applied in hardware is biased by adding 1) 3. returns the result of the DIV_RATE(src_freq, src_div) macro, which expects the (decremented) divider from the hardware-register and implictly adds 1 (i.e. 'DIV_RATE(freq, div) := freq / (div + 1)') This can be observed with the SPI driver, which sets a rate of 99MHz based on the GPLL frequency of 594MHz: the hardware generates a clock of 99MHz (src_div is 6, the bitfield in the register correctly reads 5), but reports a frequency of 84MHz (594 / 7) on return. To fix, we have two options: * either we bias (i.e. "DIV_RATE(GPLL, src_div - 1)"), which doesn't make for a particularily nice read * we simply call the i2c/spi_get_rate function (introducing additional overhead for the additional register-read), which reads the divider from the register and then passes it through the DIV_RATE macro Given that this code is not time-critical, the more readable solution (i.e. calling the appropriate get_rate function) is implemented in this change. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: NKlaus Goger <klaus.goger@theobroma-systems.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
This change adds support for configuring the module clocks for SPI1 and SPI5 from the 594MHz GPLL. Note that the driver (rk_spi.c) always sets this to 99MHz, but the implemented functionality is more general and will also support different clock configurations. X-AffectedPlatforms: RK3399-Q7 Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: NJakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com> Tested-by: NKlaus Goger <klaus.goger@theobroma-systems.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Xu Ziyuan 提交于
The genunie bus clock is sclk_x for eMMC/SDMMC, add support for it. Signed-off-by: NZiyuan Xu <xzy.xu@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Xu Ziyuan 提交于
The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for it. Signed-off-by: NZiyuan Xu <xzy.xu@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Xu Ziyuan 提交于
The genunie bus clock is sclk_x for eMMC/SDMMC/SDIO, add support for it. Signed-off-by: NZiyuan Xu <xzy.xu@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Xu Ziyuan 提交于
The genunie bus clock is sclk_x for eMMC/SDIO, add support for it. Signed-off-by: NZiyuan Xu <xzy.xu@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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- 05 4月, 2017 4 次提交
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由 Philipp Tomsich 提交于
The clock driver for the RK3399 mistakenly used (24 * 2^20) where it should have used (24 * 10^6) in a few calculations. This commits fixes this. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
The Ethernet driver for the RK3288/3399 GMAC makes sure that the clock is ungated through a call to clk_set_rate(...). Even though nothing needs to be done on the RK3399 (the clock gates are open and the clock is external), we need to implement enough support to at least return success to enable driver probing. X-AffectedPlatforms: RK3399-Q7 Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Philipp Tomsich 提交于
Due to differences in the code paths for SPL and non-SPL, some static constant structures remain unused in each build variant. This raises warnings with recent GCC versions (we currently use GCC-6.3). The warnings addressed in this commit (by matching #if conditions for the variable definition with their uses) are: * for the SPL build: drivers/clk/rockchip/clk_rk3399.c:53:29: warning: 'cpll_init_cfg' defined but not used [-Wunused-const-variable=] static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); ^~~~~~~~~~~~~ drivers/clk/rockchip/clk_rk3399.c:52:29: warning: 'gpll_init_cfg' defined but not used [-Wunused-const-variable=] static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); ^~~~~~~~~~~~~ * for the non-SPL build: drivers/clk/rockchip/clk_rk3399.c:54:29: warning: 'ppll_init_cfg' defined but not used [-Wunused-const-variable=] static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); ^~~~~~~~~~~~~ Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Heiko Stübner 提交于
The armclk starts in slow mode (24MHz) on the rk3188, which makes the whole startup take a lot of time. We therefore want to at least move to the safe 600MHz value we can use with default pmic settings. This is also the freqency the proprietary sdram-init leaves the cpu at. For boards that have pmic control later in u-boot, we also add the option to set the maximum frequency of 1.6GHz, if they so desire. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Acked-by: NSimon Glass <sjg@chromium.org>
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- 17 3月, 2017 4 次提交
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由 Kever Yang 提交于
Add rk3328 clock driver and cru structure definition. Signed-off-by: NWilliam Zhang <william.zhang@rock-chips.com> Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
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由 Heiko Stübner 提交于
Add a driver for setting up and modifying the various PLLs and peripheral clocks on the RK3188. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Reviewed-by: NSimon Glass <sjg@chromium.org> Tested-by: NKever Yang <kever.yang@rock-chips.com>
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由 Heiko Stübner 提交于
The gpll and cpll init values are only used in rk_clk_init in the SPL and therefore produce compile time warnings in regular uboot builds. Fix that with an #ifdef. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Acked-by: NSimon Glass <sjg@chromium.org> Added rockchip tag: Signed-off-by: NSimon Glass <sjg@chromium.org>
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由 Kever Yang 提交于
Add ddr clock setting, add rockchip_get_pmucru API, and enable of-platdata support. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Added rockchip tag and fix pmuclk_init() build warning: Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 26 11月, 2016 1 次提交
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由 Simon Glass 提交于
Add basic support for setting the ARM clock, since this allows us to run at maximum speed in U-Boot. Currently only a single speed is supported (1.8GHz). Signed-off-by: NSimon Glass <sjg@chromium.org>
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- 31 10月, 2016 4 次提交
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由 Simon Glass 提交于
This function is called from outside the driver. It should be placed into common SoC code. Move it. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Simon Glass 提交于
This function is called from outside the driver. It should be placed into common SoC code. Move it. Also rename the driver symbol to be more consistent with the other rockchip clock drivers. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Simon Glass 提交于
This function is called from outside the driver. It should be placed into common SoC code. Move it. Also rename the driver symbol to be more consistent with the other rockchip clock drivers. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Jacob Chen 提交于
clk_rk3399 is driver name, not device name Signed-off-by: NJacob Chen <jacob2.chen@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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- 22 9月, 2016 2 次提交
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由 Kever Yang 提交于
This patch add clk_get_rate for PWM device. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Kever Yang 提交于
pmucru is a module like cru which is a clock controller manage some PLL and module clocks. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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- 06 8月, 2016 3 次提交
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由 Heiko Stübner 提交于
The already available ilog2 function does exactly the same in the common case than the log2 function the current clock-driver reimplement. So, simply move to that one. Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Kever Yang 提交于
MMC core will use 400KHz for card initialize first and then switch to higher frequency like 50MHz, we need to support both 400KHz and about 50MHz for dwmmc controller. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Heiko Stübner 提交于
With the number of Rockchip clock drivers increasing, don't clutter up the core drivers/clk directory with them and instead move them out of the way into a separate subdirectory. Suggested-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NHeiko Stuebner <heiko@sntech.de> Acked-by: NSimon Glass <sjg@chromium.org> Updated for rk3399: Signed-off-by: NSimon Glass <sjg@chromium.org>
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