This patch adds support for i.MX27-LITEKIT development board from
LogicPD. This board uses i.MX27 SoC and has 2MB NOR flash, 64MB NAND
flash, FEC ethernet controller integrated into i.MX27.
Signed-off-by: NIlya Yanok <yanok@emcraft.com>
Acked-by: NWolfgang Denk <wd@denx.de>

Commit 7ebafb7e introduced a mistake in the spi
init function call for those boards. This patch fixes this.
Signed-off-by: NAlbin Tonnerre <albin.tonnerre@free-electrons.com>

Remove duplicate set_cr

set_cr is defined in both asm-arm/proc-armv/system.h and
include/asm-arm/system.h. This patch removes it (and some duplicate
defines) from the former.
Signed-off-by: NSimon Kagstrom <simon.kagstrom@netinsight.net>

Update CHANGELOG
Signed-off-by: NWolfgang Denk <wd@denx.de>

This fixes current build failure.
Signed-off-by: NAndre Schwarz <andre.schwarz@matrix-vision.de>

mvblm7.c: fix warning: implicit declaration of function
'mv_reset_environment'
Signed-off-by: NWolfgang Denk <wd@denx.de>

The "console: unify printing current devices" patch goofed:
CONFIG_SYS_CONSOLE_INFO_QUIET is supposed to *REMOVE* boot
time noise, not add it.  Said patch changed the #ifndefs
to #ifdef; this one restores them to the proper sense.
Signed-off-by: NDavid Brownell <dbrownell@users.sourceforge.net>

The "mac id" command took a 4-character parameter as the identifier string.
However, for any given board, only one kind of identifier is acceptable, so it
makes no sense to ask the user to type it in.  Instead, if the user enters
"mac id", the identifier (and also the version, if it's NXID) will
automatically be set to the correct value.

Improve the message that is displayed when EEPROM is read during boot.  It now
displays "EEPROM:" and then either an error message or the EEPROM identifier
if successful.

If the identifier in EEPROM is valid, then always reject a bad CRC, even if the
CRC field has not been initialized.

Don't force the MAC address count to MAX_NUM_PORTS or less.  Forcing the value
to be changed resulting in an in-memory copy that does not match what's in
hardware, even though the user did not request that change.

Finally, always update the CRC value in the in-memory copy after any field
is changed, so that the CRC is always correct.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Call fsl_pci_init_port() to initialize all the PCIe ports on the board.
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

fsl_pci_init_port can be called from board specific PCI initialization
routines to setup the PCI (or PCIe) controller.  This will reduce code
redundancy in most of the 85xx/86xx FSL board ports that setup PCI.
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The MPIC initialization code for Freescale e500 CPUs was not using I/O
accessors, and it was not issuing a read-back to the MPIC after setting
mixed mode.  This may be the cause of a spurious interrupt on some systems.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

P1011 and P2010 are single core variants of P1010 and P2020 respectively.
The board(RDB) will be same.
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

P1011 - Single core variant of P1020
P2010 - Single core variant of P2020
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

With current values of CONFIG_SYS_MEMTEST_START and CONFIG_SYS_MEMTEST_END
memory test hangs if run without arguments. Set them to sane values, so
that all available 512MB of RAM excluding exception vectors at the bottom
and u-boot code and stack at the top can be tested.
Signed-off-by: NFelix Radensky <felix@embedded-sol.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

To match all other 85xx platforms we are removing BEDBUG support.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Also fix some minor whitespace oddities while we're cleaning up
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

There are really no differences between all the 85xx linker scripts so
we can just move to a single common one.  Board code is still able to
override the common one if need be.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

P1020 is another member of QorIQ series of processors which falls in ULE
category. It is an e500 based dual core SOC.

Being a scaled down version of P2020 it has following differences:
- 533MHz - 800MHz core frequency.
- 256Kbyte L2 cache
- Ethernet controllers with classification capabilities.
Also the SOC is pin compatible with P2020
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The code base adds P1 & P2 RDB platforms support.
The folder and file names can cater to future SOCs of P1/P2 family.
P1 & P2 processors are 85xx platforms, part of Freescale QorIQ series.

Tested following on P2020RDB:
1. eTSECs
2. DDR, NAND, NOR, I2C.
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The number of CPUs are getting detected dynamically by checking the
processor SVR value.  Also removed CONFIG_NUM_CPUS references from all
the platforms with 85xx/86xx processors.

This can help to use the same u-boot image across the platforms.

Also revamped and corrected few Freescale Copyright messages.
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Removed same code pieces from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c
and moved to cpu/mpc8xxx/cpu.c(new file)
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Move files belonging to the STx boards into common vendor directory and
update the Makefile to reflect this.
Signed-off-by: NAlex Dubov <oakad@yahoo.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

For historic reasons we had defined some additional PLATFORM_CPPFLAGS like:

PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1

However these are all captured in the config.h and thus redudant.  Also
moved common 86xx flags into cpu/mpc86xx/config.mk.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

For historic reasons we had defined some additional PLATFORM_CPPFLAGS
like:

PLATFORM_CPPFLAGS += -DCONFIG_E500=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1

However these are all captured in the config.h and thus redudant.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

We move all IO addressed (CCSR, localbus, PCI) above the 4G boundary
to allow for larger memory sizes.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Acked-by: NWolfgang Denk <wd@denx.de>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The old PCI ATMU setup code would just mimic the PCI regions into the
ATMU registers.  For simple memory maps in which all memory, MMIO, etc
space fit into 4G this works ok.  However there are issues with we have
>4G of memory as we know can't access all of memory and we need to
ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with
anything since we can't turn it off.

We first setup outbound windows based on what the board code setup
in the pci regions for MMIO and IO access.  Next we place PCICSRBAR
below the MMIO window.  After which we try to setup the inbound windows
to map as much of memory as possible.

On PCIe based controllers we are able to overmap the ATMU setup since
RX & TX links are separate but report the proper amount of inbound
address space to the region tracking to ensure there is no overlap.

On PCI based controllers we use as many inbound windows as available to
map as much of the memory as possible.

Additionally we changed all the CCSR register access to use proper IO
accessor functions.  Also had to add CONFIG_SYS_CCSRBAR_PHYS to some
86xx platforms that didn't have it defined.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Change the code to use the PCIe capabilities register to determine if we
are a PCIe controller or not.  Additionally cleaned up some white space
and formatting in the file.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Every platform that calls fsl_pci_init calls fsl_pci_setup_inbound_windows
before it calls fsl_pci_init.  There isn't any reason to just call it
from fsl_pci_init and simplify things a bit.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Every platform that calls fsl_pci_init calls pci_setup_indirect before
it calls fsl_pci_init.  There isn't any reason to just call it from
fsl_pci_init and simplify things a bit.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Clean up existing boards (mvBC-P/MPC5200 and mvBL-M7/MPC8343) by
using common code.
Signed-off-by: NAndré Schwarz <andre.schwarz@matrix-vision.de>

apparently the ITX was missed last round.

Also make bootdelay consistent with other boards, so as to give on the
opportunity to fix mistakenly set bootcmd without having checked for an
bootdelay zero setting first.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

This patch adds 4 BIT ECC support in the DaVinci NAND
driver. Tested on both the DM355 and DM365.
Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: NScott Wood <scottwood@freescale.com>