The Platform-Level Interrupt Controller (PLIC)
block holds memory-mapped claim and pending registers
associated with software interrupt. It is required
for handling IPI.
Signed-off-by: NRick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>

Print an error message and hang if smp_call_function() returns an error,
indicating that relocation of the secondary harts has failed.
Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>

RISC-V U-Boot expects the hart ID to be passed to it via register a0 by
the previous boot stage. Machine mode firmware such as BBL and OpenSBI
do this when starting their payload (U-Boot) in supervisor mode. If
U-Boot is running in machine mode, this task must be handled by the boot
ROM. Explicitly populate register a0 with the hart ID from the mhartid
CSR to avoid possible problems on RISC-V processors with a boot ROM that
does not handle this task.
Suggested-by: NRick Chen <rick@andestech.com>
Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-by: NAtish Patra <atish.patra@wdc.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NRick Chen <rick@andestech.com>
Tested-by: NRick Chen <rick@andestech.com>

Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>

On RISC-V, all harts boot independently. To be able to run on a
multi-hart system, U-Boot must be extended with the functionality to
manage all harts in the system. All harts entering U-Boot are registered
in the available_harts mask stored in global data. A hart lottery system
as used in the Linux kernel selects the hart U-Boot runs on. All other
harts are halted. U-Boot can delegate functions to them using
smp_call_function().

Every hart has a valid pointer to the global data structure and a 8KiB
stack by default. The stack size is set with CONFIG_STACK_SIZE_SHIFT.
Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>

The hart ID passed by the previous boot stage is currently stored in
register s0. If we divert the control flow inside a function, which is
required as part of multi-hart support, the function epilog may not be
called, clobbering register s0. Save the hart ID in the unallocatable
register tp instead to protect the hart ID.
Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NRick Chen <rick@andestech.com>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>

Move the initialization of the caches and the debug UART until after
board_init_f_init_reserve. This is in preparation for SMP support, where
code prior to this point will be executed by all harts. This ensures
that initialization will only be performed once on the main hart running
U-Boot.
Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

The supervisor binary interface (SBI) provides the necessary functions
to implement the platform IPI functions riscv_send_ipi() and
riscv_clear_ipi(). Use it to implement them.

This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs
running in supervisor mode. Support for machine mode is already
available for CPUs that include the SiFive CLINT.
Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NAtish Patra <atish.patra@wdc.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>

Import the supervisor binary interface (SBI) header file from Linux
(arch/riscv/include/asm/sbi.h). The last change to it was in commit
6d60b6ee0c97 ("RISC-V: Device, timer, IRQs, and the SBI").
Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NAtish Patra <atish.patra@wdc.com>

Harts on RISC-V boot independently, U-Boot is responsible for managing
them. Functions are called on other harts with smp_call_function(),
which sends inter-processor interrupts (IPIs) to all other available
harts. Available harts are those marked as available in the device tree
and present in the available_harts mask stored in global data. The
available_harts mask is used to register all harts that have entered
U-Boot. Functions are specified with their address and two function
arguments (argument 2 and 3). The first function argument is always the
hart ID of the hart calling the function. On the other harts, the IPI
interrupt handler handle_ipi() must be called on software interrupts to
handle the request and call the specified function.

Functions are stored in the ipi_data data structure. Every hart has its
own data structure in global data. While this is not required at the
moment (all harts are expected to boot Linux), this does allow future
expansion, where other harts may be used for monitoring or other tasks.
Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>

After the commit: "eth: dm: fec: Add gpio phy reset binding"
SHA1: efd0b791

The FEC ETH driver switched to PHY GPIO reset performed with data defined
in DTS.
For the HSC|DDC boards the GPIO reset signal is active low and hence the
wrong DTS description must be changed (otherwise the reset for ETH is not
properly setup).
Signed-off-by: NLukasz Majewski <lukma@denx.de>

Activate I2C7 on Alt to allow access to the PMIC.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Due to a final resolution not coming up in time for 2019.04 and
following the consensus on the discussion, we'll keep this around
for 2019.04 after all.

This reverts commit 0d968ceb.

This converts the following to Kconfig:
  CONFIG_ENV_SPI_BUS
  CONFIG_ENV_SPI_CS
  CONFIG_ENV_SPI_MAX_HZ
  CONFIG_ENV_SPI_MODE

Most of time these value are not needed, CONFIG_SF_DEFAULT
with same value is used, so I introduced CONFIG_USE_ENV_SPI_*
to force the associated value for the environment.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

Replace CONFIG_ENV_SPI_BASE by the better CONFIG_SYS_SPI_BASE
(it is not the location for environment but the location for U-Boot)
and, as it is the only platform with use this define, remove
it from whitelist.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

An ADATA 16GB Industrial MLC card has so much capacitance on the Vcc
pin that the usual toggling of regulator to power the card off and on
is insufficient. When the card is calibrated into UHS SDR104 mode, it
will remain in that mode across the power cycle and subsequent attempt
to communicate with the card will fail.

The test with this card is to insert it into an SDHI slot and perform
"mmc dev 0 ; mmc dev 0", where the second "mmc dev 0" will fail.

Fix this problem by increasing the off-on delay from 0 to 20 mS.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Since commit 27cb7300 ("Ensure device tree DTS is compiled"),
build succeeds irrespective of the correctness of Makefile.

In fact, you can compile any defconfig without adding any entry in
arch/*/dts/Makefile.

I am going to revert that commit, so device tree must be explicitly
listed in Makefile.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>

Since commit 27cb7300 ("Ensure device tree DTS is compiled"),
build succeeds irrespective of the correctness of Makefile.

I am going to revert that commit, so wrong code must be fixed.

CONFIG_MCR3000 is not defined anywhere. CONFIG_TARGET_MCR3000 is the
correct one.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Since commit 27cb7300 ("Ensure device tree DTS is compiled"),
build succeeds irrespective of the correctness of Makefile.

In fact, you can compile any defconfig without adding any entry in
arch/*/dts/Makefile.

As a result, a lot of wrong code have been merged unnoticed.

I am going to revert that commit, and lots of hidden issues have
come to light:

[1] Typos

  armada-3720-uDPU.dts, sun8i-a83t-tbs-a711.dts

  use the extension ".dts" instead of ".dtb"

[2] DTB is associated to undefined CONFIG option

  For example, mx6sllevk_defconfig defines CONFIG_MX6SLL, but
  associates its device tree to CONFIG_MX6SL, which is undefined.

[3] Lots of entries are missing
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: NChris Packham <judge.packham@gmail.com>
[trini: add imx6ul pico dtbs]
Signed-off-by: NTom Rini <trini@konsulko.com>

Commit 1416e2d2 ("armv8: make SPL exception vectors optional") had a
typo in it which effectively disabled exception handling in SPL code always.

Since nobody complained, I guess we may as well disable exception handling
in SPL always by default.

So fix the bug to make the config option effective, but disable exception
handling in SPL by default. This gets us to the same functionality as before
by default, but with much less code included in the binary.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Reviewed-by: NMatthias Brugger <mbrugger@suse.com>
Reviewed-by: NAndre Przywara <andre.przywara@arm.com>

Push the Starting kernel print to the end just before the
dm_remove_devices call.
Signed-off-by: NKeerthy <j-keerthy@ti.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Prior to commit 93b283d4 ("ARM: CPU: arm926ejs: Consolidate cache
routines to common file") the kirkwood boards didn't have and dcache
support. The network and usb drivers rely on this. Set
CONFIG_SYS_DCACHE_OFF in the Kirkwood specific config.h.
Reported-by: NLeigh Brown <leigh@solinno.co.uk>
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Reviewed-by: NStefan Roese <sr@denx.de>
Signed-off-by: NStefan Roese <sr@denx.de>

When armada-385.dtsi was sync'd from Linux the name of the node
describing the pcie controller was changed from pcie-controller to pcie.
Some of the boards that include armada-385.dtsi were missed in the
update retaining the old name. This updates the affected boards.
Reported-by: NВлад Мао <vlaomao@gmail.com>
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Signed-off-by: NStefan Roese <sr@denx.de>

The conversion to DM_SPI managed to break accessing the environment on
dreamplug. This is because the environment code relies on being to able
to select the SPI device based on the sequence number. Add an alias so
that the spi0 bus gets sequence number 0.
Reported-by: NLeigh Brown <leigh@solinno.co.uk>
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Tested-by: NLeigh Brown <leigh@solinno.co.uk>
Signed-off-by: NStefan Roese <sr@denx.de>

Syscon register is required in dts to select correct
PHY interface.

Fix error below:

Net:   Failed to get syscon: -2
Signed-off-by: NLey Foon Tan <ley.foon.tan@intel.com>

Barrier transactions from CCI400 need to be disabled till
the DDR is configured, otherwise it may lead to system hang.
The patch adds workaround to fix the erratum.
Signed-off-by: NShengzhou Liu <Shengzhou.Liu@nxp.com>
Signed-off-by: NAlison Wang <alison.wang@nxp.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

spba-bus has a few nodes under it including the UART1 and
some ESPI buses.  In order to use them in SPL, the
u-boot,dm-spl flag needs to be added to the spba-bus@2000000
container.
Signed-off-by: NAdam Ford <aford173@gmail.com>

Currently the CPU frequency is incorrectly reported:

CPU:   NXP i.MX8QXP RevB A35 at 147228 MHz

Fix this problem by using a direct call to the SCU firmware to
retrieve the Cortex A35 CPU frequency.

With this change applied the CPU frequency is displayed correctly:

CPU:   NXP i.MX8QXP RevB A35 at 1200 MHz
Tested-by: NMarcelo Macedo <marcelo.macedo@nxp.com>
Signed-off-by: NFabio Estevam <festevam@gmail.com>
Tested-by: NAndrejs Cainikovs <andrejs.cainikovs@netmodule.com>

Select CONFIG_DM_MMC=y in order to support MMC driver model.

This allows the MMC board related code to be removed.
Signed-off-by: NFabio Estevam <festevam@gmail.com>
Acked-by: NOtavio Salvador <otavio@ossystems.com.br>

Import the device tree files from kernel 5.0-rc6 in preparation
for driver model conversion.
Signed-off-by: NFabio Estevam <festevam@gmail.com>
Acked-by: NOtavio Salvador <otavio@ossystems.com.br>

Use the i8254 sound driver to support creating simple beeps.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This is currently missing and without it the i8254 beeper driver
won't work.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The pc speaker driven by the i8254 is generic enough to deserve
a single dtsi file to be included by boards that use it.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The i8254 timer control IO port (0x43) should be setup correctly
by using PIT counter 2 to generate beeps, however in U-Boot other
codes like TSC driver utilizes PIT for TSC frequency calibration
and configures the counter 2 to a different mode that does not
beep. Fix this by always ensuring the PIT counter 2 is correctly
initialized so that the i8254 beeper driver works as expected.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Just add spaces around '=' sign for clarity.
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Add startup time to LDO regulators of S2MPS11 PMIC on Odroid XU3/XU4/HC1
family of boards to be sure the voltage is proper before relying on the
regulator.

The datasheet for all the S2MPS1x family is inconsistent here and does
not specify unambiguously the value of ramp delay for LDO.  It mentions
30 mV/us in one timing diagram but then omits it completely in LDO
regulator characteristics table (it is specified for bucks).

However the vendor kernels for Galaxy S5 and Odroid XU3 use values of 12
mV/us or 24 mV/us.

Without the ramp delay value the consumers do not wait for voltage
settle after changing it.  Although the proper value of ramp delay for
LDOs is unknown, it seems safer to use at least some value from
reference kernel than to leave it unset.
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: NLukasz Majewski <lukma@denx.de>
Tested-by: NAnand Moon <linux.amoon@gmail.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

The ADC block requires VDD supply to be on so provide one.
Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: NLukasz Majewski <lukma@denx.de>
Tested-by: NAnand Moon <linux.amoon@gmail.com>
Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>

Intel Edison has three UART ports, i.e.
 port 0 - Bluetooth
 port 1 - auxiliary, available for general purpose use
 port 2 - debugging, usually console output is here

Enable all of them for future use.
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

The console is actually serial #2. When we would like to enable other ports,
this would be not okay to mess up with the ordering.

Thus, fix the number of default console interface to be 2.
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

We may not do an assumption that current console device is always a first
of UCLASS_SERIAL one.

For example, on properly described Intel Edison board the console UART
is a third one.

Use current serial device as described in global data.

Fixes: a61cbad7 ("dm: serial: Adjust serial_getinfo() to use proper API")
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>