- 08 4月, 2019 12 次提交
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由 Rick Chen 提交于
The Platform-Level Interrupt Controller (PLIC) block holds memory-mapped claim and pending registers associated with software interrupt. It is required for handling IPI. Signed-off-by: NRick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
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由 Lukas Auer 提交于
Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: NAnup Patel <anup.patel@wdc.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Tested-by: NBin Meng <bmeng.cn@gmail.com>
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由 Lukas Auer 提交于
Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: NAnup Patel <anup.patel@wdc.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Lukas Auer 提交于
Print an error message and hang if smp_call_function() returns an error, indicating that relocation of the secondary harts has failed. Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Tested-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NAnup Patel <anup.patel@wdc.com>
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由 Lukas Auer 提交于
RISC-V U-Boot expects the hart ID to be passed to it via register a0 by the previous boot stage. Machine mode firmware such as BBL and OpenSBI do this when starting their payload (U-Boot) in supervisor mode. If U-Boot is running in machine mode, this task must be handled by the boot ROM. Explicitly populate register a0 with the hart ID from the mhartid CSR to avoid possible problems on RISC-V processors with a boot ROM that does not handle this task. Suggested-by: NRick Chen <rick@andestech.com> Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: NAnup Patel <anup.patel@wdc.com> Reviewed-by: NAtish Patra <atish.patra@wdc.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Tested-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NRick Chen <rick@andestech.com> Tested-by: NRick Chen <rick@andestech.com>
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由 Lukas Auer 提交于
Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: NAnup Patel <anup.patel@wdc.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Tested-by: NBin Meng <bmeng.cn@gmail.com>
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由 Lukas Auer 提交于
On RISC-V, all harts boot independently. To be able to run on a multi-hart system, U-Boot must be extended with the functionality to manage all harts in the system. All harts entering U-Boot are registered in the available_harts mask stored in global data. A hart lottery system as used in the Linux kernel selects the hart U-Boot runs on. All other harts are halted. U-Boot can delegate functions to them using smp_call_function(). Every hart has a valid pointer to the global data structure and a 8KiB stack by default. The stack size is set with CONFIG_STACK_SIZE_SHIFT. Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: NAnup Patel <anup.patel@wdc.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Tested-by: NBin Meng <bmeng.cn@gmail.com>
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由 Lukas Auer 提交于
The hart ID passed by the previous boot stage is currently stored in register s0. If we divert the control flow inside a function, which is required as part of multi-hart support, the function epilog may not be called, clobbering register s0. Save the hart ID in the unallocatable register tp instead to protect the hart ID. Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NRick Chen <rick@andestech.com> Reviewed-by: NAnup Patel <anup.patel@wdc.com>
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由 Lukas Auer 提交于
Move the initialization of the caches and the debug UART until after board_init_f_init_reserve. This is in preparation for SMP support, where code prior to this point will be executed by all harts. This ensures that initialization will only be performed once on the main hart running U-Boot. Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: NAnup Patel <anup.patel@wdc.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Lukas Auer 提交于
The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: NAnup Patel <anup.patel@wdc.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NAtish Patra <atish.patra@wdc.com> Tested-by: NBin Meng <bmeng.cn@gmail.com>
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由 Lukas Auer 提交于
Import the supervisor binary interface (SBI) header file from Linux (arch/riscv/include/asm/sbi.h). The last change to it was in commit 6d60b6ee0c97 ("RISC-V: Device, timer, IRQs, and the SBI"). Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: NAnup Patel <anup.patel@wdc.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NAtish Patra <atish.patra@wdc.com>
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由 Lukas Auer 提交于
Harts on RISC-V boot independently, U-Boot is responsible for managing them. Functions are called on other harts with smp_call_function(), which sends inter-processor interrupts (IPIs) to all other available harts. Available harts are those marked as available in the device tree and present in the available_harts mask stored in global data. The available_harts mask is used to register all harts that have entered U-Boot. Functions are specified with their address and two function arguments (argument 2 and 3). The first function argument is always the hart ID of the hart calling the function. On the other harts, the IPI interrupt handler handle_ipi() must be called on software interrupts to handle the request and call the specified function. Functions are stored in the ipi_data data structure. Every hart has its own data structure in global data. While this is not required at the moment (all harts are expected to boot Linux), this does allow future expansion, where other harts may be used for monitoring or other tasks. Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: NAnup Patel <anup.patel@wdc.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Tested-by: NBin Meng <bmeng.cn@gmail.com>
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- 05 4月, 2019 1 次提交
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git://git.denx.de/u-boot-imx由 Tom Rini 提交于
Fixes for 2019.04 - fix bashism for MX8 - fix ethernet for MX53 - fix docs for i.MX8
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- 03 4月, 2019 6 次提交
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由 Tom Rini 提交于
- Important Khadas VIM2 fix - Build fix for macOS Mojave - Build fix for gcc-4.7 for host tools.
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由 Thomas Petazzoni 提交于
Parts of the code are using C99 constructs (such as variables declared inside loops), but also GNU extensions (such as typeof), so using -std=gnu99 is necessary to build with older versions of gcc that don't default to building with gnu99. It fixes the following build failure: ./tools/../lib/crc16.c: In function "crc16_ccitt": ./tools/../lib/crc16.c:70:2: error: "for" loop initial declarations are only allowed in C99 mode for (int i = 0; i < len; i++) ^ ./tools/../lib/crc16.c:70:2: note: use option -std=c99 or -std=gnu99 to compile your code when building the host tools with gcc 4.7. Signed-off-by: NThomas Petazzoni <thomas.petazzoni@bootlin.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 認小默 提交于
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由 Neil Armstrong 提交于
The Khadas VIM2 defconfig was missing the USB PHY config and two other misc configs to setup dram banks and call misc_init_r. Align it on the other Amlogic SoC based boards defconfig. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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由 Neil Armstrong 提交于
The MESON_GXL_USB_PHY is also used on the Amlogic Meson GXM SoCs. Fixes: 2960e27e ("phy: Add Amlogic Meson USB2 & USB3 Generic PHY drivers") Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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- 02 4月, 2019 11 次提交
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由 Eugen Hristev 提交于
Fix missing at91 boards and split the at91 in two categories: at91 arm v7 at91 arm926esj which are the two main cores for the at91 architecture. Signed-off-by: NEugen Hristev <eugen.hristev@microchip.com>
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由 Lukasz Majewski 提交于
After the commit: "eth: dm: fec: Add gpio phy reset binding" SHA1: efd0b791 The FEC ETH driver switched to PHY GPIO reset performed with data defined in DTS. For the HSC|DDC boards the GPIO reset signal is active low and hence the wrong DTS description must be changed (otherwise the reset for ETH is not properly setup). Signed-off-by: NLukasz Majewski <lukma@denx.de>
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由 Lukasz Majewski 提交于
Signed-off-by: NLukasz Majewski <lukma@denx.de>
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由 Lukasz Majewski 提交于
After running tools/moveconfig.py it turned out that for various boards there are an empty #ifdef statements. Remove them to clean u-boot source code. Signed-off-by: NLukasz Majewski <lukma@denx.de>
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由 Krzysztof Kozlowski 提交于
The ohci driver calls board_usb_init(), not usb_board_init(). Signed-off-by: NKrzysztof Kozlowski <krzk@kernel.org>
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由 Fabio Estevam 提交于
Let the underline marker "=" fill the whole sentence for better readability. Signed-off-by: NFabio Estevam <festevam@gmail.com>
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由 Fabio Estevam 提交于
The DDR firmware binaries should be copied to '$(srctree)', so fix a typo. Signed-off-by: NFabio Estevam <festevam@gmail.com>
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由 Fabio Estevam 提交于
After building ATF it is needed to copy the generated bl31.bin file to the U-Boot source tree. Make this step explicit in the instructions. Signed-off-by: NFabio Estevam <festevam@gmail.com>
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由 Jagan Teki 提交于
CLK_AHB_GMAC was suppose to be part of previous commit "clk: sunxi: Implement A10 EMAC clocks" add it so-that we can get rid of sunxi_set_gate warning on boot message. Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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- 01 4月, 2019 8 次提交
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由 Baruch Siach 提交于
Use a single '=' to test string equality for compatibility with non-bash shells. Otherwise, if /bin/sh is dash, build fails: ./tools/imx8m_image.sh: 15: [: signed_hdmi_imx8m.bin: unexpected operator ./tools/imx8m_image.sh: 15: [: signed_hdmi_imx8m.bin: unexpected operator ./tools/imx8m_image.sh: 15: [: spl/u-boot-spl-ddr.bin: unexpected operator ./tools/imx8m_image.sh: 15: [: spl/u-boot-spl-ddr.bin: unexpected operator WARNING './spl/u-boot-spl-ddr.bin' not found, resulting binary is not-functional Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Tested-by: NChris Spencer <christopher.spencer@sea.co.uk>
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git://git.denx.de/u-boot-imx由 Tom Rini 提交于
Fixes for 2019.01 - pico-imx6ul: fix after conversion - engicam boards - pico-imx7d _ README due to hang with imx-usb-loader
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由 Fabio Estevam 提交于
Since commit 9e3c0174 ("pico-imx7d: Add LCD support") we started to notice some hangs in U-Boot. There is not an issue on such commit per se, but due to the LCD support the current drawn is increased and this may cause issues when powering pico-imx7d-pi from USB. Some computers may be a bit strict with USB current draw and will shut down their ports if the draw is too high. The solution for that is to use an externally powered USB hub between the board and the host computer. Add such recommendation to the README file. Signed-off-by: NFabio Estevam <festevam@gmail.com>
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由 Jagan Teki 提交于
SRAM address used for bootcount on exiting code is erasing previous count value when system reset from Linux. So use the dedicated imx6 scratch register, GPR2 to preserve the contents even if the system reset from Linux. Fixes: 4eb9aa39 ("configs: imx6qdl_icore_mmc: Enable watchdog and bootcounter") Signed-off-by: NMichael Trimarchi <michael@amarulasolutions.com> Signed-off-by: NJagan Teki <jagan@amarulasolutions.com> Tested-by: NShyam Saini <shyam.saini@amarulasolutions.com> Reviewed-by: NStefano Babic <sbabic@denx.de>
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由 Michael Trimarchi 提交于
SPL on Engicam i.Core M6 boards enabled DM, so it would require some malloc() pool before relocation in order to load U-Boot proper properly. So, enable SPL malloc() pool of 0x2000 size similarly like what we have used for icore mmc defconfigs. Reviewed-by: NJagan Teki <jagan@amarulasolutions.com> Tested-by: NShyam Saini <shyam.saini@amarulasolutions.com> Signed-off-by: NMichael Trimarchi <michael@amarulasolutions.com> Reviewed-by: NFabio Estevam <festevam@gmail.com>
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由 Adam Ford 提交于
With UUID support, the root can now point to UUID. This makes swiching between mmc 0 and mmc 1 easier by simplying changing mmcdev between 0 and 1. From there, the scripts handle the rest. Signed-off-by: NAdam Ford <aford173@gmail.com>
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由 Fabio Estevam 提交于
After the DM_MMC conversion the following eMMC boot error is observed: U-Boot SPL 2019.04-rc4 (Mar 20 2019 - 18:53:28 +0000) Trying to boot from MMC1 MMC Device 0 not found spl: could not find mmc device 0. error: -19 SPL: failed to boot from all boot devices ### ERROR ### Please RESET the board ### This happens because the SPL code does not initialize the SDHC pins and clock. Fix it by moving the original eMMC initialization from U-Boot proper to SPL. Reported-by: NOtavio Salvador <otavio@ossystems.com.br> Signed-off-by: NFabio Estevam <festevam@gmail.com> Tested-by: NFabio Berton <fabio.berton@ossystems.com.br> Reviewed-by: NOtavio Salvador <otavio@ossystems.com.br>
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- 31 3月, 2019 2 次提交
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git://git.denx.de/u-boot-rockchip由 Tom Rini 提交于
Last-minute fixes for Rockchip for 2019.04: - reverts the deprecation of the 'download-key' detection (with a full solution pending for the next release) - applies a temporary fix for the 32bit pinctrl registers on the RK3288
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