For T4 platform, the SRIO LIODN registers are in SRIO address space
and not in GUTs.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>

For B4, the SRIO LIODN registers are in SRIO address space and not
in GUTs.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>

For some PowerPC platforms, LIODN registers for SRIO ports are
in SRIO register address space. So the ccsr_rio structure should
be updated for those LIODN registers.

In addition, add a new macro "SET_SRIO_LIODN_BASE" to create
the SRIO LIODN ID table based on the SRIO LIODN register address.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Acked-by: NYork Sun <yorksun@freescale.com>

Now that nothing uses CONFIG_ARCH_DEVICE_TREE, stop defining it.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Current code uses gd->baudrate before setting its value.
Besides, I got below build warning which is introduced by
commit ddb5c5be "blackfin: add baudrate to bdinfo".

board.c:235:3: warning: passing argument 1 of 'simple_strtoul' makes pointer from integer without a cast [enabled by default]
include/vsprintf.h:27:7: note: expected 'const char *' but argument is of type 'unsigned int'

This patch ensures we get the baudrate setting before using it.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>

The function return from P_FUNCT2MUX(per) takes 2 bits, however
for BF537_FAMILY with offset != 1 the function is 1 bit.

Also has small refactor for better readability.
In portmux_setup(), it looks odd having "muxreg &= ~(3 << 1);"
while in current code we do muxreg |= (function << offset);.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>

In special_gpio_free(), call unreserve() rather than reserve() to release gpio.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>

Some version of Andes core support FPU coprocessor,
if this is the case, and toolchain support FPU instruction set,
we should enable it at low level initialization time.
Signed-off-by: NKuan-Yu Kuo <ken.kuoky@gmail.com>
Cc: Macpaul Lin <macpaul@gmail.com>

Signed-off-by: NTom Rini <trini@ti.com>

Signed-off-by: NKuan-Yu Kuo <ken.kuoky@gmail.com>
Cc: Macpaul Lin <macpaul@gmail.com>

Synchronize the code with mips64/cache.S, in order to
allow further unifications.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

Synchronize the code with mips64/cache.S, in order to
allow further unifications.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

Synchronize the code with mips64/cache.S, in order to
allow further unifications.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

Make it similar to the code in mips{32,64}/start.S, in order to
allow further unifications.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

Synchronize the code with mips{32,64}/start.S, in order to
allow further unifications.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

Make it similar to the code in mips64/start.S, in order to
allow further unifications.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

Synchronize the code with mips64/start.S, in order to
allow further unifications.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

The t4 register already holds the cache
line size, and the value of the register
is not changed in mips_init_icache.

Get the cache line size value from t4 for
mips_init_dcache as well and remove the
superfluous assignment of t5 register.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>

Nothing is used from asm/mipsregs.h.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

Checking mips32/time.c with checkpatch.pl shows this:

  arch/mips/cpu/mips32/time.c:30: WARNING: line over 80 characters
  arch/mips/cpu/mips32/time.c:57: ERROR: return is not a function, parentheses are not required
  total: 1 errors, 1 warnings, 0 checks, 85 lines checked

Fix the code to make checkpatch.pl happy.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

Move the GT64120 register base to 0x1be00000
and setup PCI BAR registers as done by the
original YAMON bootloader.

This is needed for running Linux kernel.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

The MIPS Malta board has a SOFTRES register. Writing a
magic value into that register initiates a board reset.

Use this feature to implement reset support.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

Add minimal support for the MIPS Malta CoreLV board
emulated by Qemu. The only supported peripherial is
the UART.

This is enough to boot U-Boot to the command prompt
both in little and big endian mode.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

On the origial Malta boards the REVISION register is
accessible at the 0x1fc00010 address. The contents of
this register gives information about the revision
of the Malta and Core Boards.

This register is used by the Linux kernel to identify
the actual board it is running on. However the register
is not emulated properly by Qemu, so put a hardcoded
value into the flash to make Linux work.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>

Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

Conflicts:

	arch/mips/cpu/mips64/start.S
Signed-off-by: NTom Rini <trini@ti.com>

Signed-off-by: NWolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: NTom Rini <trini@ti.com>

The timer3 counter unit for lastdesc and now values are inconsistent in current
code. The unit of "readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2)" is
second. However, CONFIG_SYS_HZ is defined as 1000 in board config file.
This means the accuracy of "lastdec" and "now" should be in millisecond,
thus fix the equation to set lastdec and now variables accordingly.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>

Add a header file, setup.h, which copy from Linux source code,
this file contain structures are used to pass initialisation parameters
to Linux. Enable this function on adp-ag101/adp-ag101p target
Signed-off-by: NKuan-Yu Kuo <ken.kuoky@gmail.com>
Cc: Macpaul Lin <macpaul@gmail.com>

The original adp-ag101/adp-ag101p initialize only one bank(64MB)
by default at boot time, but it is not enough for some application,
so increasing to two banks(128M).
Signed-off-by: NKuan-Yu Kuo <ken.kuoky@gmail.com>
Cc: Macpaul Lin <macpaul@gmail.com>

U-Boot does not compile for the adp-ag101 boards since
commit f6c3b346 (mmc:
update Faraday FTSDC010 for rw performance)

The driver assumes that the bit manipulation macros
are provided by all architectures. This is not the
case for nds32 and it causes a build error like this:

  ftsdc010_mci.c: In function 'ftsdc010_clkset':
  ftsdc010_mci.c:118: warning: implicit declaration of function 'setbits_le32'
  ftsdc010_mci.c:123: warning: implicit declaration of function 'clrbits_le32'
  drivers/mmc/libmmc.o: In function `ftsdc010_request':
  /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:234: undefined reference to `setbits_le32'
  /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:243: undefined reference to `clrbits_le32'
  /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:234: undefined reference to `clrbits_le32'
  drivers/mmc/libmmc.o: In function `ftsdc010_clkset':
  /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:118: undefined reference to `clrbits_le32'
  /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:118: undefined reference to `clrbits_le32'
  /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:121: undefined reference to `setbits_le32'
  /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:123: undefined reference to `setbits_le32'
  /devel/u-boot.git/drivers/mmc/ftsdc010_mci.c:123: undefined reference to `setbits_le32'

The patch adds bit manipulation macros for the
nds32 architecture to avoid the errors. The macros
are copied from the ARM implementation.

Compile tested only.

Cc: Kuo-Jung Su <dantesu@faraday-tech.com>
Cc: Macpaul Lin <macpaul@andestech.com>
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>

This patch adds I2C support for Vybrid VF610 platform and adds
I2C0 support to VF610TWR board.
Signed-off-by: NAlison Wang <b18965@freescale.com>

Signed-off-by: NDirk Eibach <dirk.eibach@gdsys.cc>
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefan Roese <sr@denx.de>
Tested-by: NStefan Roese <sr@denx.de>

CONFIG_I2C_MUX is replaced through the new i2c multibus/multiadapter
framework, configured through CONFIG_SYS_I2C. As CONFIG_I2C_MUX
is only used on the keymile boards, and they are now completely
moved to the new framework, remove CONFIG_I2C_MUX.
Signed-off-by: NHeiko Schocher <hs@denx.de>
Cc: Holger Brunck <holger.brunck@keymile.com>
Tested-By: NHolger Brunck <holger.brunck@keymile.com>

- added to fsl_i2c driver new multibus/multiadpater support
- adapted all config files, which uses this driver
Signed-off-by: NHeiko Schocher <hs@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>

- added to soft_i2c driver new multibus/multiadpater support
- adapted all config files, which uses this driver
Signed-off-by: NHeiko Schocher <hs@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>

Signed-off-by: NHeiko Schocher <hs@denx.de>
Signed-off-by: NSimon Glass <sjg@chromium.org>
Cc: Henrik Nordström <henrik@henriknordstrom.net>