nds32: Enable two banks of SDRAM on Andes board

The original adp-ag101/adp-ag101p initialize only one bank(64MB)
by default at boot time, but it is not enough for some application,
so increasing to two banks(128M).
Signed-off-by: NKuan-Yu Kuo <ken.kuoky@gmail.com>
Cc: Macpaul Lin <macpaul@gmail.com>

arch/nds32/cpu/n1213/ag101/lowlevel_init.S

@@ -38,6 +38,7 @@
 #define SDMC_CR1_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
 #define SDMC_CR2_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
 #define SDMC_B0_BSR_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
+#define SDMC_B1_BSR_A		(CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR)
 
 #define SDMC_TP1_D		CONFIG_SYS_FTSDMC021_TP1
 #define SDMC_TP2_D		CONFIG_SYS_FTSDMC021_TP2
@@ -45,6 +46,7 @@
 #define SDMC_CR2_D		CONFIG_SYS_FTSDMC021_CR2
 
 #define SDMC_B0_BSR_D		CONFIG_SYS_FTSDMC021_BANK0_BSR
+#define SDMC_B1_BSR_D		CONFIG_SYS_FTSDMC021_BANK1_BSR
 
 /*
  * parameters for the static memory controller
@@ -167,12 +169,12 @@ relo_base:
 	 */
 	led	0x1a
 	write32	SDMC_B0_BSR_A, SDMC_B0_BSR_D		! 0x00001100
+	write32	SDMC_B1_BSR_A, SDMC_B1_BSR_D		! 0x00001140
 
 	/* clear empty BSR registers */
 	led	0x1b
 	li	$r4, CONFIG_FTSDMC021_BASE
 	li	$r5, 0x0
-	swi	$r5, [$r4 + FTSDMC021_BANK1_BSR]
 	swi	$r5, [$r4 + FTSDMC021_BANK2_BSR]
 	swi	$r5, [$r4 + FTSDMC021_BANK3_BSR]
 
@@ -223,6 +225,8 @@ relo_base:
 	 * - after  remap: flash/rom 0x80000000, sdram: 0x00000000
 	 */
 	led	0x1c
+	write32 SDMC_B0_BSR_A, 0x00001000
+	write32 SDMC_B1_BSR_A, 0x00001040
 	setbf15	AHBC_CR_A, FTAHBC020S_CR_REMAP		! 0x1
 
 #endif /* #ifdef CONFIG_MEM_REMAP */

board/AndesTech/adp-ag101/adp-ag101.c

@@ -50,7 +50,7 @@ int board_init(void)
 int dram_init(void)
 {
 	unsigned long sdram_base = PHYS_SDRAM_0;
-	unsigned long expected_size = PHYS_SDRAM_0_SIZE;
+	unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
 	unsigned long actual_size;
 
 	actual_size = get_ram_size((void *)sdram_base, expected_size);
@@ -65,6 +65,14 @@ int dram_init(void)
 	return 0;
 }
 
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
+	gd->bd->bi_dram[0].size =  PHYS_SDRAM_0_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[1].size =  PHYS_SDRAM_1_SIZE;
+}
+
 int board_eth_init(bd_t *bd)
 {
 	return ftmac100_initialize(bd);

board/AndesTech/adp-ag101p/adp-ag101p.c

@@ -50,7 +50,7 @@ int board_init(void)
 int dram_init(void)
 {
 	unsigned long sdram_base = PHYS_SDRAM_0;
-	unsigned long expected_size = PHYS_SDRAM_0_SIZE;
+	unsigned long expected_size = PHYS_SDRAM_0_SIZE + PHYS_SDRAM_1_SIZE;
 	unsigned long actual_size;
 
 	actual_size = get_ram_size((void *)sdram_base, expected_size);
@@ -65,6 +65,14 @@ int dram_init(void)
 	return 0;
 }
 
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_0;
+	gd->bd->bi_dram[0].size =  PHYS_SDRAM_0_SIZE;
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[1].size =  PHYS_SDRAM_1_SIZE;
+}
+
 int board_eth_init(bd_t *bd)
 {
 	return ftmac100_initialize(bd);

include/configs/adp-ag101.h

@@ -235,6 +235,11 @@
 #define CONFIG_SYS_FTSDMC021_BANK0_BSR	(FTSDMC021_BANK_ENABLE	 |	\
 					 CONFIG_SYS_FTSDMC021_BANK0_BASE)
 
+#define CONFIG_SYS_FTSDMC021_BANK1_BASE \
+	(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
+#define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE   |      \
+		CONFIG_SYS_FTSDMC021_BANK1_BASE)
+
 #endif
 
 /*
@@ -248,9 +253,12 @@
 #else	/* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
 #define PHYS_SDRAM_0		0x10000000	/* SDRAM Bank #1 */
 #endif
+#define PHYS_SDRAM_1 \
+	(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)	/* SDRAM Bank #2 */
 
-#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define CONFIG_NR_DRAM_BANKS	2		/* we have 2 bank of DRAM */
 #define PHYS_SDRAM_0_SIZE	0x04000000	/* 64 MB */
+#define PHYS_SDRAM_1_SIZE	0x04000000	/* 64 MB */
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_0
 

include/configs/adp-ag101p.h

@@ -236,6 +236,10 @@
 #define CONFIG_SYS_FTSDMC021_BANK0_BSR	(FTSDMC021_BANK_ENABLE	 |	\
 					 CONFIG_SYS_FTSDMC021_BANK0_BASE)
 
+#define CONFIG_SYS_FTSDMC021_BANK1_BASE	\
+	(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
+#define CONFIG_SYS_FTSDMC021_BANK1_BSR	(FTSDMC021_BANK_ENABLE	 |	\
+					 CONFIG_SYS_FTSDMC021_BANK1_BASE)
 #endif
 
 /*
@@ -249,9 +253,12 @@
 #else	/* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
 #define PHYS_SDRAM_0		0x10000000	/* SDRAM Bank #1 */
 #endif
+#define PHYS_SDRAM_1 \
+	(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE)	/* SDRAM Bank #2 */
 
-#define CONFIG_NR_DRAM_BANKS	1		/* we have 1 bank of DRAM */
+#define CONFIG_NR_DRAM_BANKS	2		/* we have 2 bank of DRAM */
 #define PHYS_SDRAM_0_SIZE	0x04000000	/* 64 MB */
+#define PHYS_SDRAM_1_SIZE	0x04000000	/* 64 MB */
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_0