Signed-off-by: NDetlev Zundel <dzu@denx.de>

Add MPC8360EMDS_ATM_config and MPC832XEMDS_ATM_config into
Makfile and MAKEALL
Signed-off-by: NTony Li <tony.li@freescale.com>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

Correct to val8 from val.
Signed-off-by: NTony Li <tony.li@freescale.com>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NRunet Torgersen <runet@innovsys.com>

As a direct correlation exists between DDR DIMM slots
and SPD EEPROM addresses used to configure them, use
the individually defined SPD_EEPROM_ADDRESS* values to
determine if a DDR DIMM slot should have its SPD
configuration read or not.

Effectively, this now allows for 1 or 2 DIMM slots
per memory controller.
Signed-off-by: NJon Loeliger <jdl@freescale.com>

Some USB keys need to be switched off before loading the kernel
otherwise they can remain in an undefined status which prevents them
to be correctly recognized by the kernel.
Signed-off-by: NRodolfo Giometti <giometti@linux.it>

The I2C bootstrap values that can be setup via the "bootstrap" command,
were setup incorrect regarding the generation of the internal sync PCI
clock. The values for PLB clock == 133MHz were slighly incorrect and the
values for PLB clock == 166MHz were totally incorrect. This could
lead to a hangup upon booting while PCI configuration scan.

This patch fixes this issue and configures valid PCI divisor values
for the sync PCI clock, with respect to the provided external async
PCI frequency.

Here the values of the formula in the chapter 14.2 "PCI clocking"
from the 440EPx users manual:

AsyncPCICLK - 1MHz <= SyncPCIClk <= (2 * AsyncPCIClk) - 1MHz

33MHz async PCI frequency:
PLB = 133:
=>      32 <= 44.3 <= 65        (div = 3)

PLB = 166:
=>      32 <= 55.3 <= 65        (div = 3)

66MHz async PCI frequency:
PLB = 133:
=>      65 <= 66.5 <= 132       (div = 2)

PLB = 166:
=>      65 <= 83 <= 132         (div = 2)
Signed-off-by: NStefan Roese <sr@denx.de>

The BCSR status bit for the 66MHz PCI operation was correctly
addressed (MSB/LSB problem). Now the correct currently setup
PCI frequency is displayed upon bootup.

This patch also fixes this problem on Rainier & Yellowstone, since these
boards use the same souce code as Sequoia & Yosemite do.
Signed-off-by: NStefan Roese <sr@denx.de>

Adjust flash map to support the new S29GLxxN (N-Type) Flashes with
doubled sector size.
Signed-off-by: NMartin Krause <martin.krause@tqs.de>

Signed-off-by: NMartin Krause <martin.krause@tqs.de>

At 133 MHz the current SDRAM refresh rate is too fast
(measured 4 * 1.17 us).
CFG_MAMR_PTA changes from 39 to 97. This result
in a refresh rate of 4 * 7.8 us at the default clock
50 MHz. At 133 MHz the value will be then 4 * 2.9 us.
This is a compromise until a new method is found to
adjust the refresh rate.
Signed-off-by: NMartin Krause <martin.krause@tqs.de>

Adjust flash map to support the new S29GLxxN (N-Type) Flashes with
doubled sector size.
Signed-off-by: NMartin Krause <martin.krause@tqs.de>

and remove code violation

Signed-off-by: NWolfgang Denk <wd@denx.de>

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: NWolfgang Denk <wd@denx.de>

Signed-off-by: NWolfgang Denk <wd@denx.de>

Signed-off-by: NWolfgang Denk <wd@denx.de>

Signed-off-by: NGrzegorz Bernacki <gjb@semihalf.com>

The ATSTK1000-specific flash driver intializes bi_flashstart,
bi_flashsize and bi_flashoffset, but other flash drivers, like the CFI
driver, don't.

Initialize these in board_init_r instead so that things will still be
set up correctly when we switch to the CFI driver.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

Signed-off-by: NMarian Balakowicz <m8@semihalf.com>