AE250 is the Soc using NX25 cpu core base on RISC-V arch.
Details please see the doc/README.ae250.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Signed-off-by: NGreentime Hu <green.hu@gmail.com>

Add makefile, interrupts.c and boot.c,... functions
to support RISC-V arch.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Signed-off-by: NGreentime Hu <green.hu@gmail.com>
Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>

Add Andes nx25 cpu core (called AndesStar V5) to support RISC-V arch

Verifications:
1. startup and relocation ok.
2. boot from rom or ram both ok.
2. timer driver ok.
3. uart driver ok
4. mmc driver ok
5. spi driver ok.
6. 32/64 bit both ok.

Detail verification message please see doc/README.ae250.
Signed-off-by: NRick Chen <rick@andestech.com>
Signed-off-by: NRick Chen <rickchen36@gmail.com>
Signed-off-by: NGreentime Hu <green.hu@gmail.com>
Cc: Padmarao Begari <Padmarao.Begari@microsemi.com>

a64-olinuxino has 8GiB eMMC, enable it.
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

The clock selection is done now from the am335x-fb code, so there is no
more need doing this in the board code.
Signed-off-by: NHannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: NAnatolij Gustschin <agust@denx.de>

Actual am335x-fb implementation takes now a real clock frequency instead
a divider. So this component doesn't need to know anymore some base
frequency of the LCDC, we simply provide the pixel-clock frequency.
Signed-off-by: NHannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: NAnatolij Gustschin <agust@denx.de>

The LCDC IP-core an be feed from several clock sources, one of those is
a dedicated DPLL for generating a dividable base-clock for this IP-core.

The TRM specifies the maximum input frequency for the LCCD with 200 MHz,
so we must not exceed this value with the PLL frequency (which can lock
much higher).

This patch tries every combination of multipliers and divisors of the
PLL and the IP-core itself for getting as near as possible the the
requested panel->pxl_clk.
Signed-off-by: NHannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: NAnatolij Gustschin <agust@denx.de>

Signed-off-by: NHannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: NAnatolij Gustschin <agust@denx.de>

Signed-off-by: NHannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: NAnatolij Gustschin <agust@denx.de>

Adds the register definition of the Display DPLL
Signed-off-by: NHannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: NAnatolij Gustschin <agust@denx.de>

Signed-off-by: NUdit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: NSumit Garg <sumit.garg@nxp.com>
[YS: run moveconfig.py -s]
Reviewed-by: NYork Sun <york.sun@nxp.com>

Using changes in this patch we were able to reduce approx 8k
size of u-boot-spl.bin image. Following is breif description of
changes to reduce SPL size:
1. Changes in board/freescale/ls1088a/Makefile to remove
   compilation of eth.c and cpld.c in case of SPL build.
2. Changes in board/freescale/ls1088a/ls1088a.c to keep
   board_early_init_f funcations in case of SPL build.
3. Changes in ls1088a_common.h & ls1088ardb.h to remove driver
   specific macros due to which static data was being compiled in
   case of SPL build.
Signed-off-by: NSumit Garg <sumit.garg@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Compile-off mp.c and libfdt.c in case of SPL build. SPL size reduces
by approx 2k.
Signed-off-by: NSumit Garg <sumit.garg@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Remove duplicate macro CONFIG_FSL_PCIE_RESET and update its comment.
It enables PCIe reset to fix link width 2x - 4x.
Signed-off-by: NBao Xiaowei <xiaowei.bao@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

855873: An eviction might overtake a cache clean operation
Workaround: The erratum can be avoided by upgrading cache clean by
address operations to cache clean and invalidate operations. For
Cortex-A53 r0p3 and later release, this can be achieved by setting
CPUACTLR.ENDCCASCI to 1.

This patch is to implement the workaround for this erratum.
Signed-off-by: NAlison Wang <alison.wang@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The CONFIG_SYS_DPAA_QBMAN define is used by DPAA1 freescale SOCs to
add device tree fixups that allow deep sleep in Linux. The define was
placed in header files included by a number of boards, but was not
explicitly documented in any of the Kconfigs. A description was added
to the drivers/networking menuconfig and default selection for
current SOCs that have this part
Signed-off-by: NAhmed Mansour <ahmed.mansour@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This patch adds changes necessary to move functionality present in
PowerPC folders with ARM architectures that have DPAA1 QBMan hardware

- Create new board/freescale/common/fsl_portals.c to house shared
  device tree fixups for DPAA1 devices with ARM and PowerPC cores
- Add new header file to top includes directory to allow files in
  both architectures to grab the function prototypes
- Port inhibit_portals() from PowerPC to ARM. This function is used in
  setup to disable interrupts on all QMan and BMan portals. It is
  needed because the interrupts are enabled by default for all portals
  including unused/uninitialised portals. When the kernel attempts to
  go to deep sleep the unused portals prevent it from doing so
Signed-off-by: NAhmed Mansour <ahmed.mansour@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Sata registers PP2C and PP3C are used to control the configuration
of the PHY control OOB timing for the COMINIT/COMWAKE parameters
respectively. Calculate those parameters from port clock frequency.
Overwrite those registers with calculated values to get better OOB
timing.
Signed-off-by: NTang Yuantian <andy.tang@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Signed-off-by: NAshish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Given gcc-6.1 and later we can now safely have strings discarded when
the functions are unused.  This lets us drop certain cases of not
building something so that we don't have the strings brought in when the
code was discarded.  Simplify the code now by dropping guards we don't
need now.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Chander Kashyap <k.chander@samsung.com>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Wenyou Yang <wenyou.yang@microchip.com>
Signed-off-by: NTom Rini <trini@konsulko.com>

commit 21a24c3b ("fs/fat: fix case for FAT shortnames") made it
possible that get_name() returns file names with some upper cases.
find_directory_entry() must be updated to take this account, and use
case-insensitive functions to compare file names.
Signed-off-by: NJean-Jacques Hiblot <jjhiblot@ti.com>

Follow Linux commit ed067d4a859f ("linux/kernel.h: Add ALIGN_DOWN
macro").
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The following config symbols are only defined once and never referenced
anywhere else:

CONFIG_AP325RXA
CONFIG_AP_SH4A_4A
CONFIG_CPU_SH_TYPE_R
CONFIG_ECOVEC
CONFIG_ESPT
CONFIG_MIGO_R
CONFIG_MPR2
CONFIG_MS7720SE
CONFIG_MS7722SE
CONFIG_MS7750SE
CONFIG_R0P7734
CONFIG_R2DPLUS
CONFIG_RSK7203
CONFIG_RSK7264
CONFIG_RSK7269
CONFIG_SH7752EVB
CONFIG_SH7753EVB
CONFIG_SH7757LCR
CONFIG_SH7763RDP
CONFIG_SH7785LCR

Most of them are config symbols named after the respective boards which
seems to have been a standard practice at some point.
Signed-off-by: NTuomas Tynkkynen <tuomas@tuxera.com>

These macros are all defined once and never checked or used anywhere:

CONFIG_MACH_ASPENITE
CONFIG_MACH_DAVINCI_CALIMAIN
CONFIG_MACH_DOCKSTAR
CONFIG_MACH_EDMINIV2
CONFIG_MACH_GOFLEXHOME
CONFIG_MACH_GONI
CONFIG_MACH_GURUPLUG
CONFIG_MACH_KM_KIRKWOOD
CONFIG_MACH_OPENRD_BASE
CONFIG_MACH_SHEEVAPLUG

Almost all of them were only used for the mach_is_foo() logic in
arch/arm/asm/mach-types.h that were dropped in
commit f9dadaef ("arm: Re-sync asm/mach-types.h with
Linux Kernel v4.9")
Signed-off-by: NTuomas Tynkkynen <tuomas@tuxera.com>

Configure AM57xx EVMs for the exact PHY part that is
present on the various boards. This makes U-Boot apply
configurations needed for this PHY like centering the
FLP timing.

For configurations to take effect, DM_ETH needs to be
enabled. Do that too.

Tested on BeagleBoard x15 and AM571x IDK.
Reviewed-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

The 't208xrdb t4qds t102*' job is close to the time limit and
sometimes fails, so this splits it into 3 separate jobs.
Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>

Last user of this option went away in 2015 in commit:
d928664f ("powerpc: 74xx_7xx: remove 74xx_7xx cpu support")
Signed-off-by: NTuomas Tynkkynen <tuomas@tuxera.com>

BCM2835 ARM Peripherals doc shows gpio pins 4, 5, 6, 12 and 13 carry altenate
function, ALT5 for ARM JTAG
Signed-off-by: NHenry Zhang <henryzhang62@yahoo.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

STM32F469-disco embeds an arm_pl180 mmc IP, so
enable CMD_MMC, DM_MMC and ARM_PL180_MMCI flags.

Also enables all filesystem command related flags :
  _ CMD_EXT2
  _ CMD_EXT4
  _ CMD_FAT
  _ CMD_FS_GENERIC
  _ CMD_GPT
  _ CMD_BOOTZ
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add DT nodes to enable ARM_PL180_MMCI IP support for STM32F746
and STM32F769 discovery boards

There is a hardware issue on these boards, it misses a pullup on the GPIO line
used as card detect to allow correct SD card detection.
As workaround, cd-gpios property is not present in DT.
So SD card is always considered present in the slot.
Signed-off-by: NChristophe Priouzeau <christophe.priouzeau@st.com>
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

STM32F469 SoC uses an arm_pl180_mmci SDIO controller.
Signed-off-by: NAndrea Merello <andrea.merello@gmail.com>
Signed-off-by: NAlexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

This board offers :

 _ STM32F469NIH6 microcontroller featuring 2 Mbytes of Flash memory
   and 324 Kbytes of RAM in BGA216 package
 _ On-board ST-LINK/V2-1 SWD debugger, supporting USB reenumeration capability:
     _ Mbed-enabled (mbed.org)
     _ USB functions: USB virtual COM port, mass storage, debug port
 _ 4 inches 800x480 pixel TFT color LCD with MIPI DSI interface and capacitive
   touch screen
 _ SAI Audio DAC, with a stereo headphone output jack
 _ 3 MEMS microphones
 _ MicroSD card connector
 _ I2C extension connector
 _ 4Mx32bit SDRAM
 _ 128-Mbit Quad-SPI NOR Flash
 _ Reset and wake-up buttons
 _ 4 color user LEDs
 _ USB OTG FS with Micro-AB connector
 _ Three power supply options:
 _ Expansion connectors and Arduino™ UNO V3 connectors
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

  _ Add gpio compatible and aliases for stm32f469

  _ Add FMC sdram node

  _ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl,
    pwrcfg and gpio nodes.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>

This DT file comes from kernel v4.15-rc1

stm32f469-pinctrl.dtsi header has been updated with correct
STMicroelectronics Copyright.

Remove the paragraph about writing to the Free Software
Foundation's mailing address as requested by checkpatch.
Signed-off-by: NPatrice Chotard <patrice.chotard@st.com>