- 01 9月, 2012 40 次提交
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由 Allen Martin 提交于
This is make naming consistent with the kernel and devicetree and in preparation of pulling out the common tegra20 code. Signed-off-by: NAllen Martin <amartin@nvidia.com> Acked-by: NStephen Warren <swarren@wwwdotorg.org> Tested-by: NThierry Reding <thierry.reding@avionic-design.de> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Stephen Warren 提交于
This SoC is used in the Raspberry Pi, for example. For more details, see: http://www.broadcom.com/products/BCM2835 http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf. Initial support is enough to boot to a serial console, execute a minimal set of U-Boot commands, download data over a serial port, and boot a Linux kernel. No storage or network drivers are implemented. GPIO driver originally by Vikram Narayanan <vikram186@gmail.com> with many fixes from myself. Signed-off-by: NStephen Warren <swarren@wwwdotorg.org>
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由 Mathieu J. Poirier 提交于
Register mapping has changed on power control chip between the first and second revision. Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: NJohn Rigby <john.rigby@linaro.org> Signed-off-by: NTom Rini <trini@ti.com>
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由 Mathieu J. Poirier 提交于
Functions such as providing power to the MMC device and reading the processor version register should be in the cpu area for access by multiple u8500-based boards. Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: NJohn Rigby <john.rigby@linaro.org> Signed-off-by: NTom Rini <trini@ti.com>
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由 Mathieu J. Poirier 提交于
LAN and GBF need to be powered explicitely, doing so with interface to AB8500 companion chip. Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: NJohn Rigby <john.rigby@linaro.org>
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由 Mathieu J. Poirier 提交于
Addresses between ux500.v1 and ux500.v2 have changed slightly, hence mandating a review of the PRCMU access methods. Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: NJohn Rigby <john.rigby@linaro.org>
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由 Mathieu J. Poirier 提交于
Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: NJohn Rigby <john.rigby@linaro.org>
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由 Mathieu J. Poirier 提交于
Enabling timers and clocks in PRCMU and cleaning up mailbox. Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: NJohn Rigby <john.rigby@linaro.org>
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由 Mathieu J. Poirier 提交于
This is to allow the prcmu functions to be used by multiple u8500-based processors. Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: NJohn Rigby <john.rigby@linaro.org>
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由 Mathieu J. Poirier 提交于
Signed-off-by: NMathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: NJohn Rigby <john.rigby@linaro.org> Acked-by: NTom Rini <trini@ti.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Conflicts: drivers/gpio/Makefile
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由 Satyanarayana, Sandhya 提交于
This patch updates secure_emif_sdram_config with the same value written to sdram_config during ddr3 initialization. During suspend/resume, this value is copied into sdram_config. With this, a write to sdram_config at the end of resume sequence which triggers an init sequence can be avoided. Without this register write in place, the DDR_RESET line goes low for a few cycles during resume which is a violation of the JEDEC spec. Signed-off-by: NSatyanarayana, Sandhya <sandhya.satyanarayana@ti.com>
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由 Sughosh Ganu 提交于
Also enable the ohci port on hawkboard. These additions result in an increased u-boot size -- adjust the same accordingly in the board's config. Move the usb header for da8xx platforms under arch-davinci. Signed-off-by: NSughosh Ganu <urwithsughosh@gmail.com>
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由 Tom Rini 提交于
Make the lowlevel_init function that these platforms have which just sets up the stack and calls a C function available to all armv7 platforms. As part of this we change some of the macros that are used to be more clear. Previously (except for am335x evm) we had been setting CONFIG_SYS_INIT_SP_ADDR to a series of new defines that are equivalent to simply referencing NON_SECURE_SRAM_END. On am335x evm we should have been doing this initially and do now. Cc: Sricharan R <r.sricharan@ti.com> Tested-by: NAllen Martin <amartin@nvidia.com> Signed-off-by: NTom Rini <trini@ti.com>
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由 Tom Rini 提交于
- Correct the MMC1 base offset - Remove MMC2 (that area is reserved and not MMC2). - Add the real BOOT_DEVICE_MMC2 value Signed-off-by: NTom Rini <trini@ti.com>
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由 Otavio Salvador 提交于
Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>
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由 Otavio Salvador 提交于
Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>
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由 Otavio Salvador 提交于
As the register accessing mode is the same for all i.MXS SoCs we ought to use 'mxs' prefix intead of 'mx28'. Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>
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由 Otavio Salvador 提交于
Most code can be shared between i.MX23 and i.MX28 as both are from i.MXS family; this source directory structure makes easy to share code among them. Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br> Acked-by: NStefano Babic <sbabic@denx.de>
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由 Otavio Salvador 提交于
The information now is gathered from HW_DIGCTL_CHIPID register and includes the chip modem and revision on the output. Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>
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由 Bo Shen 提交于
Add at91sam9x5ek board support, this board support the following SoCs AT91SAM9G15, AT91SAM9G25, AT91SAM9G35, AT91SAM9X25, AT91SAM9X35 Using at91sam9x5ek_nandflash to configure for the board Now only supports NAND with software ECC boot up Signed-off-by: NBo Shen <voice.shen@atmel.com> [move MAINTAINERS entry to right place] Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Laurence Withers 提交于
Replace a magic number for the DDR2/mDDR PHY clock ID with a proper definition. In addition, don't request this clock ID on DA830 hardware, which does not have a DDR2/mDDR PHY (or associated PLL controller). Signed-off-by: NLaurence Withers <lwithers@guralp.com> Cc: Tom Rini <trini@ti.com> Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
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由 Laurence Withers 提交于
On the DA830, UART2's clock is derived from PLL controller 0 output 2. On the DA850, it is in the ASYNC3 group, and may be switched between PLL controller 0 or 1. Fix the definition of the ID to match. Signed-off-by: NLaurence Withers <lwithers@guralp.com> Cc: Tom Rini <trini@ti.com> Cc: Prabhakar Lad <prabhakar.csengg@gmail.com>
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由 Laurence Withers 提交于
Tidy up the clock IDs defined for the DA8xx SOCs. With this new structure in place, it is clear how to define new clock IDs, and how these map to the numbers presented in the technical reference manual. Signed-off-by: NLaurence Withers <lwithers@guralp.com> Cc: Tom Rini <trini@ti.com> Cc: Prabhakar Lad <prabhakar.csengg@gmail.com> Signed-off-by: NTom Rini <trini@ti.com>
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由 Tom Rini 提交于
- Move definition of the EEPROM contents to <asm/arch/sys_proto.h> - Make some defines a little less generic now. - Pinmux must be done by done by SPL now. - Create 3 pinmux functions, uart0, i2c0 and board. - Add pinmux specific to Starter Kit EVM for MMC now. Signed-off-by: NTom Rini <trini@ti.com>
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由 Tom Rini 提交于
- Board requires gpio0 #7 to be set to power DDR3. - Board uses DDR3, add a way to determine which DDR type to call config_ddr with. - Both of the above require filling in the header structure early, move it into the data section. Signed-off-by: NTom Rini <trini@ti.com>
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由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@ti.com>
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由 Tom Rini 提交于
The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry. Correct this by documenting a missing register that will be used at some point in the future (when write leveling is supported). Further, the cmdNcs{force,delay} fields are undocumented and we have been setting them to zero, remove. Next, setting of the 'DATAn_REG_PHY_USE_RANK0_DELAYS field belongs with the rest of the ddr_data entries, so program it there. Finally, comment on how we are configuring the DATA1 registers that correspond to the DATA0 (dt0) registers defined in the struct. Signed-off-by: NTom Rini <trini@ti.com>
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由 Tom Rini 提交于
The various ratio1 fields are not documented in any of the documentation I can find. Removing these and testing has yielded success, so remove the code that sets them and move their locations into the reserved fields. Signed-off-by: NTom Rini <trini@ti.com>
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由 Tom Rini 提交于
This function sets a number of related registers to the same value (the registers in question all have the same field descriptions and are related in operation). Rather than defining a struct and setting the value repeatedly, just pass in the value. Signed-off-by: NTom Rini <trini@ti.com>
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由 Tom Rini 提交于
Rather than defining our own structs to note what to use when programming the EMIF and related re-use the emif_regs struct. Signed-off-by: NTom Rini <trini@ti.com>
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由 Tom Rini 提交于
A number of memory initalization functions were int and always returned 0. Further it's not feasible to be doing error checking here, so simply turn them into void functions. Signed-off-by: NTom Rini <trini@ti.com>
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由 Tom Rini 提交于
- Remove the call to set ddrctrl->ddrioctrl as it's all zeros. - Comment what we're really setting in ddrctrl->ddrckectrl which is that we're operating in the normal mode where EMIF/PHY clock is controlled by the PHY. Signed-off-by: NTom Rini <trini@ti.com>
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由 Vaibhav Bedia 提交于
EMIF parameters are calculated based on the AC timing parameters from the SDRAM datasheet and the DDR frequency. Current values for these paramters in AM335x U-Boot code, though reliable, are not fully optimal. The most optimal settings can be derived based on the guidelines published at [1]. A pre-computed set of values with the most optimum settings for AM335x EVM and BeagleBone can be found at [2]. [1] http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips [2] http://processors.wiki.ti.com/index.php/OMAP_and_Sitara_CCS_support#AM335xSigned-off-by: NVaibhav Bedia <vaibhav.bedia@ti.com> Signed-off-by: NTom Rini <trini@ti.com>
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由 Tom Rini 提交于
- Remove a handful of unused defines. - Prefix more values with 'DDR2' as DDR3 will require different values. Signed-off-by: NTom Rini <trini@ti.com>
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由 Tom Rini 提交于
Depending on if we have DDR2 or DDR3 on the board we will need to call ddr_pll_config with a different value. This call can be delayed slightly to the point where we know which type of memory we have. Signed-off-by: NTom Rini <trini@ti.com>
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由 Tom Rini 提交于
We need to pass in the type of memory that is connected to the board. The only reliable way to do this is to know what type of board we are running on (which later will be knowable in s_init()). For now, pass in the value of DDR2. Signed-off-by: NTom Rini <trini@ti.com>
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由 Tom Rini 提交于
Rework the EMIF4/DDR code slightly to setup the structs that config_cmd_ctrl and config_ddr_data take to be setup at compile time and mark them as const. This lets us simplify the calling path slightly as well as making it easier to deal with DDR3. Signed-off-by: NTom Rini <trini@ti.com>
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由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@ti.com>
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由 Tom Rini 提交于
The am33xx does not have a DMM, so don't define the base. Signed-off-by: NTom Rini <trini@ti.com>
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由 Javier Martinez Canillas 提交于
Signed-off-by: NJavier Martinez Canillas <javier@dowhile0.org>
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