提交 cc0427d2 编写于 作者: T Tom Rini
* I2C controller embedded in STMicroelectronis STM32 platforms
Required properties :
- compatible : Must be "st,stm32f7-i2c"
- reg : Offset and length of the register set for the device
- resets: Must contain the phandle to the reset controller
- clocks: Must contain the input clock of the I2C instance
- A pinctrl state named "default" must be defined to set pins in mode of
operation for I2C transfer
- #address-cells = <1>;
- #size-cells = <0>;
Optional properties :
- clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
the default 100 kHz frequency will be used. As only Normal, Fast and Fast+
modes are implemented, possible values are 100000, 400000 and 1000000.
Example :
i2c1: i2c@40005400 {
compatible = "st,stm32f7-i2c";
reg = <0x40005400 0x400>;
resets = <&rcc 181>;
clocks = <&clk_pclk1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
};
......@@ -174,6 +174,26 @@ config SYS_I2C_S3C24X0
help
Support for Samsung I2C controller as Samsung SoCs.
config SYS_I2C_STM32F7
bool "STMicroelectronics STM32F7 I2C support"
depends on (STM32F7 || STM32H7) && DM_I2C
help
Enable this option to add support for STM32 I2C controller
introduced with STM32F7/H7 SoCs. This I2C controller supports :
_ Slave and master modes
_ Multimaster capability
_ Standard-mode (up to 100 kHz)
_ Fast-mode (up to 400 kHz)
_ Fast-mode Plus (up to 1 MHz)
_ 7-bit and 10-bit addressing mode
_ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
_ All 7-bit addresses acknowledge mode
_ General call
_ Programmable setup and hold times
_ Easy to use event management
_ Optional clock stretching
_ Software reset
config SYS_I2C_UNIPHIER
bool "UniPhier I2C driver"
depends on ARCH_UNIPHIER && DM_I2C
......
......@@ -37,6 +37,7 @@ obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o exynos_hs_i2c.o
obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o
obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
obj-$(CONFIG_SYS_I2C_STM32F7) += stm32f7_i2c.o
obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o
obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o
obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o
......
......@@ -34,3 +34,12 @@ config I2C_MUX_PCA954x
paritioning I2C bus and connect multiple devices with the same address
to the same I2C controller where driver handles proper routing to
target i2c device. PCA9544 and PCA9548 are supported.
config I2C_MUX_GPIO
tristate "GPIO-based I2C multiplexer"
depends on I2C_MUX && DM_GPIO
help
If you say yes to this option, support will be included for
a GPIO based I2C multiplexer. This driver provides access to
I2C busses connected through a MUX, which is controlled
through GPIO pins.
......@@ -6,3 +6,4 @@
obj-$(CONFIG_I2C_ARB_GPIO_CHALLENGE) += i2c-arb-gpio-challenge.o
obj-$(CONFIG_$(SPL_)I2C_MUX) += i2c-mux-uclass.o
obj-$(CONFIG_I2C_MUX_PCA954x) += pca954x.o
obj-$(CONFIG_I2C_MUX_GPIO) += i2c-mux-gpio.o
/*
* I2C multiplexer using GPIO API
*
* Copyright 2017 NXP
*
* Peng Fan <peng.fan@nxp.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/io.h>
#include <asm-generic/gpio.h>
#include <common.h>
#include <dm.h>
#include <dm/pinctrl.h>
#include <fdtdec.h>
#include <i2c.h>
#include <linux/errno.h>
DECLARE_GLOBAL_DATA_PTR;
/**
* struct i2c_mux_gpio_priv - private data for i2c mux gpio
*
* @values: the reg value of each child node
* @n_values: num of regs
* @gpios: the mux-gpios array
* @n_gpios: num of gpios in mux-gpios
* @idle: the value of idle-state
*/
struct i2c_mux_gpio_priv {
u32 *values;
int n_values;
struct gpio_desc *gpios;
int n_gpios;
u32 idle;
};
static int i2c_mux_gpio_select(struct udevice *dev, struct udevice *bus,
uint channel)
{
struct i2c_mux_gpio_priv *priv = dev_get_priv(dev);
int i, ret;
for (i = 0; i < priv->n_gpios; i++) {
ret = dm_gpio_set_value(&priv->gpios[i], (channel >> i) & 1);
if (ret)
return ret;
}
return 0;
}
static int i2c_mux_gpio_deselect(struct udevice *dev, struct udevice *bus,
uint channel)
{
struct i2c_mux_gpio_priv *priv = dev_get_priv(dev);
int i, ret;
for (i = 0; i < priv->n_gpios; i++) {
ret = dm_gpio_set_value(&priv->gpios[i], (priv->idle >> i) & 1);
if (ret)
return ret;
}
return 0;
}
static int i2c_mux_gpio_probe(struct udevice *dev)
{
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
struct i2c_mux_gpio_priv *mux = dev_get_priv(dev);
struct gpio_desc *gpios;
u32 *values;
int i = 0, subnode, ret;
mux->n_values = fdtdec_get_child_count(fdt, node);
values = devm_kzalloc(dev, sizeof(*mux->values) * mux->n_values,
GFP_KERNEL);
if (!values) {
dev_err(dev, "Cannot alloc values array");
return -ENOMEM;
}
fdt_for_each_subnode(subnode, fdt, node) {
*(values + i) = fdtdec_get_uint(fdt, subnode, "reg", -1);
i++;
}
mux->values = values;
mux->idle = fdtdec_get_uint(fdt, node, "idle-state", -1);
mux->n_gpios = gpio_get_list_count(dev, "mux-gpios");
if (mux->n_gpios < 0) {
dev_err(dev, "Missing mux-gpios property\n");
return -EINVAL;
}
gpios = devm_kzalloc(dev, sizeof(struct gpio_desc) * mux->n_gpios,
GFP_KERNEL);
if (!gpios) {
dev_err(dev, "Cannot allocate gpios array\n");
return -ENOMEM;
}
ret = gpio_request_list_by_name(dev, "mux-gpios", gpios, mux->n_gpios,
GPIOD_IS_OUT_ACTIVE);
if (ret <= 0) {
dev_err(dev, "Failed to request mux-gpios\n");
return ret;
}
mux->gpios = gpios;
return 0;
}
static const struct i2c_mux_ops i2c_mux_gpio_ops = {
.select = i2c_mux_gpio_select,
.deselect = i2c_mux_gpio_deselect,
};
static const struct udevice_id i2c_mux_gpio_ids[] = {
{ .compatible = "i2c-mux-gpio", },
{}
};
U_BOOT_DRIVER(i2c_mux_gpio) = {
.name = "i2c_mux_gpio",
.id = UCLASS_I2C_MUX,
.of_match = i2c_mux_gpio_ids,
.ops = &i2c_mux_gpio_ops,
.probe = i2c_mux_gpio_probe,
.priv_auto_alloc_size = sizeof(struct i2c_mux_gpio_priv),
};
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