Add support for CATcenter board (based on PPChameleon ME module)

10767ccb · wdenk · 02b11f8e · 10767ccb · 10767ccb · 10767ccb
Showing with 848 addition and 144 deletion

CHANGELOG CHANGELOG +2 -0

Makefile Makefile +5 -0

include/configs/CATcenter.h include/configs/CATcenter.h +703 -0

include/configs/PPChameleonEVB.h include/configs/PPChameleonEVB.h +138 -144

未找到文件。
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,8 @@
 Changes since U-Boot 1.1.1:
 ======================================================================

+* Add support for CATcenter board (based on PPChameleon ME module)
+
 * Patch by Klaus Heydeck, 12 May 2004:
  Using external watchdog for KUP4 boards in mpc8xx/cpu.c;
  load_sernum_ethaddr() for KUP4 boards in lib_ppc/board.c;

--- a/Makefile
+++ b/Makefile
@@ -548,6 +548,11 @@ BUBINGA405EP_config:	unconfig
 CANBT_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx canbt esd

+CATcenter_config:	unconfig
+	@ echo "/* CATcenter uses PPChameleon Model ME */"  > include/config.h
+	@ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 1" >> include/config.h
+	@./mkconfig -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
+
 CPCI405_config	\
 CPCI4052_config	\
 CPCI405AB_config:	unconfig

--- a/include/configs/CATcenter.h
+++ b/include/configs/CATcenter.h
--- a/include/configs/PPChameleonEVB.h
+++ b/include/configs/PPChameleonEVB.h
@@ -92,9 +92,10 @@
 				CFG_CMD_EEPROM	| \
 				CFG_CMD_I2C	| \
 				CFG_CMD_IRQ	| \
+				CFG_CMD_JFFS2	| \
 				CFG_CMD_MII	| \
 				CFG_CMD_NAND	| \
-				CFG_CMD_JFFS2)
+				CFG_CMD_PCI	)

 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -136,9 +137,9 @@
 #define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

-#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
+#undef	CFG_EXT_SERIAL_CLOCK		/* no external serial clock used */
 #define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
-#define CFG_BASE_BAUD	    691200
+#define CFG_BASE_BAUD		691200

 /* The following table includes the supported baudrates */
 #define CFG_BAUDRATE_TABLE	\
@@ -339,8 +340,8 @@
 #define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

 #if 0 /* test-only */
-#define CFG_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
+#define CFG_JFFS2_FIRST_BANK	0	 /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS	1	 /* ! second bank contains U-Boot */
 #endif

 /*-----------------------------------------------------------------------
@@ -460,34 +461,27 @@
 #define CFG_FPGA_STATUS_FLASH	0x0008
 #define CFG_FPGA_STATUS_TS_IRQ	0x1000

-#define CFG_FPGA_SPARTAN2	1	    /* using Xilinx Spartan 2 now    */
-#define CFG_FPGA_MAX_SIZE	128*1024    /* 128kByte is enough for XC2S50E*/
+#define CFG_FPGA_SPARTAN2	1		/* using Xilinx Spartan 2 now	 */
+#define CFG_FPGA_MAX_SIZE	128*1024	/* 128kByte is enough for XC2S50E*/

 /* FPGA program pin configuration */
-#define CFG_FPGA_PRG		0x04000000  /* FPGA program pin (ppc output) */
-#define CFG_FPGA_CLK		0x02000000  /* FPGA clk pin (ppc output)     */
-#define CFG_FPGA_DATA		0x01000000  /* FPGA data pin (ppc output)    */
-#define CFG_FPGA_INIT		0x00010000  /* FPGA init pin (ppc input)     */
-#define CFG_FPGA_DONE		0x00008000  /* FPGA done pin (ppc input)     */
+#define CFG_FPGA_PRG		0x04000000	/* FPGA program pin (ppc output) */
+#define CFG_FPGA_CLK		0x02000000	/* FPGA clk pin (ppc output)	 */
+#define CFG_FPGA_DATA		0x01000000	/* FPGA data pin (ppc output)	 */
+#define CFG_FPGA_INIT		0x00010000	/* FPGA init pin (ppc input)	 */
+#define CFG_FPGA_DONE		0x00008000	/* FPGA done pin (ppc input)	 */

 /*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */
-#if 0 /* test-only */
-#define CFG_INIT_DCACHE_CS	4	/* use cs # 4 for data cache memory    */
-
-#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#else
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM	  1
+#define CFG_TEMP_STACK_OCM	1

 /* On Chip Memory location */
 #define CFG_OCM_DATA_ADDR	0xF8000000
 #define CFG_OCM_DATA_SIZE	0x1000
 #define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
 #define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-#endif

 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
@@ -537,147 +531,147 @@
 !	are plugged in the board will be utilized as non-ECC DIMMs.
 !-----------------------------------------------------------------------
 */
-#undef	      AUTO_MEMORY_CONFIG
-#define	       DIMM_READ_ADDR 0xAB
-#define	       DIMM_WRITE_ADDR 0xAA
-
-
-#define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register	   */
-#define CPC0_BOOT    (CNTRL_DCR_BASE+0x1)  /* Chip Clock Status register   */
-#define CPC0_CR1     (CNTRL_DCR_BASE+0x2)  /* Chip Control 1 register	   */
-#define CPC0_EPRCSR  (CNTRL_DCR_BASE+0x3)  /* EMAC PHY Rcv Clk Src register*/
-#define CPC0_PLLMR1  (CNTRL_DCR_BASE+0x4)  /* PLL mode 1 register	   */
-#define CPC0_UCR     (CNTRL_DCR_BASE+0x5)  /* UART Control register	   */
-#define CPC0_SRR     (CNTRL_DCR_BASE+0x6)  /* Soft Reset register	   */
-#define CPC0_JTAGID  (CNTRL_DCR_BASE+0x7)  /* JTAG ID register		   */
-#define CPC0_SPARE   (CNTRL_DCR_BASE+0x8)  /* Spare DCR			   */
-#define CPC0_PCI     (CNTRL_DCR_BASE+0x9)  /* PCI Control register	   */
+#undef		AUTO_MEMORY_CONFIG
+#define		DIMM_READ_ADDR 0xAB
+#define		DIMM_WRITE_ADDR 0xAA
+
+
+#define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register		*/
+#define CPC0_BOOT    (CNTRL_DCR_BASE+0x1)  /* Chip Clock Status register	*/
+#define CPC0_CR1     (CNTRL_DCR_BASE+0x2)  /* Chip Control 1 register		*/
+#define CPC0_EPRCSR  (CNTRL_DCR_BASE+0x3)  /* EMAC PHY Rcv Clk Src register	*/
+#define CPC0_PLLMR1  (CNTRL_DCR_BASE+0x4)  /* PLL mode 1 register		*/
+#define CPC0_UCR     (CNTRL_DCR_BASE+0x5)  /* UART Control register		*/
+#define CPC0_SRR     (CNTRL_DCR_BASE+0x6)  /* Soft Reset register		*/
+#define CPC0_JTAGID  (CNTRL_DCR_BASE+0x7)  /* JTAG ID register			*/
+#define CPC0_SPARE   (CNTRL_DCR_BASE+0x8)  /* Spare DCR				*/
+#define CPC0_PCI     (CNTRL_DCR_BASE+0x9)  /* PCI Control register		*/

 /* Defines for CPC0_PLLMR1 Register fields */
-#define PLL_ACTIVE		   0x80000000
-#define CPC0_PLLMR1_SSCS	   0x80000000
-#define PLL_RESET		   0x40000000
-#define CPC0_PLLMR1_PLLR	   0x40000000
+#define PLL_ACTIVE		0x80000000
+#define CPC0_PLLMR1_SSCS	0x80000000
+#define PLL_RESET		0x40000000
+#define CPC0_PLLMR1_PLLR	0x40000000
    /* Feedback multiplier */
-#define PLL_FBKDIV		   0x00F00000
-#define CPC0_PLLMR1_FBDV	   0x00F00000
-#define PLL_FBKDIV_16		   0x00000000
-#define PLL_FBKDIV_1		   0x00100000
-#define PLL_FBKDIV_2		   0x00200000
-#define PLL_FBKDIV_3		   0x00300000
-#define PLL_FBKDIV_4		   0x00400000
-#define PLL_FBKDIV_5		   0x00500000
-#define PLL_FBKDIV_6		   0x00600000
-#define PLL_FBKDIV_7		   0x00700000
-#define PLL_FBKDIV_8		   0x00800000
-#define PLL_FBKDIV_9		   0x00900000
-#define PLL_FBKDIV_10		   0x00A00000
-#define PLL_FBKDIV_11		   0x00B00000
-#define PLL_FBKDIV_12		   0x00C00000
-#define PLL_FBKDIV_13		   0x00D00000
-#define PLL_FBKDIV_14		   0x00E00000
-#define PLL_FBKDIV_15		   0x00F00000
+#define PLL_FBKDIV		0x00F00000
+#define CPC0_PLLMR1_FBDV	0x00F00000
+#define PLL_FBKDIV_16		0x00000000
+#define PLL_FBKDIV_1		0x00100000
+#define PLL_FBKDIV_2		0x00200000
+#define PLL_FBKDIV_3		0x00300000
+#define PLL_FBKDIV_4		0x00400000
+#define PLL_FBKDIV_5		0x00500000
+#define PLL_FBKDIV_6		0x00600000
+#define PLL_FBKDIV_7		0x00700000
+#define PLL_FBKDIV_8		0x00800000
+#define PLL_FBKDIV_9		0x00900000
+#define PLL_FBKDIV_10		0x00A00000
+#define PLL_FBKDIV_11		0x00B00000
+#define PLL_FBKDIV_12		0x00C00000
+#define PLL_FBKDIV_13		0x00D00000
+#define PLL_FBKDIV_14		0x00E00000
+#define PLL_FBKDIV_15		0x00F00000
    /* Forward A divisor */
-#define PLL_FWDDIVA		   0x00070000
-#define CPC0_PLLMR1_FWDVA	   0x00070000
-#define PLL_FWDDIVA_8		   0x00000000
-#define PLL_FWDDIVA_7		   0x00010000
-#define PLL_FWDDIVA_6		   0x00020000
-#define PLL_FWDDIVA_5		   0x00030000
-#define PLL_FWDDIVA_4		   0x00040000
-#define PLL_FWDDIVA_3		   0x00050000
-#define PLL_FWDDIVA_2		   0x00060000
-#define PLL_FWDDIVA_1		   0x00070000
+#define PLL_FWDDIVA		0x00070000
+#define CPC0_PLLMR1_FWDVA	0x00070000
+#define PLL_FWDDIVA_8		0x00000000
+#define PLL_FWDDIVA_7		0x00010000
+#define PLL_FWDDIVA_6		0x00020000
+#define PLL_FWDDIVA_5		0x00030000
+#define PLL_FWDDIVA_4		0x00040000
+#define PLL_FWDDIVA_3		0x00050000
+#define PLL_FWDDIVA_2		0x00060000
+#define PLL_FWDDIVA_1		0x00070000
    /* Forward B divisor */
-#define PLL_FWDDIVB		   0x00007000
-#define CPC0_PLLMR1_FWDVB	   0x00007000
-#define PLL_FWDDIVB_8		   0x00000000
-#define PLL_FWDDIVB_7		   0x00001000
-#define PLL_FWDDIVB_6		   0x00002000
-#define PLL_FWDDIVB_5		   0x00003000
-#define PLL_FWDDIVB_4		   0x00004000
-#define PLL_FWDDIVB_3		   0x00005000
-#define PLL_FWDDIVB_2		   0x00006000
-#define PLL_FWDDIVB_1		   0x00007000
+#define PLL_FWDDIVB		0x00007000
+#define CPC0_PLLMR1_FWDVB	0x00007000
+#define PLL_FWDDIVB_8		0x00000000
+#define PLL_FWDDIVB_7		0x00001000
+#define PLL_FWDDIVB_6		0x00002000
+#define PLL_FWDDIVB_5		0x00003000
+#define PLL_FWDDIVB_4		0x00004000
+#define PLL_FWDDIVB_3		0x00005000
+#define PLL_FWDDIVB_2		0x00006000
+#define PLL_FWDDIVB_1		0x00007000
    /* PLL tune bits */
-#define PLL_TUNE_MASK		 0x000003FF
-#define PLL_TUNE_2_M_3		 0x00000133	/*  2 <= M <= 3		      */
-#define PLL_TUNE_4_M_6		 0x00000134	/*  3 <	 M <= 6		      */
-#define PLL_TUNE_7_M_10		 0x00000138	/*  6 <	 M <= 10	      */
-#define PLL_TUNE_11_M_14	 0x0000013C	/* 10 <	 M <= 14	      */
-#define PLL_TUNE_15_M_40	 0x0000023E	/* 14 <	 M <= 40	      */
-#define PLL_TUNE_VCO_LOW	 0x00000000	/* 500MHz <= VCO <=  800MHz   */
-#define PLL_TUNE_VCO_HI		 0x00000080	/* 800MHz <  VCO <= 1000MHz   */
+#define PLL_TUNE_MASK		0x000003FF
+#define PLL_TUNE_2_M_3		0x00000133	/*  2 <= M <= 3			*/
+#define PLL_TUNE_4_M_6		0x00000134	/*  3 <	 M <= 6			*/
+#define PLL_TUNE_7_M_10		0x00000138	/*  6 <	 M <= 10		*/
+#define PLL_TUNE_11_M_14	0x0000013C	/* 10 <	 M <= 14		*/
+#define PLL_TUNE_15_M_40	0x0000023E	/* 14 <	 M <= 40		*/
+#define PLL_TUNE_VCO_LOW	0x00000000	/* 500MHz <= VCO <=  800MHz	*/
+#define PLL_TUNE_VCO_HI		0x00000080	/* 800MHz <  VCO <= 1000MHz	*/

 /* Defines for CPC0_PLLMR0 Register fields */
    /* CPU divisor */
-#define PLL_CPUDIV		   0x00300000
-#define CPC0_PLLMR0_CCDV	   0x00300000
-#define PLL_CPUDIV_1		   0x00000000
-#define PLL_CPUDIV_2		   0x00100000
-#define PLL_CPUDIV_3		   0x00200000
-#define PLL_CPUDIV_4		   0x00300000
+#define PLL_CPUDIV		0x00300000
+#define CPC0_PLLMR0_CCDV	0x00300000
+#define PLL_CPUDIV_1		0x00000000
+#define PLL_CPUDIV_2		0x00100000
+#define PLL_CPUDIV_3		0x00200000
+#define PLL_CPUDIV_4		0x00300000
    /* PLB divisor */
-#define PLL_PLBDIV		   0x00030000
-#define CPC0_PLLMR0_CBDV	   0x00030000
-#define PLL_PLBDIV_1		   0x00000000
-#define PLL_PLBDIV_2		   0x00010000
-#define PLL_PLBDIV_3		   0x00020000
-#define PLL_PLBDIV_4		   0x00030000
+#define PLL_PLBDIV		0x00030000
+#define CPC0_PLLMR0_CBDV	0x00030000
+#define PLL_PLBDIV_1		0x00000000
+#define PLL_PLBDIV_2		0x00010000
+#define PLL_PLBDIV_3		0x00020000
+#define PLL_PLBDIV_4		0x00030000
    /* OPB divisor */
-#define PLL_OPBDIV		   0x00003000
-#define CPC0_PLLMR0_OPDV	   0x00003000
-#define PLL_OPBDIV_1		   0x00000000
-#define PLL_OPBDIV_2		   0x00001000
-#define PLL_OPBDIV_3		   0x00002000
-#define PLL_OPBDIV_4		   0x00003000
+#define PLL_OPBDIV		0x00003000
+#define CPC0_PLLMR0_OPDV	0x00003000
+#define PLL_OPBDIV_1		0x00000000
+#define PLL_OPBDIV_2		0x00001000
+#define PLL_OPBDIV_3		0x00002000
+#define PLL_OPBDIV_4		0x00003000
    /* EBC divisor */
-#define PLL_EXTBUSDIV		   0x00000300
-#define CPC0_PLLMR0_EPDV	   0x00000300
-#define PLL_EXTBUSDIV_2		   0x00000000
-#define PLL_EXTBUSDIV_3		   0x00000100
-#define PLL_EXTBUSDIV_4		   0x00000200
-#define PLL_EXTBUSDIV_5		   0x00000300
+#define PLL_EXTBUSDIV		0x00000300
+#define CPC0_PLLMR0_EPDV	0x00000300
+#define PLL_EXTBUSDIV_2		0x00000000
+#define PLL_EXTBUSDIV_3		0x00000100
+#define PLL_EXTBUSDIV_4		0x00000200
+#define PLL_EXTBUSDIV_5		0x00000300
    /* MAL divisor */
-#define PLL_MALDIV		   0x00000030
-#define CPC0_PLLMR0_MPDV	   0x00000030
-#define PLL_MALDIV_1		   0x00000000
-#define PLL_MALDIV_2		   0x00000010
-#define PLL_MALDIV_3		   0x00000020
-#define PLL_MALDIV_4		   0x00000030
+#define PLL_MALDIV		0x00000030
+#define CPC0_PLLMR0_MPDV	0x00000030
+#define PLL_MALDIV_1		0x00000000
+#define PLL_MALDIV_2		0x00000010
+#define PLL_MALDIV_3		0x00000020
+#define PLL_MALDIV_4		0x00000030
    /* PCI divisor */
-#define PLL_PCIDIV		   0x00000003
-#define CPC0_PLLMR0_PPFD	   0x00000003
-#define PLL_PCIDIV_1		   0x00000000
-#define PLL_PCIDIV_2		   0x00000001
-#define PLL_PCIDIV_3		   0x00000002
-#define PLL_PCIDIV_4		   0x00000003
+#define PLL_PCIDIV		0x00000003
+#define CPC0_PLLMR0_PPFD	0x00000003
+#define PLL_PCIDIV_1		0x00000000
+#define PLL_PCIDIV_2		0x00000001
+#define PLL_PCIDIV_3		0x00000002
+#define PLL_PCIDIV_4		0x00000003

 /* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
 #define PLLMR0_133_133_33_66_33	 (PLL_CPUDIV_1 | PLL_PLBDIV_1 |	 \
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
-			      PLL_MALDIV_1 | PLL_PCIDIV_4)
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
+				  PLL_MALDIV_1 | PLL_PCIDIV_4)
 #define PLLMR1_133_133_33_66_33	 (PLL_FBKDIV_4	|  \
-			      PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
-			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |  \
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
-			      PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6  |  \
-			      PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
-			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |	\
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
-			      PLL_MALDIV_1 | PLL_PCIDIV_4)
-#define PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8  |  \
-			      PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
-			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
-#define PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |	\
-			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
-			      PLL_MALDIV_1 | PLL_PCIDIV_2)
-#define PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10	|  \
-			      PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
-			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
+				  PLL_FWDDIVA_6 | PLL_FWDDIVB_6 |  \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_200_100_50_33	 (PLL_CPUDIV_1 | PLL_PLBDIV_2 |	 \
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
+				  PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PLLMR1_200_100_50_33	 (PLL_FBKDIV_6	|  \
+				  PLL_FWDDIVA_4 | PLL_FWDDIVB_4 |  \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_266_133_33_66_33	 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 |	\
+				  PLL_MALDIV_1 | PLL_PCIDIV_4)
+#define PLLMR1_266_133_33_66_33	 (PLL_FBKDIV_8	|  \
+				  PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
+#define PLLMR0_333_111_37_55_55	 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
+				  PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 |	\
+				  PLL_MALDIV_1 | PLL_PCIDIV_2)
+#define PLLMR1_333_111_37_55_55	 (PLL_FBKDIV_10 |  \
+				  PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
+				  PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)

 #if   (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
 /* Model HI */
@@ -696,7 +690,7 @@

 #endif /* CONFIG_NO_SERIAL_EEPROM */

-#define CONFIG_JFFS2_NAND 1 			/* jffs2 on nand support */
+#define CONFIG_JFFS2_NAND 1			/* jffs2 on nand support */
 #define CONFIG_JFFS2_NAND_DEV 0			/* nand device jffs2 lives on */
 #define CONFIG_JFFS2_NAND_OFF 0			/* start of jffs2 partition */
 #define CONFIG_JFFS2_NAND_SIZE 2*1024*1024	/* size of jffs2 partition */