Add support for CATcenter board (based on PPChameleon ME module)

CHANGELOG

@@ -2,6 +2,8 @@
 Changes since U-Boot 1.1.1:
 ======================================================================
 
+* Add support for CATcenter board (based on PPChameleon ME module)
+
 * Patch by Klaus Heydeck, 12 May 2004:
   Using external watchdog for KUP4 boards in mpc8xx/cpu.c;
   load_sernum_ethaddr() for KUP4 boards in lib_ppc/board.c;

Makefile

@@ -548,6 +548,11 @@ BUBINGA405EP_config:	unconfig
 CANBT_config:	unconfig
 	@./mkconfig $(@:_config=) ppc ppc4xx canbt esd
 
+CATcenter_config:	unconfig
+	@ echo "/* CATcenter uses PPChameleon Model ME */"  > include/config.h
+	@ echo "#define CONFIG_PPCHAMELEON_MODULE_MODEL 1" >> include/config.h
+	@./mkconfig -a $(call xtract_4xx,$@) ppc ppc4xx PPChameleonEVB dave
+
 CPCI405_config	\
 CPCI4052_config	\
 CPCI405AB_config:	unconfig

include/configs/PPChameleonEVB.h

@@ -92,9 +92,10 @@
 				CFG_CMD_EEPROM	| \
 				CFG_CMD_I2C	| \
 				CFG_CMD_IRQ	| \
+				CFG_CMD_JFFS2	| \
 				CFG_CMD_MII	| \
 				CFG_CMD_NAND	| \
-				CFG_CMD_JFFS2)
+				CFG_CMD_PCI	)
 
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
@@ -473,12 +474,6 @@
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in data cache)
  */
-#if 0 /* test-only */
-#define CFG_INIT_DCACHE_CS	4	/* use cs # 4 for data cache memory    */
-
-#define CFG_INIT_RAM_ADDR	0x40000000  /* use data cache		       */
-#define CFG_INIT_RAM_END	0x2000	/* End of used area in RAM	       */
-#else
 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 #define CFG_TEMP_STACK_OCM	1
 
@@ -487,7 +482,6 @@
 #define CFG_OCM_DATA_SIZE	0x1000
 #define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
 #define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
-#endif
 
 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
@@ -545,7 +539,7 @@
 #define CPC0_PLLMR0  (CNTRL_DCR_BASE+0x0)  /* PLL mode 0 register		*/
 #define CPC0_BOOT    (CNTRL_DCR_BASE+0x1)  /* Chip Clock Status register	*/
 #define CPC0_CR1     (CNTRL_DCR_BASE+0x2)  /* Chip Control 1 register		*/
-#define CPC0_EPRCSR  (CNTRL_DCR_BASE+0x3)  /* EMAC PHY Rcv Clk Src register*/
+#define CPC0_EPRCSR  (CNTRL_DCR_BASE+0x3)  /* EMAC PHY Rcv Clk Src register	*/
 #define CPC0_PLLMR1  (CNTRL_DCR_BASE+0x4)  /* PLL mode 1 register		*/
 #define CPC0_UCR     (CNTRL_DCR_BASE+0x5)  /* UART Control register		*/
 #define CPC0_SRR     (CNTRL_DCR_BASE+0x6)  /* Soft Reset register		*/