ARM: tegra: Make cache line size SoC specific

Currently all Tegra SoCs are assumed to have 32 byte cache lines. This
isn't true for Tegra114, however, which uses 4 Cortex-A15 cores and
therefore uses a cache line size of 64 bytes. Move the cache line size
setting to the per-SoC common configuration file.
Signed-off-by: NThierry Reding <treding@nvidia.com>
Tested-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

include/configs/tegra-common.h

@@ -17,8 +17,6 @@
 #define CONFIG_TEGRA			/* which is a Tegra generic machine */
 #define CONFIG_SYS_L2CACHE_OFF		/* No L2 cache */
 
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
 #include <asm/arch/tegra.h>		/* get chip and board defs */
 
 /*

include/configs/tegra114-common.h

@@ -18,6 +18,9 @@
 #define _TEGRA114_COMMON_H_
 #include "tegra-common.h"
 
+/* Cortex-A15 uses a cache line size of 64 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 /*
  * NS16550 Configuration
  */

include/configs/tegra20-common.h

@@ -9,6 +9,9 @@
 #define _TEGRA20_COMMON_H_
 #include "tegra-common.h"
 
+/* Cortex-A9 uses a cache line size of 32 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
 /*
  * Errata configuration
  */

include/configs/tegra30-common.h

@@ -9,6 +9,9 @@
 #define _TEGRA30_COMMON_H_
 #include "tegra-common.h"
 
+/* Cortex-A9 uses a cache line size of 32 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
 /*
  * Errata configuration
  */