diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h
index ccd68a19fd4cf2a23f656d3df46ae34e1fdc00d0..0aac14e1c366cc653be55dcac76d4f1c3779c8ae 100644
--- a/include/configs/tegra-common.h
+++ b/include/configs/tegra-common.h
@@ -17,8 +17,6 @@
 #define CONFIG_TEGRA			/* which is a Tegra generic machine */
 #define CONFIG_SYS_L2CACHE_OFF		/* No L2 cache */
 
-#define CONFIG_SYS_CACHELINE_SIZE	32
-
 #include <asm/arch/tegra.h>		/* get chip and board defs */
 
 /*
diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h
index 44e98e501952bb26284b531323aee68c9621e9c3..c3de9a999e952e3f893a6ae9efa2538e53b79e3e 100644
--- a/include/configs/tegra114-common.h
+++ b/include/configs/tegra114-common.h
@@ -18,6 +18,9 @@
 #define _TEGRA114_COMMON_H_
 #include "tegra-common.h"
 
+/* Cortex-A15 uses a cache line size of 64 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
 /*
  * NS16550 Configuration
  */
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index d5e9ee4062e4fd7b1343e761c08cdbdb47186f80..b009a316b14cd29e4389e64dfef8cbfec111bf3c 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -9,6 +9,9 @@
 #define _TEGRA20_COMMON_H_
 #include "tegra-common.h"
 
+/* Cortex-A9 uses a cache line size of 32 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
 /*
  * Errata configuration
  */
diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
index 5ac88165041595a9edd7d13f70e1b2fb61684c90..99acbfd28b29de65dad657cbd556cd523322e2c2 100644
--- a/include/configs/tegra30-common.h
+++ b/include/configs/tegra30-common.h
@@ -9,6 +9,9 @@
 #define _TEGRA30_COMMON_H_
 #include "tegra-common.h"
 
+/* Cortex-A9 uses a cache line size of 32 bytes */
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
 /*
  * Errata configuration
  */